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REVIEW 4 major objections 5 minor 59 references

200 mm Wafer-Scale Monolithic 3D Integration of Atomic Layer-Deposited Oxide Semiconductors

T0 review · 4 major / 5 minor · reviewed 2026-08-11 · deepseek-v4-flash

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Pith's one-line read This paper reports wafer-scale monolithic 3D integration of three tiers of ALD InOx transistors on 200 mm silicon, with cross-tier circuits and a simulated four-tier LLM accelerator projecting 1.4x to 2.9x speedup.

desk verdict Solid wafer-scale M3D experimental core; the CIM speedup is an unverified simulation that needs qualified language. read the letter →

arxiv 2608.09508 v1 pith:2ESRA3EP submitted 2026-08-10 physics.app-ph cond-mat.mtrl-sci

Chang Niu , Linjia Long , Luqi Zheng , Shuting Du , Jian-Yu Lin , Kisoo Nam , Zehao Lin , Chang Liu
show 4 more authors
Juanjuan Lu Haiyan Wang Haitong Li Peide D. Ye
This is my paper · ORCID
classification physics.app-phcond-mat.mtrl-sci PACS 85.30.Tv81.15.Gh85.50.-n
keywords monolithic3DintegrationatomiclayerdepositionindiumoxidetransistorsferroelectricFETBEOLcompatibilitycomputing-in-memoryLLMaccelerator200mmwafer
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper's aim is to establish that atomic-layer-deposited (ALD) indium oxide ($\mathrm{InO_x}$) transistors can serve as the building block of monolithic 3D integrated circuits: devices are grown directly on top of one another on a 200 mm silicon wafer at temperatures low enough to be back-end-of-line (BEOL) compatible, and the lower tiers keep working after each new tier is added. It reports more than 100,000 devices in three stacked tiers—ferroelectric Fe-FETs, enhancement-mode FETs, and depletion-mode FETs—with threshold-voltage standard deviation as low as $0.04$ V and average electron mobility up to $91.6\ \mathrm{cm^2\,V^{-1}s^{-1}}$. Using those devices it builds cross-tier circuits: multi-level ferroelectric nonvolatile memory, inverters, and two-transistor zero-capacitor eDRAM cells. It also projects a four-tier computing-in-memory accelerator for large language models with $1.4\times$ to $2.9\times$ speedup over a planar baseline of the same footprint. If these results hold, they establish a scalable route to vertical transistor stacking, one of the main options for continuing performance gains after planar CMOS scaling slows.

What carries the argument

The load-bearing element is the ALD $\mathrm{InO_x}$ transistor: a roughly 225 $^\circ$C deposited amorphous oxide channel whose threshold voltage can be placed wherever the designer needs it—enhancement or depletion—by choosing channel thickness and oxygen annealing. This one tunable device type replaces both pull-up and pull-down elements in an NMOS-only logic style, with depletion-mode loads and enhancement-mode switches. The same channel, paired with ferroelectric $\mathrm{HfZrO_2}$ (HZO), forms the Fe-FETs that provide nonvolatile memory. The measured device data feed a custom process design kit and an in-house model-to-chip mapping framework, which is what turns the three-tier fabrication result into the four-tier CIM accelerator projection.

What would settle it

Fabricate a four-tier InOx stack using the same process flow and run the LLM inference benchmark against the same-footprint 2D baseline; if the measured speedup falls below 1.4x or the energy-delay product is worse than the planar design, the central system-level projection fails. A simpler check is to measure whether the Tier 1 Fe-FET memory window and the Tier 2 and Tier 3 mobility survive processing of a fourth tier, since any degradation would invalidate the repeatable-stacking claim.

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Extended reading notes

Core claim

The paper's central claim is that wafer-scale monolithic 3D integration works with ALD-grown amorphous indium oxide channels. The authors show three tiers—Fe-FETs at the bottom, enhancement-mode FETs in the middle, and depletion-mode FETs on top—all fabricated on the same 200 mm wafer, and they quantify uniformity across the wafer: threshold-voltage spreads down to $0.04$ V, memory windows averaging $2.18$ V, and mobilities of $63.5$ to $91.6\ \mathrm{cm^2\,V^{-1}s^{-1}}$ depending on tier and thickness. The top-tier devices show no degradation relative to the bottom tier, which is the prerequisite for stacking more tiers. With the same three tiers, the paper demonstrates fully functional cross-tier circuits, so that logic and memory are not just co-located vertically but actually connected through inter-layer vias. The final claim is system-level: using a custom InOx process design kit and a three-dimensional design flow, a four-tier computing-in-memory accelerator for transformer-based LLMs partitions static weights into ferroelectric NVM and dynamic attention computations into eDRAM, and is projected to deliver $1.4\times$ to $2.9\times$ speedup and comparable energy-delay-product improvement over a same-footprint planar implementation.

Load-bearing premise

The load-bearing premise is that the custom simulation framework and process design kit, calibrated to measured single-tier devices, faithfully predict the performance of a four-tier chip that was never fabricated.

Editorial extensions

If this is right

  • The 200 mm process establishes ALD InOx as a candidate BEOL channel with the uniformity ($V_{th}$ sigma down to 0.04 V) and yield needed for wafer-scale manufacturing.
  • Cross-tier inverters, Fe-NVMs, and eDRAMs show that logic and memory can be interconnected vertically, not just stacked, so dense 3D systems-on-wafer become possible.
  • Because the top-tier devices show no degradation, the same process can in principle be repeated to add a fourth, fifth, or more tiers.
  • The CIM accelerator projection implies that splitting LLM workloads between static Fe-NVM and dynamic eDRAM tiers could cut inference latency by 1.4x to 2.9x relative to a planar implementation of the same footprint.
  • NMOS-only logic built from E-mode and D-mode InOx FETs gives a complete standard-cell library, so existing 2D physical-design tools can be reused for a tier-by-tier 3D flow.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The four-tier CIM speedup is a simulation result, not a measured chip; until a four-tier part is fabricated and benchmarked, the 1.4x to 2.9x range should be treated as a calibrated projection rather than a demonstrated speedup.
  • If the wafer-level uniformity and cross-tier yields reproduce in a commercial fab, ALD InOx M3D could lower the cost of 3D integration relative to wafer bonding, because it avoids high-temperature epitaxy and transfer steps.
  • The multi-level Fe-NVM cell stores n voltage levels times m polarization states; testing whether these levels stay separable under cycling, retention, and read disturb would directly probe whether that extra dimension is practical for analog in-memory computing.
  • Because the authors note the layout is not yet optimized for parasitic capacitance and coupling, reducing those parasitics should improve cross-tier circuit margins and may push the projected speedup beyond the lower bound.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 5 minor

Summary. This paper reports wafer-scale monolithic 3D (M3D) integration of three tiers of atomic-layer-deposited (ALD) InOx-based devices on 200 mm silicon wafers, including ferroelectric (Fe-FET), enhancement-mode (E-mode), and depletion-mode (D-mode) field-effect transistors. The authors present statistical characterization of over 100,000 fabricated devices, achieving threshold-voltage standard deviation as low as 0.04 V, average mobility up to 91.6 cm2/V·s, and fully functional cross-tier circuits including multi-level ferroelectric nonvolatile memories (MLFe-NVMs), inverters, and 2T0C eDRAMs. The paper also describes a four-tier 3D computing-in-memory (CIM) accelerator design for large-language-model workloads, implemented with a custom InOx process design kit and evaluated with an in-house simulation framework, with a claimed 1.4x to 2.9x speedup and comparable energy-delay-product improvements over a same-footprint 2D baseline.

Significance. If the experimental claims are confirmed, this work represents a notable advance in BEOL-compatible M3D integration. The paper's main strength is the substantial statistical data: more than 300 devices per tier across 52 dies, wafer-scale Vth maps, and functional cross-tier circuits, which support the scalability and uniformity claims. The CIM accelerator projection is forward-looking but is a simulation-based case study rather than a fabricated chip; its credibility rests on the calibration of the custom PDK and the fairness of the baseline, both of which require more transparency. The explicit limitation statement in the Conclusions is a positive sign, but the abstract's unqualified 'delivering' overstates the evidence.

major comments (4)
  1. [Abstract; 'Indium oxide multi tier computing in memory accelerator'] The 1.4–2.9x speedup claim is a projected simulation result from an in-house framework (3D-CIMlet, ref. 55) and a custom OS-PDK, not a measurement of a fabricated four-tier chip. The abstract's wording 'delivering' should be qualified as 'projected' or 'simulated' to avoid overstating the evidence. Furthermore, the Methods define the 2D baseline as 'a planar oxide-semiconductor implementation constrained to the same chip footprint, FeFET/eDRAM composition ratio, and workload-mapping strategy.' Because the 3D macro stacks four tiers, this same-footprint constraint gives the 3D design roughly four times the active device area; the speedup therefore reflects at least in part increased resource density rather than an intrinsic per-device performance advantage. Please present a resource-matched comparison (e.g., equal total device area or equal memory capacity) or explicitly discuss the sensitivity of the speedup to this baseline definition.
  2. [Methods, 'System simulation and benchmarking'] The OS-PDK is calibrated from measured devices with channel lengths of 5 um (Fig. 2e) and 100 nm (Fig. 2a), yet the CIM design is implemented at the 40 nm technology node. The scaling methodology used to extrapolate the Verilog-A models from the measured devices to 40 nm (e.g., constant-field scaling, adjustment of mobility, Vth, and parasitic capacitances) is not described. Since the projected speedup and EDP depend on these scaled parameters, please provide the scaling rules or perform a sensitivity analysis over the assumed 40 nm device parameters.
  3. [Device characterizations of multi-tier ALD InOx transistors (Fig. 3)] The statement that 'the devices fabricated on the top tiers exhibit no performance degradation compared to those on the lower tiers' is not supported by a controlled comparison. The Tier-1 devices are Fe-FETs with HZO dielectric and 400°C annealing, Tier-2 devices are E-mode FETs, and Tier-3 devices are D-mode FETs with a thicker InOx channel; these differ in device type, dielectric, and channel thickness, so the observed differences in Vth and mobility cannot isolate the effect of tier level. A direct comparison of the same device type fabricated at Tier 1 and Tier 3 would substantiate the thermal-budget compatibility claim; otherwise the claim should be softened to 'remain functional.'
  4. [Cross tier integrated circuits and memory; 'Indium oxide multi tier computing in memory accelerator'] The eDRAM is described as 'refresh-free' with 'ultra-long retention,' but no quantitative retention time is reported in the main text. The retention characteristic in Fig. 4j shows a large on/off ratio, but the time scale and the criterion for a valid logic '1' are not stated. Please report the measured retention time (e.g., the time for the read current to degrade to a specified sense margin) and specify the refresh-free condition used in the CIM design.
minor comments (5)
  1. [Fig. 2c caption] The list of sample sizes (n = 19, 19, 21, 20, ...) would be clearer if the corresponding channel lengths were explicitly mapped in the caption, as the current list is ambiguous without the figure.
  2. [Abstract and introduction] The terms 'E-mode' and 'D-mode' are used without definition; please define them as enhancement-mode (normally off) and depletion-mode (normally on) at first use.
  3. [Conclusions; Methods, 'System simulation and benchmarking'] The paper notes that heat transport cannot be inferred directly from two-dimensional circuits, yet the system-level simulation does not include thermal effects; please state the thermal assumptions (e.g., uniform temperature, no inter-tier thermal coupling) in the simulation section.
  4. [Cross tier integrated circuits and memory] The MLFe-NVM description mentions 'n x m storage levels' but does not specify the demonstrated n and m values for the multi-level operation in Figs. 4b-4c; please clarify the number of distinct levels achieved.
  5. [References] Some references have inconsistent formatting (e.g., conference series names and years); please check for consistency (e.g., refs. 35, 38, 40).

Circularity Check

1 steps flagged · score 4.0 of 10

Experimental wafer-scale M3D integration is self-contained and not circular; the abstract's CIM speedup, however, is a projection from the authors' own in-house framework and a self-defined same-footprint 2D baseline, making the system-level claim self-referential.

  1. self citation load bearing [Abstract; Section 'Indium oxide multi tier computing in memory accelerator'; Methods, 'System simulation and benchmarking']
    "The LLM accelerator is evaluated using our in-house framework55, which performs comprehensive model-to-chip mapping by processing detailed model parameters, chip configuration settings, and calibrated M3D technology libraries. ... The 2D baseline was a planar oxide-semiconductor implementation constrained to the same chip footprint, FeFET/eDRAM composition ratio, and workload-mapping strategy as the 3D design."

    The headline 'delivering 1.4x to 2.9x speedup' is not a measured hardware result: it is an output of the authors' own 3D-CIMlet framework (ref. 55, whose authors overlap with the present paper) fed by a custom InOx PDK calibrated to the authors' devices. Because the 3D macro has four vertical tiers while the 2D baseline is a planar implementation constrained to the same footprint, the comparison builds the multi-tier resource-density advantage into the baseline definition.

full rationale

The core of the paper—200 mm wafer-scale fabrication of three-tier ALD InOx FETs and Fe-FETs, >100,000 devices, statistical Vth/mobility distributions, and functional cross-tier MLFe-NVMs, inverters, and 2T0C eDRAMs—is experimental and internally consistent. Device parameters are extracted by standard constant-current and maximum-transconductance methods, and the wafer-scale maps are direct measurements, so no derivation step reduces to its inputs. The only load-bearing self-reference is the system-level CIM evaluation: the 1.4x-2.9x speedup is produced by the authors' in-house framework55 and a custom PDK, with a 2D baseline that is defined by the authors to have the same footprint but only a single planar tier. That formulation intentionally isolates 'resource density and data movement,' so the speedup is partly an artifact of the chosen baseline rather than an externally validated performance-per-resource gain. This is a self-referential modeling claim, not a mathematical tautology, and the conclusion itself asks for larger hardware demonstrations. Because the central M3D integration claim has independent experimental content, the score is 4 rather than 6 or higher.

Assumptions & free parameters 2 free parameters · 4 assumptions · 0 invented entities

No new physical particles, forces, or conserved quantities are introduced. The MLFe-NVM and CIM macro are device and circuit concepts, not new physical entities. The main hand-chosen variables are film thickness and annealing conditions, and the system projection relies on assumptions about model fidelity and baseline definition.

free parameters (2)
  • InOx channel thickness = 1.8 nm (thin, E-mode), 3.5 nm (thick, D-mode)
    Channel thickness is chosen by hand to set threshold voltage; thicker films shift Vth negative to make depletion-mode devices. This is a process knob rather than a fitted constant, but it directly tunes the reported device mode.
  • Annealing temperature = 190-300 C in O2, plus 400 C N2 for HZO activation
    Annealing conditions are varied to optimize mobility and threshold voltage; the 91.6 cm2/Vs average mobility is associated with the 300 C anneal. This is an experimental variable that affects the reported performance.
assumptions (4)
  • domain assumption ALD InOx deposited at 225 C is a high-quality channel with low defect density and good interface to HfO2 and HZO.
    The device performance and uniformity claims rest on this assumption. It is supported by the measured results but not derived from first principles.
  • domain assumption HZO on InOx crystallizes into the ferroelectric phase after 400 C N2 anneal without an interfacial layer.
    The Fe-FET memory window relies on this. The paper provides P-V loops and remanent polarization maps as supporting evidence.
  • ad hoc to paper Verilog-A models and the OS-PDK calibrated from the fabricated devices are representative of a real 40 nm 3D chip.
    The system-level speedup is computed with this assumption; the four-tier chip is not fabricated.
  • ad hoc to paper A 2D baseline with the same footprint and NVM/eDRAM composition ratio is a fair comparison for quantifying the M3D benefit.
    The 1.4x to 2.9x speedup is relative to this baseline; a different baseline definition would change the result.

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Cite this review

Pith. "Pith review of 200 mm Wafer-Scale Monolithic 3D Integration of Atomic Layer-Deposited Oxide Semiconductors." pith.science (2026). https://pith.science/paper/2ESRA3EP

@misc{pith2026260809508,
  author       = {Pith},
  title        = {Pith review of: 200 mm Wafer-Scale Monolithic 3D Integration of Atomic Layer-Deposited Oxide Semiconductors},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/2ESRA3EP}},
  note         = {Machine review of arXiv:2608.09508}
}
read the original abstract

Monolithic 3D (M3D) integration offers a pathway to overcome the scaling limits of conventional silicon complementary metal-oxide-semiconductor (CMOS) technology by extending dense vertical stacking of multifunctional logic and memory devices. Here, we demonstrate wafer-scale M3D integration of three tiers of atomic-layer-deposited (ALD) indium oxide (InOx)-based devices (>100,000 fabricated), including ferroelectric, enhancement-mode, and depletion-mode field-effect transistors, on 200 mm silicon wafers. We achieve threshold voltage standard deviation as low as 0.04 V, average electron mobility up to 91.6 cm2V-1s-1, and fully functional cross-tier circuits. A four-tier 3D computing-in-memory (CIM) accelerator targeting large language model workloads is developed using a custom InOx process design kit, delivering 1.4x to 2.9x speedup and comparable energy-delay product improvements over 2D baselines. These results establish ALD InOx M3D integration as a scalable and CMOS-compatible platform for next-generation artificial intelligence hardware and advanced electronics.

Figures

Figures reproduced from arXiv: 2608.09508 by the authors.

Figure 1
Figure 1. Multi-tier ALD InOx integration on 200 mm wafers. a, Schematic illustration of the M3D integration of ALD InOx-based devices, including ferroelectric, E-mode, and D￾mode FETs across three tiers. b, Optical image of a 200 mm silicon wafer with integrated multi-tier ALD InOx devices. c, Fabrication process flow for the wafer-scale M3D integration, showing the sequential stacking of three transistor tiers using BEOL￾co… view at source ↗
Figure 2
Figure 2. Process-dependent electrical performance of ALD InOx on 200 mm wafers. a￾b, Transfer and output characteristics of InOx FETs, showing high on-current (1000 μA/μm) in short-channel devices and excellent saturation behavior in long channel devices. c-d, Channel length dependence of the transfer characteristics, demonstrating the scalability of InOx FETs. The sample sizes were n = 19, 19, 21, 20, 19, 20, 18, 16, 20, 20… view at source ↗
Figure 3
Figure 3. Device characterizations of multi-tier ALD InOx transistors on a 200 mm wafer. a-c, Electrical performance of Tier 1 Fe-FETs: transfer characteristics (a), statistical distributions of extracted parameters (b), and spatial color map of threshold voltages across the wafer (c). d-f, Electrical performance of Tier 2 E-mode FETs: transfer characteristics (d), extracted device statistics (e), and threshold voltage mappin… view at source ↗
Figures from the paper (2 more)
Figure 4
Figure 4. Figure 4: Cross-tier multifunctional vertical integrated logic and memory on a 200 mm wafer. a, Schematic illustration of cross-tier logic and memory integration, including Fe￾NVMs, inverters, and 2T0C eDRAM. b-c, Multi-level operation of a Fe-NVM cell under opposite ferroelectr…
Figure 5
Figure 5. Figure 5: InOx-based 3D multi-tier computing-in-memory (CIM) LLM accelerator design and benchmarking. a, Schematic of the proposed multi-tier 3D CIM macro, featuring four tiers with scalability for additional stacking. b, Customized 3D-IC design flow from RTL to GDS using PDK ba…

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Reviewed August 11, 2026 · model on record in the stance chip above.