Paper Citation Record · LEDGER

RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution

As of 10 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 11 inbound Pith citation observations for arXiv:2312.08617.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2312.08617 v5

Coverage vector

measured 0 of 0 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links

measured 11 of 11 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-10T06:31:04.303077+00:00

measured 11 of 11 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-08-07T10:34:04.396377Z

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: arxiv_reference, observed 2026-07-02T11:26:54.353732Z

Reference resolution

0 of 0 outbound references displayed

verified exact0
verified fuzzy0
unresolved0
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

No outbound reference observations are available for this paper version.

Pith citing papers

Observation 267bfea6-d13c-41b0-bed5-3bfdef747ef2 · inbound

QiMeng: Fully Automated Hardware and Software Design for Processor Chip cites this paper.

QiMeng: Fully Automated Hardware and Software Design for Processor Chip RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution

Reference 41

Resolution: unresolved; no resolver link, observed 2026-08-07T10:34:04.396377Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation ed1710f7-c9ff-4636-8fab-3ddaa7089255 · inbound

VeriOpt: PPA-Aware High-Quality Verilog Generation via Multi-Role LLMs cites this paper.

VeriOpt: PPA-Aware High-Quality Verilog Generation via Multi-Role LLMs RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution

Reference 5

Resolution: unresolved; no resolver link, observed 2026-08-06T15:51:34.431027Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 84c0b0b9-c2a6-4899-9341-9ccb86a0d787 · inbound

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs cites this paper.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution

Reference 4

Resolution: unresolved; no resolver link, observed 2026-08-06T15:19:52.253221Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 0fe74f83-553e-4f91-a8cb-5a962da28f51 · inbound

SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits cites this paper.

SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution

Reference 3

Resolution: unresolved; no resolver link, observed 2026-08-05T16:00:39.439485Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 96b644a8-e289-44c1-8858-c40690391dc6 · inbound

MACO: A Multi-Agent LLM Framework for Automated CGRA Hardware/Software Co-Design cites this paper.

MACO: A Multi-Agent LLM Framework for Automated CGRA Hardware/Software Co-Design RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution

Reference 18

Resolution: unresolved; no resolver link, observed 2026-08-04T16:31:32.458167Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 0b0a7f71-b9d6-48b5-a3cc-0707e679fa7f · inbound

ChipCraftBrain: Validation-First RTL Generation via Multi-Agent Orchestration cites this paper.

ChipCraftBrain: Validation-First RTL Generation via Multi-Agent Orchestration RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution

Reference 6

Resolution: verified exact; arxiv_id, observed 2026-05-11T13:36:08.347789Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation c65e14eb-20fb-4c0f-be4f-0237e24b7389 · inbound

RefEvo: Agentic Design with Co-Evolutionary Verification for Agile Reference Model Generation cites this paper.

RefEvo: Agentic Design with Co-Evolutionary Verification for Agile Reference Model Generation RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution

Reference 9

Resolution: verified exact; arxiv_id, observed 2026-05-11T22:11:14.615391Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation d9df277e-bc8c-4616-a08f-81057eef75f1 · inbound

Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generation cites this paper.

Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generation RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution

Reference 10

Resolution: verified exact; arxiv_id, observed 2026-06-29T18:53:51.265943Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 848f8f92-28ff-4b6f-9ebc-09323e5031a6 · inbound

Alpha-RTL: Test-Time Training for RTL Hardware Optimization cites this paper.

Alpha-RTL: Test-Time Training for RTL Hardware Optimization RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution

Reference 3

Resolution: verified exact; arxiv_id, observed 2026-07-02T07:06:44.132730Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 5b882b5e-8538-47dd-aa4a-26ae5034d4a2 · inbound

RTLScout: Joint Agentic Code and Synthesis Optimization for Efficient Digital Circuits cites this paper.

RTLScout: Joint Agentic Code and Synthesis Optimization for Efficient Digital Circuits RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution

Reference 19

Resolution: verified exact; arxiv_id, observed 2026-07-02T11:26:54.355587Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 439ecdb6-d94c-4c47-ac8e-1f8e756ccc81 · inbound

Agentic Hardware Design as Repository-Level Code Evolution cites this paper.

Agentic Hardware Design as Repository-Level Code Evolution RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution

Reference 11

Resolution: metadata mismatch; arxiv_id, observed 2026-07-01T18:45:58.292383Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.