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arxiv: 1907.00942 · v1 · pith:5FKEE43Pnew · submitted 2019-07-01 · ⚛️ physics.app-ph

Cryogenic Memory Architecture Integrating Spin Hall Effect based Magnetic Memory and Superconductive Cryotron Devices

Minh-Hai Nguyen , Guilhem J. Ribeill , Martin Gustafsson , Shengjie Shi , Sriharsha V. Aradhya , Andrew P. Wagner , Leonardo M. Ranzani , Lijun Zhu
show 14 more authors
Reza Baghdadi3 Brenden Butters Emily Toomey Marco Colangelo Patrick A. Truitt Amir Jafari-Salim David McAllister Daniel Yohannes Sean R. Cheng Rich Lazarus Oleg Mukhanov Karl K. Berggren Robert A. Buhrman Graham E. Rowlands Thomas A. Ohki
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Pith reviewed 2026-05-25 11:11 UTC · model grok-4.3

classification ⚛️ physics.app-ph
keywords cryogenic memoryspin Hall effectmagnetic tunnel junctioncryotronsuperconducting logicnon-volatile memory4K operation
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The pith

Cryogenic memory cells integrate spin Hall magnetic junctions with cryotron selectors to achieve 8 pJ writes at 4 K with low error rates.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper shows that combining spin Hall effect driven magnetic tunnel junctions with superconducting cryotrons creates functional cryogenic memory cells. This approach tackles the memory bottleneck in cryogenic computing systems that use Josephson junction logic, which currently lack efficient high-density memory at 4 K. Demonstrations include a 4x4 array with write energies of about 8 pJ, 30% overhead, and error rates under 10 to the -6. Such cells could support the memory needs of exascale cryogenic computers and quantum control electronics if the approach scales. The work positions this hybrid technology as a step toward power-efficient memory operating at cryogenic temperatures.

Core claim

We demonstrate an array of cryogenic memory cells consisting of a non-volatile three-terminal magnetic tunnel junction element driven by the spin Hall effect, combined with a superconducting heater-cryotron bit-select element. The write energy of these memory elements is roughly 8 pJ with a bit-select element, designed to achieve a minimum overhead power consumption of about 30%. Individual magnetic memory cells measured at 4 K show reliable switching with write error rates below 10^{-6}, and a 4x4 array can be fully addressed with bit select error rates of 10^{-6}.

What carries the argument

The hybrid cryogenic memory cell consisting of a spin Hall effect three-terminal magnetic tunnel junction combined with a superconducting heater-cryotron bit-select element, which provides non-volatile data storage and selective bit addressing at cryogenic temperatures.

If this is right

  • The architecture targets energy and performance specifications for superconducting high performance and quantum computing control systems.
  • Write energy of roughly 8 pJ with 30% overhead from the bit-select element.
  • Reliable switching demonstrated with write error rates below 10^{-6} for individual cells.
  • A 4x4 array is fully addressed with bit select error rates of 10^{-6}.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Scaling to larger arrays may introduce thermal and wiring challenges that increase the effective overhead beyond 30%.
  • This could be extended by testing integration with Josephson junction logic circuits for full system performance.
  • The non-volatility allows retention without power, which may benefit power gating in cryogenic systems.

Load-bearing premise

The measured error rates and energy figures from small test arrays at 4 K will remain acceptable when integrated into larger memory banks with full cryogenic wiring, thermal loading, and system-level control electronics.

What would settle it

Measuring write error rates above 10^{-6} or significantly higher energy consumption in a scaled-up array or with complete system wiring would falsify the practicality for larger cryogenic memory.

Figures

Figures reproduced from arXiv: 1907.00942 by Amir Jafari-Salim, Andrew P. Wagner, Daniel Yohannes, David McAllister, Emily Toomey, Graham E. Rowlands, Guilhem J. Ribeill, Karl K. Berggren, Leonardo M. Ranzani, Lijun Zhu, Marco Colangelo, Martin Gustafsson, Minh-Hai Nguyen, Oleg Mukhanov, Patrick A. Truitt, Reza Baghdadi3 Brenden Butters, Rich Lazarus, Robert A. Buhrman, Sean R. Cheng, Shengjie Shi, Sriharsha V. Aradhya, Thomas A. Ohki.

Figure 3
Figure 3. Figure 3: Characterisation of a standalone hTron device. (a) Voltage drops (right axis) over the hTron gate and channel as functions of applied currents (left axis). Switching occurs at 𝐼J K = 87 µA. (b) Distribution of the gate critical current obtained by repeating the bias sequence in panel (a) 100 times, and its cumulative probability of switching to the normal state (right axis). (c) Probabilities for the gate … view at source ↗
read the original abstract

One of the most challenging obstacles to realizing exascale computing is minimizing the energy consumption of L2 cache, main memory, and interconnects to that memory. For promising cryogenic computing schemes utilizing Josephson junction superconducting logic, this obstacle is exacerbated by the cryogenic system requirements that expose the technology's lack of high-density, high-speed and power-efficient memory. Here we demonstrate an array of cryogenic memory cells consisting of a non-volatile three-terminal magnetic tunnel junction element driven by the spin Hall effect, combined with a superconducting heater-cryotron bit-select element. The write energy of these memory elements is roughly 8 pJ with a bit-select element, designed to achieve a minimum overhead power consumption of about 30%. Individual magnetic memory cells measured at 4 K show reliable switching with write error rates below $10^{-6}$, and a 4x4 array can be fully addressed with bit select error rates of $10^{-6}$. This demonstration is a first step towards a full cryogenic memory architecture targeting energy and performance specifications appropriate for applications in superconducting high performance and quantum computing control systems, which require significant memory resources operating at 4 K.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

1 major / 2 minor

Summary. The manuscript presents an experimental demonstration of a 4x4 array of cryogenic memory cells integrating non-volatile three-terminal magnetic tunnel junctions driven by the spin Hall effect with superconducting heater-cryotron bit-select elements. Measurements at 4 K report write energies of roughly 8 pJ per cell (including bit-select), write error rates below 10^{-6} for individual cells, and bit-select error rates of 10^{-6} for the full array. The work frames this as an initial step toward memory solutions for superconducting high-performance and quantum computing systems.

Significance. If the reported error rates and energy values are supported by the experimental data and methods in the full manuscript, the result provides a concrete hybrid device platform that combines MTJ non-volatility with cryotron selection. This addresses a recognized gap in cryogenic memory density and efficiency. The experimental realization on a small array, rather than simulation alone, is a strength; the work does not claim to have solved system-level scaling.

major comments (1)
  1. [Abstract] Abstract: the phrase 'designed to achieve a minimum overhead power consumption of about 30%' is presented without indicating whether this figure is obtained from measurements on the 4x4 array or from separate modeling; if the latter, it must be clearly separated from the experimental claims to avoid implying system-level validation that is not shown.
minor comments (2)
  1. The scaling discussion in the introduction and conclusion should explicitly note that thermal loading, interconnect resistance, and control electronics effects have not been measured beyond the 4x4 prototype; this is consistent with the 'first step' framing but should be stated directly.
  2. Ensure that all reported error rates include the number of trials, confidence intervals, and any observed failure modes so that the <10^{-6} figures can be evaluated for statistical robustness.

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for their careful reading of the manuscript and for the constructive comment on the abstract. We address the point below and will revise the manuscript to improve clarity.

read point-by-point responses

  1. Referee: [Abstract] Abstract: the phrase 'designed to achieve a minimum overhead power consumption of about 30%' is presented without indicating whether this figure is obtained from measurements on the 4x4 array or from separate modeling; if the latter, it must be clearly separated from the experimental claims to avoid implying system-level validation that is not shown.

    Authors: We agree that the current phrasing in the abstract is ambiguous and could be misread as implying a measured system-level result. The 30% overhead figure is a design target derived from separate circuit modeling of the heater-cryotron bit-select element (based on its resistance and bias conditions), not from direct power measurements on the fabricated 4x4 array. The experimental results reported are strictly the ~8 pJ write energy per cell (including the bit-select element) and the error-rate statistics. We will revise the abstract to explicitly attribute the 30% figure to modeling and to separate it from the experimental claims. revision: yes

Circularity Check

0 steps flagged

No circularity: experimental demonstration only

full rationale

The paper reports direct experimental measurements on fabricated 4x4 arrays of SHE-MTJ + heater-cryotron cells at 4 K, including write energy (~8 pJ), write error rates (<10^{-6}), and bit-select error rates (10^{-6}). No equations, fitted models, predictions, or derivation chains are present in the abstract or described results. The central claims are empirical observations from test structures, not reductions of outputs to prior fitted inputs or self-citations. Scaling assumptions to larger systems are noted as untested but do not constitute circularity in any claimed derivation.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

This is an experimental device demonstration paper. No mathematical derivations, fitted parameters, or new postulated entities appear in the abstract.

pith-pipeline@v0.9.0 · 5846 in / 1133 out tokens · 24421 ms · 2026-05-25T11:11:53.149754+00:00 · methodology

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Reference graph

Works this paper leans on

42 extracted references · 42 canonical work pages

  1. [1]

    S., Ripple, A

    Holmes, D. S., Ripple, A. L. & Manheimer, M. A. Energy-Efficient Superconducting Computing—Power Budgets and Requirements. IEEE Trans. Appl. Supercond. 23, 1701610 (2013)

    work page 2013

  2. [2]

    Mukhanov, O. A. Energy-Efficient single flux quantum technology. IEEE Trans. Appl. Supercond. 21, 760 (2011)

    work page 2011

  3. [3]

    Merolla, P. A. et al. A million spiking-neuron integrated circuit with a scalable communication network and interface. Science 345, 668 (2014)

    work page 2014

  4. [4]

    Davies, M. et al. Loihi: A neuromorphic manycore processor with on-chip learning. IEEE Micro 38, 82–99 (2018)

    work page 2018

  5. [5]

    P., Herr, A

    Herr, Q. P., Herr, A. Y., Oberg, O. T. & Ioannidis, A. G. Ultra-low-power superconductor logic. J. Appl. Phys. 109, 103903 (2011)

    work page 2011

  6. [6]

    Tolpygo, S. K. et al. 20 kA/cm 2 Process development for superconducting integrated circuits with 80 GHz clock frequency. IEEE Trans. Appl. Supercond. 17, 946 (2007)

    work page 2007

  7. [7]

    & Hidaka, M

    Nagasawa, S., Hinode, K., Satoh, T., Kitagawa, Y. & Hidaka, M. Design of all-dc-powered high-speed single flux quantum random access memory based on a pipeline structure for memory cell arrays. Supercond. Sci. Technol. 19, S325 (2006)

    work page 2006

  8. [8]

    Liu, Q. et al. Latency and power measurements on a 64-kb hybrid Josephson-CMOS memory. IEEE Trans. Appl. Supercond. 17, 526 (2007)

    work page 2007

  9. [9]

    Ware, F. et al. Do superconducting processors really need cryogenic memories? The case for cold DRAM. in Proc. Int’l Sym. On Mem. Sys. 183 (2017). doi:10.1145/3132402.3132424

    work page doi:10.1145/3132402.3132424 2017

  10. [10]

    Tanaka, M. et al. Josephson-CMOS Hybrid Memory with Nanocryotrons. IEEE Trans. Appl. Supercond. 27, 1800904 (2017)

    work page 2017

  11. [11]

    Zhao, Q. Y. et al. A compact superconducting nanowire memory element operated by nanowire cryotrons. Supercond. Sci. Technol. 31, 035009 (2018)

    work page 2018

  12. [12]

    N., Toomey, E

    McCaughan, A. N., Toomey, E. A., Schneider, M. L., Berggren, K. K. & Nam, S. W. A kinetic-inductance-based superconducting memory element with shunting and sub-nanosecond write times. Supercond. Sci. Technol. 32, 015005 (2018)

    work page 2018

  13. [13]

    K., Polyakov, Y

    Semenov, V. K., Polyakov, Y. A., Tolpygo, S. K. & Member, S. Very Large Scale Integration of Josephson-Junction- Based Superconductor Random Access Memories. IEEE Trans. Appl. Supercond. 29, 1302809 (2019)

    work page 2019

  14. [14]

    Butters, B. A. Development of a scalable superconducting memory. (Massachusetts Institute of Technology, 2018)

    work page 2018

  15. [15]

    Rowlands, G. E. et al. A cryogenic spin-torque memory element with precessional magnetization dynamics. Sci. Rep. 9, 803 (2019)

    work page 2019

  16. [16]

    Relm, L. et al. Sub-nanosecond switching in a cryogenic spin-torque spin-valve memory element with a dilute permalloy free layer. Appl. Phys. Lett. 114, 212402 (2019)

    work page 2019

  17. [17]

    Rowlands, G. E. et al. Nanosecond reversal of three-terminal spin Hall effect memories sustained at cryogenic temperatures. (Submitted) (2019)

    work page 2019

  18. [18]

    Vernik, I. V. et al. Magnetic josephson junctions with superconducting interlayer for cryogenic memory. IEEE Trans. Appl. Supercond. 23, 1701208 (2013)

    work page 2013

  19. [19]

    Dayton, I. M. et al. Experimental Demonstration of a Josephson Magnetic Memory Cell with a Programmable pi-Junction. IEEE Magn. Lett. 9, 3301905 (2018)

    work page 2018

  20. [20]

    Liu, L. et al. Spin-torque switching with the giant spin Hall effect of tantalum. Science 336, 555 (2012)

    work page 2012

  21. [21]

    V., Rowlands, G

    Aradhya, S. V., Rowlands, G. E., Oh, J., Ralph, D. C. & Buhrman, R. A. Nanosecond-Timescale Low Energy Switching of In-Plane Magnetic Tunnel Junctions through Dynamic Oersted-Field-Assisted Spin Hall Effect. Nano Lett. 16, 5987 (2016)

    work page 2016

  22. [22]

    McCaughan, A. N. & Berggren, K. K. A superconducting-nanowire three-terminal electrothermal device. Nano Lett. 14, 5748 (2014)

    work page 2014

  23. [23]

    A., Mukhanov, O

    Ohki, T. A., Mukhanov, O. & Kirichenko, A. Magnetic RAM array architecture. U.S. Patent. US 9,747,9, (2017)

    work page 2017

  24. [24]

    Dyakonov, M. I. & Perel, V. I. Current-induced spin orientation of electrons in semiconductors. Phys. Leters 35A, 459 (1971)

    work page 1971

  25. [25]

    Spin Hall Effect

    Hirsch, J. Spin Hall Effect. Phys. Rev. Lett. 83, 1834 (1999)

    work page 1999

  26. [26]

    Spin hall effect in the presence of spin diffusion

    Zhang, S. Spin hall effect in the presence of spin diffusion. Phys. Rev. Lett. 85, 393 (2000)

    work page 2000

  27. [27]

    Slonczewski, J. C. Current-driven excitation of magnetic multilayers. J. Magn. Magn. Mater. 159, L1–L7 (1996)

    work page 1996

  28. [28]

    Mihai Miron, I. et al. Current-driven spin torque induced by the Rashba effect in a ferromagnetic metal layer. Nat. Mater. 9, 230 (2010)

    work page 2010

  29. [29]

    Gurevich, A. V. & Mints, R. G. Self-heating in normal metals and superconductors. Rev. Mod. Phys. 59, 941–999 (1987)

    work page 1987

  30. [30]

    Liu, L., Moriyama, T., Ralph, D. C. & Buhrman, R. A. Spin-Torque Ferromagnetic Resonance Induced by the Spin Hall Effect. Phys. Rev. Lett. 106, 036601 (2011)

    work page 2011

  31. [31]

    Pai, C.-F. et al. Spin transfer torque devices utilizing the giant spin Hall effect of tungsten. Appl. Phys. Lett. 101, 122404 (2012)

    work page 2012

  32. [32]

    Nguyen, M.-H., Zhao, M., Ralph, D. C. & Buhrman, R. A. Enhanced spin Hall torque efficiency in Pt100−xAlx and Pt100−xHfx alloys arising from the intrinsic spin Hall effect. Appl. Phys. Lett. 108, 242407 (2016)

    work page 2016

  33. [33]

    Laczkowski, P. et al. Experimental evidences of a large extrinsic spin Hall effect in AuW alloy. Appl. Phys. Lett. 104, 142403 (2014)

    work page 2014

  34. [34]

    Zhu, L., Ralph, D. C. & Buhrman, R. A. Highly Efficient Spin-Current Generation by the Spin Hall Effect in Au_1-xPt_x. Phys. Rev. Appl. 10, 031001 (2018)

    work page 2018

  35. [35]

    Nguyen, M.-H. et al. Enhancement of the anti-damping spin torque efficacy of platinum by interface modification. Appl. Phys. Lett. 106, 222402 (2015)

    work page 2015

  36. [36]

    Nguyen, M. H. et al. Efficient switching of 3-terminal magnetic tunnel junctions by the giant spin Hall effect of Pt85Hf15alloy. Appl. Phys. Lett. 112, 062404 (2018)

    work page 2018

  37. [37]

    Sun, J. Z. Spin-current interaction with a monodomain magnetic body: A model study. Phys. Rev. B 62, 570 (2000)

    work page 2000

  38. [38]

    H., Katine, J

    Koch, R. H., Katine, J. A. & Sun, J. Z. Time-resolved reversal of spin-transfer switching in a nanomagnet. Phys. Rev. Lett. 92, 088302 (2004)

    work page 2004

  39. [39]

    Han, J. et al. Room-Temperature Spin-Orbit Torque Switching Induced by a Topological Insulator. Phys. Rev. Lett. 119, 077702 (2017)

    work page 2017

  40. [40]

    V., Ralph, D

    Shi, S., Ou, Y., Aradhya, S. V., Ralph, D. C. & Buhrman, R. A. Fast, low-current spin-orbit torque switching of magnetic tunnel junctions through atomic modifications of the free layer interfaces. Phys. Rev. Appl. 9, 011002 (2018)

    work page 2018

  41. [41]

    Clem, J. R. & Berggren, K. K. Geometry-dependent critical currents in superconducting nanocircuits. Phys. Rev. B 84, 174510 (2011)

    work page 2011

  42. [42]

    Manheimer, M. A. Cryogenic computing complexity program: Phase 1 introduction. IEEE Trans. Appl. Supercond. 25, 1301704 (2015)

    work page 2015