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CoFHEE: A Co-processor for Fully Homomorphic Encryption Execution (Extended Version)

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arxiv 2204.08742 v3 pith:6EIN5LQX submitted 2022-04-19 cs.CR cs.AR

classification cs.CRcs.AR
keywords cofheepolynomialcomputationencryptionexecutionfullyhomomorphicasic
verification ladder T0 review T1 audit T2 compute T3 formal

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abstract

The migration of computation to the cloud has raised concerns regarding the security and privacy of sensitive data, as their need to be decrypted before processing, renders them susceptible to potential breaches. Fully Homomorphic Encryption (FHE) serves as a countermeasure to this issue by enabling computation to be executed directly on encrypted data. Nevertheless, the execution of FHE is orders of magnitude slower compared to unencrypted computation, thereby impeding its practicality and adoption. Therefore, enhancing the performance of FHE is crucial for its implementation in real-world scenarios. In this study, we elaborate on our endeavors to design, implement, fabricate, and post-silicon validate CoFHEE, a co-processor for low-level polynomial operations targeting Fully Homomorphic Encryption execution. With a compact design area of $12mm^2$, CoFHEE features ASIC implementations of fundamental polynomial operations, including polynomial addition and subtraction, Hadamard product, and Number Theoretic Transform, which underlie most higher-level FHE primitives. CoFHEE is capable of natively supporting polynomial degrees of up to $n = 2^{14}$ with a coefficient size of 128 bits, and has been fabricated and silicon-verified using 55nm CMOS technology. To evaluate it, we conduct performance and power experiments on our chip, and compare it to state-of-the-art software implementations and other ASIC designs.

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Cited by 1 Pith paper

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. EFFACT: A Highly Efficient Full-Stack FHE Acceleration Platform

    cs.CR 2025-04 conditional novelty 6.0 of 10

    EFFACT combines a streaming compiler, circuit-level function-unit reuse, and compact NTT and automorphism units to accelerate FHE workloads efficiently at small SRAM size.

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