FPGA-based Implementation of a New Data Frame Correction System for Merging Units

With today's increasing demand for digital devices in Substation Automation Systems (SAS) based on the IEC61850 standard, the measured data error due to the synchronization problem should be considered as a significant problem in digitalized SAS. Although time tagging and mathematical methods have been proposed to alleviate this problem, they require a massive amount of calculations and elaborations. To develop a solution for both problems of the data error and the massive computation, in this paper, we propose a data frame correction (DFC) system with a new method of data shift computation as a data correction method implemented as a hardware accelerator on FPGA. Compared to the state-of-the-art DFC systems, the results show that the proposed DFC system can achieve data correction with up to 99.6% fewer hardware resources utilization and fulfills 9x calculation speed while maintaining IEC61850 required accuracy in 2.1ms.