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VeriGen: A Large Language Model for Verilog Code Generation

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arxiv 2308.00708 v1 pith:GGVUXYUE submitted 2023-07-28 cs.PL cs.LGcs.SE

Shailja Thakur , Baleegh Ahmad , Hammond Pearce , Benjamin Tan , Brendan Dolan-Gavitt , Ramesh Karri , Siddharth Garg This is my paper · ORCID
classification cs.PLcs.LGcs.SE
keywords verilogcodemodellanguagellmsproblemdesignfine-tuned
verification ladder T0 review T1 audit T2 compute T3 formal

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In this study, we explore the capability of Large Language Models (LLMs) to automate hardware design by generating high-quality Verilog code, a common language for designing and modeling digital systems. We fine-tune pre-existing LLMs on Verilog datasets compiled from GitHub and Verilog textbooks. We evaluate the functional correctness of the generated Verilog code using a specially designed test suite, featuring a custom problem set and testing benches. Here, our fine-tuned open-source CodeGen-16B model outperforms the commercial state-of-the-art GPT-3.5-turbo model with a 1.1% overall increase. Upon testing with a more diverse and complex problem set, we find that the fine-tuned model shows competitive performance against state-of-the-art gpt-3.5-turbo, excelling in certain scenarios. Notably, it demonstrates a 41% improvement in generating syntactically correct Verilog code across various problem categories compared to its pre-trained counterpart, highlighting the potential of smaller, in-house LLMs in hardware design automation.

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Cited by 4 Pith papers

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    An open-source LLM-based pipeline repaired a simple ALU bug with k-induction proof, but succeeded on only 1 of 6 benchmarks.

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