REVIEW 2 major objections 5 minor 1 cited by
Croc: An End-to-End Open-Source Extensible RISC-V MCU Platform to Democratize Silicon
T0 review · 2 major / 5 minor · reviewed 2026-08-08 · deepseek-v4-flash
Pith's one-line read Croc is an open-source RISC-V MCU platform that takes student designs from RTL to tapeout.
desk verdict A solid educational chip-design platform with a real student tapeout, but 'silicon-proven' is one overstatement until the MLEM chip is actually tested. read the letter →
The pith
A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.
The reading
What carries the argument
The load-bearing mechanism is the Croc platform as a complete minimal starting point: one repository holding the RTL, software setup, and documentation, plus a streamlined open-source implementation flow in which a new lightweight SystemVerilog frontend for the synthesis tool replaces a complicated preprocessing step. The CVE2 core is the workhorse; its single-cycle tightly coupled memory banks let it retire one instruction per cycle, and its RV32I(EMC) base leaves room for students to add custom instructions. A containerized toolchain bundles the open EDA tools and the open PDK, so every student works in the same reproducible environment, and an FPGA flow provides low-cost verification before tapeout.
What would settle it
Take the fabricated demonstrator chip from the reported tapeout, load the same firmware used in RTL simulation, and exercise the UART, GPIO, timer, and LED-controller peripherals at the reported 80 MHz operating point; if the silicon does not boot or peripheral traffic is corrupted, the claim that Croc is silicon-proven for classroom tapeouts fails.
Extended reading notes
Core claim
Croc is a minimal RISC-V microcontroller system-on-chip built entirely from open, production-ready SystemVerilog blocks: a single-issue in-order CVE2 core implementing RV32I(EMC), a tightly coupled interconnect, two SRAM banks, a small set of peripherals, and a user domain where students can attach their own accelerators or instruction-set extensions. The paper's central claim is that this design, together with a documented, containerized open-source synthesis and place-and-route flow and an open 130 nm PDK, is enough for a small student team to complete a physical chip implementation. The demonstrator MLEM confirms the claim at the layout level: a 5 mm², 350-thousand-gate-equivalent chip at 56% density, closing timing at 80 MHz under typical conditions, implemented in under an hour on a single machine with less than 8 GiB of memory.
Load-bearing premise
The central claim assumes the fabricated MLEM chip actually works as designed: the paper reports a successful physical implementation and tapeout but provides no post-silicon test measurements.
Editorial extensions
If this is right
- A two-person student team can turn RTL into a physical 130 nm chip layout in eight weeks using only open-source tools and an open PDK.
- A university course can assign real tapeouts at scale: the paper reports an upcoming class of 80 students producing up to 40 ASIC layouts and up to five student-led SoC tapeouts.
- Students can experiment with custom ISA extensions and accelerators without leaving the mainline flow, because the baseline design is small enough to close timing quickly.
- The same platform doubles as a starting kit for commercial RISC-V MCU products in security, control, or edge machine learning, since it is built on production-ready IP cores.
- Because the PDK and tools are open and the teaching material is openly licensed, the course can be replicated outside the host institution.
Reading between the lines
- If the reported eight-week timeline holds generally, the bottleneck in student chip design shifts from tool access and licensing to verification and design bring-up, so course time may be better spent on those skills.
- The paper's evidence stops at tapeout, so a direct next step is post-silicon bring-up of the fabricated demonstrator; functional measurements would turn 'tapeout demonstrated' into 'silicon verified'.
- The same flow should transfer to other open PDK nodes and to larger student chips; whether the one-hour, 8 GiB implementation budget scales to multi-core designs is an open question.
- An open analog PDK layer, if added, would let the same educational model cover sensors or radio front ends, widening the hands-on scope beyond digital logic.
Signed reviews
Editorial analysis
A structured set of objections, weighed in public.
Referee Report
Summary. The paper presents Croc, an open-source RISC-V microcontroller platform designed for hands-on VLSI education. The platform includes a minimal MCU built around the CVE2 core, a set of peripherals, a user domain for student extensions, and a streamlined open-source RTL-to-GDS implementation flow using Yosys, OpenROAD, and the IHP 130 nm open PDK. The authors report an eight-week tapeout of a demonstrator chip, MLEM, by two bachelor students, and they plan to use Croc in an ETH Zurich VLSI course for up to 80 students. The paper claims that Croc is 'silicon-proven' and that the tapeout demonstrates the platform's viability for education.
Significance. If the central claims are substantiated, this work is a valuable contribution to open-source hardware education. The platform is fully open, built on industry-maintained IPs (CVE2), and is accompanied by lecture notes and exercises under a Creative Commons license. The reported tapeout of MLEM in an open PDK by two students in eight weeks is strong evidence that the RTL-to-GDS flow is accessible and reproducible. Practical details such as the sub-hour implementation run with a memory footprint below 8 GiB are concrete and useful for academic settings. However, the paper's most prominent claim—that Croc is 'silicon-proven'—is not supported by functional post-silicon measurements, which weakens the significance until such evidence is supplied or the claim is appropriately qualified.
major comments (2)
- [MLEM Student Tapeout and Contributions list] The paper claims that the MLEM tapeout 'silicon-proves' the SoC platform, but it reports only physical implementation metrics (die area, gate count, density, and clock frequency) and no post-silicon functional test results. There are no measurements from the fabricated chip, no UART/GPIO/NeoPixel loopback tests, and no evidence that software executes correctly on the silicon. Physical fabrication success is necessary but not sufficient for functional correctness; a chip can pass DRC/LVS and still fail due to a design logic error, a missing constraint, or a timing corner issue. The contribution should be downgraded to 'successful tapeout and physical implementation' or the authors must provide post-silicon bring-up results to justify the 'silicon-proven' wording.
- [Croc Platform] The paper states that Croc is built on 'production-ready, industry-proven IPs' and 'silicon-proven SystemVerilog code,' but it provides no evidence or citations that the CVE2 core or the other integrated IPs have been functionally silicon-proven in this or a comparable configuration. The phrase 'industry-proven' appears in the introduction and the platform description, and it is part of the paper's implied credibility argument. The authors should either supply references to prior functional tapeouts of these IPs or rephrase to 'open-source IPs with active industry maintenance' to avoid an unsupported claim.
minor comments (5)
- [Abstract] There is a missing space in 'extensibleRISC-V' in the abstract; it should read 'extensible RISC-V.'
- [Figure 1] Figure 1 contains the informal text 'I am Doug Dimmadome, owner of the Dimmsdale Dimmadome!' which appears to be a meme and is not appropriate for a formal publication. It should be removed or replaced with a neutral watermark or annotation.
- [MLEM Student Tapeout] The claim that the implementation completes in 'less than one hour' on a '6th Generation Intel Core i7' is underspecified. The authors should give the exact CPU model, number of cores, RAM capacity, and storage type to allow reproducibility and fair comparison.
- [Croc Platform] The assertion that CVE2 'achieve[s] its ideal performance of one instruction per cycle' is not backed by cycle-accurate simulation data or benchmark results. A short note about the instruction throughput measured in simulation would strengthen the claim.
- [MLEM Student Tapeout] The term 'verified' in the sentence 'they independently designed, implemented, and verified their designs' is ambiguous. It could refer to simulation-based functional verification, logic equivalence checking, or physical verification; the paper should clarify what verification steps were performed.
Circularity Check
No significant circularity; descriptive platform paper with independent tapeout evidence, minor self-citations not load-bearing.
full rationale
This is a hardware/system description paper, not a mathematical derivation. The central claim—that Croc enables a student ASIC design from RTL to tapeout—is supported by an actual physical implementation report: MLEM measures 5 mm2, has 350kGE at 56% density, achieves 80 MHz under typical conditions, and is implemented in under one hour with less than 8 GiB memory. The implementation uses the external IHP 130 nm open PDK and external open-source tools (Yosys, OpenROAD, Verilator), with the authors' yosys-slang frontend serving as a tool rather than as a premise that assumes the conclusion. The paper cites the authors' prior Basilisk flow and the Croc repository itself, but these are pointers to artifacts and not load-bearing derivations; the quoted implementation results are independently stated. The phrase 'silicon-proving the SoC platform' is stronger than the presented evidence, because no post-silicon test measurements are reported, but that is an empirical/verification gap, not circularity. No fitted parameter is renamed as a prediction, no quantity is defined in terms of the claimed result, and no uniqueness theorem is imported. Accordingly, no significant circularity is present; the minor self-citations do not reduce the central claim to its own inputs.
Assumptions & free parameters
assumptions (3)
- domain assumption The open-source EDA tools (Yosys, OpenRoad, Verilator) and the IHP-Open130nm PDK are adequate and mature enough for a production-like implementation flow.
- domain assumption The open IHP 130nm PDK is accessible to students and universities under acceptable legal and practical terms.
- domain assumption The CVE2/Ibex core and its toolchain are sufficiently bug-free and well-documented for a beginner to extend and integrate safely.
Cite this review
Pith. "Pith review of Croc: An End-to-End Open-Source Extensible RISC-V MCU Platform to Democratize Silicon." pith.science (2026). https://pith.science/paper/GPTWQSP2
@misc{pith2026250205090,
author = {Pith},
title = {Pith review of: Croc: An End-to-End Open-Source Extensible RISC-V MCU Platform to Democratize Silicon},
year = {2026},
howpublished = {\url{https://pith.science/paper/GPTWQSP2}},
note = {Machine review of arXiv:2502.05090}
}
read the original abstract
Ensuring a continuous and growing influx of skilled chip designers and a smooth path from education to innovation are key goals for several national and international "Chips Acts". Silicon democratization can greatly benefit from end-to-end (from silicon technology to software) free and open-source (OS) platforms. We present Croc, an extensible RISC-V microcontroller platform explicitly targeted at hands-on teaching and innovation. Croc features a streamlined OS synthesis and an end-to-end OS implementation flow, ensuring full, unconstrained access to the design, the design automation tools, and the implementation technology. Croc uses the industry-proven, open-source CVE2 core, implementing the RV32I(EMC) instruction set architecture (ISA), enabling students to define and implement their own ISA extensions. MLEM, a tapeout of Croc in IHP's open 130 nm node completed in eight weeks by a team of just two students, demonstrates the platform's viability for hands-on teaching in schools, universities, or even on a self-education path. In spring 2025, ETH Zurich will utilize Croc for its curricular VLSI class, involving up to 80 students, producing up to 40 OS application-specific integrated circuit layouts, and completing up to five student-led system-on-chip tapeouts. The lecture notes and exercises are already available under a Creative Commons license.
Figures
Forward citations
Cited by 1 Pith paper
-
Basilisk: A 34 mm2 End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS
A 34 mm2 Linux-capable 64-bit RISC-V SoC with 2.7 MGE was designed and fabricated using an end-to-end open-source EDA flow, reaching 62 MHz at 1.2 V.
Reference graph
Works this paper leans on
- [1]
-
[2]
congress.gov/bill/ 117th-congress/house-bill/4346
H.R.4346 - CHIPS and Science Act . congress.gov/bill/ 117th-congress/house-bill/4346
- [3]
-
[4]
Importance of Open-Source EDA Tools for Academia . open- source-eda-letter.eu
-
[5]
Edu4Chip. ce . cit . tum . de / ce / forschung / gebiete / design - electronic-circuits-systems/edu4chip
-
[6]
PULP Platform Contributors.Croc System-on-Chip. github. com/pulp-platform/croc. 2024
work page 2024
- [7]
-
[8]
H. Krzysztof et al. “Reflections on the First European Open Source PDK by IHP-Experiences After One Year and Future Activities”. In: 31st MIXDES. IEEE. 2024, pp. 19–22
work page 2024
Show all 14 references
-
[9]
Insights from Basilisk: Are Open-Source EDA Tools Ready for a Multi-Million-Gate, Linux-Booting RV64 SoC Design?
P. Sauter et al. “Insights from Basilisk: Are Open-Source EDA Tools Ready for a Multi-Million-Gate, Linux-Booting RV64 SoC Design?” In: 33rd IWLS (2024)
2024
-
[10]
Ibex RISC-V Core
lowRISC Contributors. Ibex RISC-V Core . github . com / lowRISC/ibex. 2015
2015
-
[11]
OpenHW Group CORE-V CVE2 RISC-V IP
OpenHW Group Contributors. OpenHW Group CORE-V CVE2 RISC-V IP . github.com/openhwgroup/cve2. 2022
2022
-
[12]
github.com/openhwgroup/programs/blob/master/TGs/ cores-task-group/obi/OBI-v1.5.0.pdf
OBI 1. github.com/openhwgroup/programs/blob/master/TGs/ cores-task-group/obi/OBI-v1.5.0.pdf
-
[13]
IIC-OSIC-TOOLS
IIC-JKU. IIC-OSIC-TOOLS. github.com/iic-jku/IIC-OSIC- TOOLS. 2024
2024
-
[14]
Phillip Burgess.Adafruit NeoPixel überguide, Adafruit. 2013. 2 RISC-V Summit Europe, Paris, 12-15 May 2025
2013
Reviewed August 8, 2026 · model on record in the stance chip above.
Discussion (0). Continue with ORCID to comment.