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arxiv: 1804.06508 · v1 · pith:HFCX6I3Anew · submitted 2018-04-18 · 💻 cs.NE · cs.LG

UCNN: Exploiting Computational Reuse in Deep Neural Networks via Weight Repetition

classification 💻 cs.NE cs.LG
keywords weightucnnenergyrepetitionacceleratorsamesparsityweights
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Convolutional Neural Networks (CNNs) have begun to permeate all corners of electronic society (from voice recognition to scene generation) due to their high accuracy and machine efficiency per operation. At their core, CNN computations are made up of multi-dimensional dot products between weight and input vectors. This paper studies how weight repetition ---when the same weight occurs multiple times in or across weight vectors--- can be exploited to save energy and improve performance during CNN inference. This generalizes a popular line of work to improve efficiency from CNN weight sparsity, as reducing computation due to repeated zero weights is a special case of reducing computation due to repeated weights. To exploit weight repetition, this paper proposes a new CNN accelerator called the Unique Weight CNN Accelerator (UCNN). UCNN uses weight repetition to reuse CNN sub-computations (e.g., dot products) and to reduce CNN model size when stored in off-chip DRAM ---both of which save energy. UCNN further improves performance by exploiting sparsity in weights. We evaluate UCNN with an accelerator-level cycle and energy model and with an RTL implementation of the UCNN processing element. On three contemporary CNNs, UCNN improves throughput-normalized energy consumption by 1.2x - 4x, relative to a similarly provisioned baseline accelerator that uses Eyeriss-style sparsity optimizations. At the same time, the UCNN processing element adds only 17-24% area overhead relative to the same baseline.

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Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score.

  1. Mixed-Signal Charge-Domain Acceleration of Deep Neural networks through Interleaved Bit-Partitioned Arithmetic

    cs.AR 2019-06 unverdicted novelty 6.0

    The authors propose BIHIWE, a microarchitecture that accelerates DNN dot-products by bit-partitioning them into spatially parallel low-bitwidth MAC units operating in the charge domain and sharing A/D converters.