Memory-Centric Computing: Recent Advances in Processing-in-DRAM

Ataberk Olgun; Geraldo F. Oliveira; Ismail Emir Yuksel; Onur Mutlu

REVIEW 3 major objections 6 minor 234 references

Memory-Centric Computing: Recent Advances in Processing-in-DRAM

T0 review · 3 major / 6 minor · reviewed 2026-08-11 · deepseek-v4-flash

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Pith's one-line read Processing-in-DRAM turns DRAM into a compute substrate, with unmodified chips performing Boolean logic at 94–99% success.

desk verdict A clear, well-illustrated survey of the authors' own Processing-in-DRAM work, but the COTS 'high reliability' claim outruns the data: 95% per-operation success is undependable without an error model. read the letter →

arxiv 2412.19275 v1 pith:HL5XMXY6 submitted 2024-12-26 cs.AR cs.DC

Onur Mutlu , Ataberk Olgun , Geraldo F. Oliveira , Ismail Emir Yuksel This is my paper · ORCID

classification cs.ARcs.DC

keywords processing-in-DRAMmemory-centriccomputingbulkbitwiseoperationsDRAMtimingviolationsimultaneousrowactivationMIMDRAMSectoredin-memorycomputation

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper argues that DRAM, the working memory of nearly every computer, can be turned into a place where computation happens rather than merely data storage, and that doing so removes the expensive movement of data between processor and memory. It reviews recent advances in Processing-in-DRAM in three parts: hardware/software support (MIMDRAM) that lets different memory arrays execute different bit-serial instructions at fine grain; experimental evidence that unmodified commercial DRAM chips can perform NOT, NAND, NOR, AND, OR, and multi-row copy by deliberately violating timing parameters, with per-operation success rates above 94%; and a DRAM design (Sectored DRAM) that activates only part of a row to save energy. If these results hold, memory-centric designs could substantially reduce data movement overheads in memory-bound workloads, strengthening the case for treating memory as a combined storage-and-computation substrate.

What carries the argument

The load-bearing mechanism is charge sharing on DRAM bitlines during simultaneous row activation. In an Ambit-style triple-row activation, three cells connected to one bitline share charge and a sense amplifier resolves the majority, yielding AND and OR; in the COTS experiments, violating tRP lets a second activate interrupt precharge so the same charge-sharing principle performs NOT, NAND/NOR, and Multi-RowCopy on unmodified chips. MIMDRAM's additional machinery is mat-level isolation: mat isolation transistors, row decoder latches, and mat selectors let different mats in a subarray run different instructions, with inter-mat and intra-mat interconnects moving data between mats. Sectored DRAM's machinery is wordline segmentation with sector latches and transistors to activate a chosen subset of mats.

What would settle it

Run the NOT, AND/NAND, and Multi-RowCopy command sequences from Section V on a large sample of commercial DRAM chips, comparing every result against a known-good pattern across extended temperature, voltage, and chip-to-chip variation; if the measured success rate falls below what the paper claims or below a level usable without correction, the claim of reliable unmodified-chip computation is falsified.

Watch

Extended reading notes

Core claim

The paper's central claim is that Processing-in-DRAM has moved from proposal to demonstrated capability. First, MIMDRAM shows a hardware/software co-designed system in which each DRAM mat within a subarray can independently execute different bit-serial SIMD operations; evaluating twelve real applications and 495 multi-programmed mixes, it reports 13.2x/0.22x/173x the performance of CPU/GPU/SIMDRAM baselines, and 15.6x the SIMD utilization of SIMDRAM. Second, experiments on 224 and 120 commercial off-the-shelf DRAM chips show that by issuing back-to-back ACT/PRE commands with tRP below the manufacturer specification (e.g., <3ns), a memory controller can make the chips perform functionally complete Boolean operations: NOT, NAND, NOR, AND, OR, and one-row-to-31-row copy, with average success rates of 94.94% to 99.98%. Third, Sectored DRAM splits wordlines so a single activate touches only a subset of mats, cutting DRAM energy by up to 33% and improving performance by up to 36% for data-intensive workloads.

Load-bearing premise

The central claim of dependable computation on unmodified DRAM chips rests on the assumption that deliberately violating the manufacturer's timing parameters produces correct results reliably enough for real workloads; the paper reports 94.94% to 99.98% success rates and does not propose an error-detection or correction mechanism for the failed operations.

Editorial extensions

If this is right

If MIMDRAM's results stand, bulk bitwise operations in DRAM can be programmed at the granularity of vectorizing compilers, making in-memory computation usable for real workloads without hand-tuning.
If COTS DRAM chips truly perform NOT/NAND/NOR at above 94% success under timing violation, then a memory controller with no DRAM modification can implement functionally complete Boolean logic on existing hardware.
The demonstrated Multi-RowCopy, one row copied concurrently into up to 31 rows, implies that bulk data copy and initialization can be accelerated inside DRAM, and may also offer a defense against cold-boot attacks.
Sectored DRAM's fine-grained activation implies that the energy cost of over-fetching can be cut by roughly a fifth to a third in data-intensive workloads, which directly improves the efficiency of Processing-in-DRAM systems that rely on row activation.
Together, the three advances imply that the memory controller and DRAM interface should be redesigned to expose row-level and mat-level computation commands rather than treating DRAM solely as a byte-addressable store.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

The paper does not specify an error-detection or correction mechanism for COTS DRAM computation; one implicit consequence is that practical use would need to pair these operations with ECC or re-execution, which would reduce the net gains.
The COTS success rates are averages across tested chips; the paper leaves open whether a production system could tolerate the worst-case chips, so the strongest defensible version of the claim is that the capability exists, not that it is already dependable at scale.
A natural extension is to combine the two approaches: use MIMDRAM-style mat-level control with COTS-style timing-violation operations to build a hybrid that keeps the programmability of the former and the zero-modification cost of the latter.
If the fine-grained activation of Sectored DRAM is combined with in-memory compute, the energy savings from avoiding over-fetch would compound the savings from avoiding data movement, a combination the paper does not quantify.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

The short version: this is a competent invited survey of the Mutlu group's own Processing-in-DRAM line of work, with one genuinely new but small measurement (Fig. 13, TRNG throughput for 2/8/16/32-row activation). If you need a single place to point someone who wants to understand MIMDRAM, Sectored DRAM, and the COTS bulk-bitwise experiments, it does the job. But treat the COTS reliability claim with care; the paper's own numbers support 'promising phenomenon', not 'dependable computation substrate.'

What it does well: the mechanism descriptions are clear and accurate to the underlying papers. The figures are helpful. The evaluation numbers for MIMDRAM and Sectored DRAM come from peer-reviewed simulation studies (gem5/CACTI), and the COTS results are real measurements across hundreds of chips. The survey is honest about its scope: it is a review of the authors' prior work, and the only new data is the ongoing TRNG parameter scan.

Where it gets soft: the 'high reliability' framing for COTS operations. A per-operation success rate of 94.94% (16-input AND) or even 98-99% for NOT does not make a multi-gate computation dependable. Ten chained gates at 95% each succeed with probability under 60%. The paper does not report per-bit error rates, error correlation, or any detection/correction mechanism, and it does not distinguish deterministic (profileable) errors from random ones. The stress-test note lands: this is a missing error model, not an internal inconsistency. The conclusion's invitation to see COTS DRAM as a practical substrate overreaches the data. The paper's own 'solid foundation for future robust mechanisms' framing is the defensible one.

Also, the MIMDRAM and Sectored DRAM gains are simulation-based, and the paper says so; readers should treat them as upper bounds, not measured outcomes. The self-citation is heavy, but that is what an invited review of one's own program looks like; the underlying works are externally peer-reviewed.

Who should read it: researchers entering the PiD area, or people wanting a quick map of this group's results. For a serious referee, yes — as an invited survey it should be reviewed for accuracy and framing, and the referee should push for a caveat on COTS reliability or a pointer to the error-handling question. I would not desk reject it.

Referee Report

3 major / 6 minor

Summary. This invited overview paper summarizes recent Processing-in-DRAM (PiD) advances from the authors' group. It describes MIMDRAM, a hardware/software co-designed Processing-using-DRAM system that enables fine-grained, multiple-instruction multiple-data execution within DRAM mats; experimental results on commercial off-the-shelf (COTS) DRAM chips showing NOT, AND/NAND/OR/NOR, many-row activation, Multi-RowCopy, and true random number generation; and Sectored DRAM, a fine-grained DRAM architecture. The paper reports large performance and energy gains for MIMDRAM (13.2x/0.22x/173x performance versus CPU/GPU/SIMDRAM), high success rates (>94%) for COTS DRAM bulk-bitwise operations, and up to 33% DRAM energy savings for Sectored DRAM.

Significance. If the claims hold, the paper provides useful evidence that Processing-in-DRAM can reduce data-movement overheads: MIMDRAM's compiler/runtime support addresses programmability, the COTS experiments demonstrate functional completeness on unmodified chips, and Sectored DRAM targets access-granularity inefficiencies. The experimental breadth is a strength: the COTS results are based on hundreds of real chips, the MIMDRAM evaluation uses gem5 and CACTI against external baselines, and the paper explicitly identifies interconnect throughput as a limiter. However, the paper is a condensed summary of prior peer-reviewed works rather than a self-contained technical contribution, and the practical-usability claim for COTS DRAM computation is not fully supported by the reported success-rate statistics.

major comments (3)

[Section V, Figs. 8-11] The paper states that COTS DRAM chips perform NOT, AND/NAND/OR/NOR, and Multi-RowCopy operations "at high success rates (>94%)" and describes these as "functionally-complete bulk-bitwise Boolean operations." The reported success rates are per-operation, not per-bit: for example, the average success rate for 16-input AND/NAND is 94.94%. A computation composed of k such operations has expected success roughly 0.95^k, so a 10-gate expression would be wrong in more than 40% of runs without correction. The paper does not report per-bit error rates, error correlation across rows/data patterns/temperature/voltage, whether errors are deterministic and profileable or random, or any detection/correction mechanism. The evidence supports a feasibility demonstration, but the claim that unmodified COTS DRAM can serve as a dependable substrate for real workloads is not supported. Please add an explicit error model, or restrict the claim to "feasibility" and discuss error mitigation (e.g., verification, recomputation, ECC).
[Section IV, Fig. 6] The headline MIMDRAM results are compared against CPU, GPU, and SIMDRAM baselines, but the evaluation methodology for the CPU and GPU baselines is not described. The text only says that MIMDRAM and SIMDRAM are implemented in gem5 and evaluated with CACTI, and that 12 memory-bound applications were selected from five benchmark suites. It is unclear whether the CPU and GPU results come from real hardware, full-system simulation, or vendor simulators, and whether the 12 applications are identical across all four target systems. Without this information, the 13.2x/0.22x/173x performance and 0.0017x/0.00007x/0.004x energy ratios cannot be independently interpreted. Please specify the baseline configurations, simulation methodology, and whether the reported ratios are end-to-end or kernel-only.
[Section VI] The Sectored DRAM section makes strong quantitative claims: "reduces the DRAM energy consumption of data intensive workloads by up to 33% (20% on average), while improving performance by up to 36% (17% on average)" and "system-wide energy savings of up to 23%." However, the section provides no evaluation setup: no workload list, no baseline DRAM configuration, no simulator description, and no sensitivity analysis. The reader cannot verify these numbers from this paper. Please add a concise methodology summary, or state explicitly that the results are taken from [222] and summarize the setup used there.

minor comments (6)

[Section V, Fig. 11 caption] The caption says the results were "measured in 224, 224, and 120 COTS DRAM chips" without spelling out which operation corresponds to which count; please clarify the mapping (e.g., NOT: 224, AND/NAND/OR/NOR: 224, Multi-RowCopy: 120).
[Section V, Fig. 8 and surrounding text] The phrase "with violated manufacturer-recommended tRP timing, e.g., <3ns" is awkward; it should read "with tRP set below the manufacturer-recommended value (e.g., <3ns)."
[Section IV, Fig. 6] The notation "13.2×/0.22×/173× the performance" is ambiguous because the baseline order is only given later; spell out "relative to CPU/GPU/SIMDRAM" in the caption or text.
[Section V, Fig. 12] The figure describes a TRNG command sequence with ACT R0 and ACT R3 but says this "activates four rows simultaneously"; please explain how four rows are activated, since the text otherwise implies a single-row ACT activates only one row.
[References] The reference list contains several typos, e.g., [5] "V olos" should be "Volos," [64] "opthers" should be "others," and [138] "Boroum" should be "Boroumand." A careful proofread is needed.
[Section III, first paragraph] The sentence "First, enabling widespread use of PiM on a wide variety of important workloads requires PiM systems to i) be easy to program and seamlessly compile workloads into" is grammatically incomplete; please revise.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the paper is a review that reports experimental and simulation results from cited prior works, with no fitted parameter or definitional reduction.

full rationale

The paper is an invited review summarizing the authors' prior peer-reviewed work on Processing-in-DRAM. Its central quantitative claims are measurements or simulations taken from the cited original papers: MIMDRAM speedups are obtained from gem5 and CACTI evaluations described in [219]; COTS DRAM operation success rates are experimental characterizations reported in [220,221,223]; Sectored DRAM energy/performance numbers are simulation results from [222]. None of these numbers is derived from a parameter fitted in this paper, and none is defined in terms of the conclusion it supports. The paper does not invoke a uniqueness theorem, does not smuggle an ansatz through a citation, and does not rename an empirical pattern as a new derivation. The only notable concern is that the COTS DRAM >94% success-rate claim lacks a per-bit error model and error-correction mechanism, which makes the practical reliability conclusion under-supported; however, that is a correctness/completeness issue, not circularity. Heavy self-citation is present, but per the review rules self-citation is not circularity when, as here, the cited works are independent experimental and simulation studies with external baselines (CPU, GPU, SIMDRAM) and the claims do not reduce to the survey's own definitions.

Assumptions & free parameters 0 free parameters · 3 assumptions · 2 invented entities

This review introduces no new natural entities or fitted parameters. The hardware structures listed are proposed designs evaluated in simulation; they have no independent fabricated evidence. The central assumptions are that timing-violation DRAM operations are reliable and that the simulation models reflect real hardware.

assumptions (3)

domain assumption DRAM charge-sharing and sense-amplifier behavior can be reliably exploited by violating timing parameters
The COTS results (Section V) rely on the assumption that many-row activation leads to deterministic majority/AND/OR behavior across chips.
domain assumption Simulation models (gem5, CACTI) accurately capture MIMDRAM and Sectored DRAM behavior
MIMDRAM and Sectored DRAM evaluations (Sections IV and VI) use simulation; their speedup and energy numbers depend on model fidelity.
domain assumption The 12 selected applications are representative of data-intensive workloads
The authors selected 12 applications from 117 based on memory-bound and auto-vectorizable criteria, which may favor the evaluated PiD mechanisms.

invented entities (2)

MIMDRAM hardware modifications (mat isolation transistor, row decoder latch, mat selector, inter-mat and intra-mat interconnects)
purpose: Enable fine-grained processing-using-DRAM with multiple-instruction multiple-data execution
These structures are proposed and evaluated only through gem5/CACTI simulation in the cited work; no fabricated chip is demonstrated.
Sectored DRAM sector latches, sector transistors, and additional local wordline drivers
purpose: Enable fine-grained DRAM row activation and data transfer to reduce wasted energy
The design is simulated, not fabricated; independent silicon evidence is absent.

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Cite this review

Pith. "Pith review of Memory-Centric Computing: Recent Advances in Processing-in-DRAM." pith.science (2026). https://pith.science/paper/HL5XMXY6

@misc{pith2026241219275,
  author       = {Pith},
  title        = {Pith review of: Memory-Centric Computing: Recent Advances in Processing-in-DRAM},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/HL5XMXY6}},
  note         = {Machine review of arXiv:2412.19275}
}

read the original abstract

Memory-centric computing aims to enable computation capability in and near all places where data is generated and stored. As such, it can greatly reduce the large negative performance and energy impact of data access and data movement, by 1) fundamentally avoiding data movement, 2) reducing data access latency & energy, and 3) exploiting large parallelism of memory arrays. Many recent studies show that memory-centric computing can largely improve system performance & energy efficiency. Major industrial vendors and startup companies have recently introduced memory chips with sophisticated computation capabilities. Going forward, both hardware and software stack should be revisited and designed carefully to take advantage of memory-centric computing. This work describes several major recent advances in memory-centric computing, specifically in Processing-in-DRAM, a paradigm where the operational characteristics of a DRAM chip are exploited and enhanced to perform computation on data stored in DRAM. Specifically, we describe 1) new techniques that slightly modify DRAM chips to enable both enhanced computation capability and easier programmability, 2) new experimental studies that demonstrate the functionally-complete bulk-bitwise computational capability of real commercial off-the-shelf DRAM chips, without any modifications to the DRAM chip or the interface, and 3) new DRAM designs that improve access granularity & efficiency, unleashing the true potential of Processing-in-DRAM.

Figures

Figures reproduced from arXiv: 2412.19275 by the authors.

**Figure 1.** An example of performing the MAJority-of-three operation (i.e., MAJ3(A,B,C)) (a) and the NOT operation (i.e., dst=NOT(src)) in Ambit [122]. In (a), we focus on DRAM cell and sense amplifier operations ( 0 ). Initially, cells A, B, C, and bitline have voltage levels of GND, VDD, VDD, and VDD/2, respectively ( 1 ). We first perform a triple-row activation (TRA) to simultaneously activate cells A, B, and C ( 2 ). When … view at source ↗

**Figure 5.** An example of a PuD vector reduction, i.e., out+=(A[i]+B[i]), in MIMDRAM [219]. For illustration purposes, we assume that DRAM has only two mats, and the 10 1-bit data elements of the input arrays A and B are evenly distributed across the two DRAM mats. MIMDRAM executes a vector reduction in three steps. In the first step, MIMDRAM executes a PuD addition operation over the data in the two DRAM mats ( 1 ), storing th… view at source ↗

**Figure 6.** CPU-normalized performance (a), energy (b), and energy efficiency (performance/Watt) (c) results for processor-centric (i.e., Intel Skylake CPU [225] and NVIDIA A100 GPU [226]) and memory-centric (i.e., SIMDRAM [185] and MIMDRAM [219]) architectures executing 12 real-world applications. We implement MIMDRAM and SIMDRAM using gem5 and evaluate their energy consumption using CACTI. We analyze 117 applications from SPE… view at source ↗

Figures from the paper (7 more)

**Figure 7.** Figure 7 [PITH_FULL_IMAGE:figures/full_fig_p003_7.png]

**Figure 9.** Figure 9: Command sequence for performing the two-input AND and NAND operations (i.e., AND(X, Y) and NAND(X, Y)) in COTS DRAM chips and the state of cells during each related step. The memory controller issues each command (shown in orange boxes below the time axis) at the corre…

**Figure 10.** Figure 10: Command sequence for performing the Multi-RowCopy operation (i.e., copying src row to N other dst rows simultaneously) in COTS DRAM chips and the state of cells during each related step. The memory controller issues each command (shown in orange boxes below the time a…

**Figure 8.** Figure 8: Command sequence for performing the NOT operation (dst = NOT(src)) in COTS DRAM chips and the state of cells during each related step. The memory controller issues each command (shown in orange boxes below the time axis) at the corresponding tick mark on the time axis …

**Figure 11.** Figure 11: Success rates of the NOT operation with varying numbers of destination rows (a) AND, NAND, OR, and NOR operations with varying numbers of input operands (b) the Multi-RowCopy operation with varying numbers of destination rows (c), as measured in 224, 224, and 120 COTS…

**Figure 12.** Figure 12: Command sequence for true random number generation in COTS DRAM chips and the state of cells during each related step. The memory controller issues each command (shown in orange boxes below the time axis) at the corresponding tick mark and asserted signals are highlig…

**Figure 14.** Figure 14: A DRAM module (a), a DRAM chip with multiple banks (b), baseline DRAM bank organization with multiple subarrays (c), and a Sectored DRAM subarray (d) [222]. The global row decoder ( 1 ) enables a global wordline ( 2 ) based on the higher-order bits of a DRAM row addre…

Discussion (0). Continue with ORCID to comment.

Reference graph

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Accelerating Weather Prediction Using Near-Memory Reconfigurable Fabric,

G. Singh, D. Diamantopoulos, J. Gómez-Luna, C. Hagleitner, S. Stuijk, H. Corporaal, and O. Mutlu, “Accelerating Weather Prediction Using Near-Memory Reconfigurable Fabric,” TRETS, 2022

2022
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Cellular logic-in-memory arrays,

W. H. Kautz, “Cellular logic-in-memory arrays,” IEEE ToC, 1969

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A Logic-in-Memory Computer,

H. S. Stone, “A Logic-in-Memory Computer,” IEEE ToC, 1970

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A 1.2V 8Gb 8-Channel 128GB/s High-Bandwidth Memory (HBM) Stacked DRAM with Effective Microbump I/O Test Methods Using 29nm Process and TSV,

D. U. Lee, K. W. Kim, K. W. Kim, H. Kim, J. Y . Kim, Y . J. Park, J. H. Kim, D. S. Kim, H. B. Park, J. W. Shin et al. , “A 1.2V 8Gb 8-Channel 128GB/s High-Bandwidth Memory (HBM) Stacked DRAM with Effective Microbump I/O Test Methods Using 29nm Process and TSV,” in ISSCC, 2014

2014
[206]

Simultane- ous Multi-Layer Access: Improving 3D-Stacked Memory Bandwidth at Low Cost,

D. Lee, S. Ghose, G. Pekhimenko, S. Khan, and O. Mutlu, “Simultane- ous Multi-Layer Access: Improving 3D-Stacked Memory Bandwidth at Low Cost,” TACO, 2016

2016
[207]

JEDEC, JESD23-5D: High Bandwidth Memory (HBM) DRAM Standard, 2021

2021
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JEDEC, JESD23-8A: High Bandwidth Memory (HBM3) DRAM Stan- dard, 2021

2021
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Present and Future, Challenges of High Bandwith Memory (HBM),

K. Kim and M.-j. Park, “Present and Future, Challenges of High Bandwith Memory (HBM),” in IMW, 2024

2024
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MATSA: An MRAM-Based Energy-Efficient Accelerator for Time Series Analysis,

I. Fernandez, C. Giannoula, A. Manglik, R. Quislant, N. M. Ghiasi, J. Gómez-Luna, E. Gutierrez, O. Plata, and O. Mutlu, “MATSA: An MRAM-Based Energy-Efficient Accelerator for Time Series Analysis,” IEEE Access, 2024

2024
[211]

Design Space Exploration for PIM Architectures in 3D-Stacked Memories,

J. P. C. de Lima, P. C. Santos, M. A. Alves, A. Beck, and L. Carro, “Design Space Exploration for PIM Architectures in 3D-Stacked Memories,” in CF, 2018

2018
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BlueDBM: An appliance for big data analytics,

S.-W. Jun, M. Liu, S. Lee, J. Hicks, J. Ankcorn, M. King, S. Xu, and Arvind, “BlueDBM: An appliance for big data analytics,” ISCA, 2015

2015
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Field-Effect Transistor Memory,

R. H. Dennard, “Field-Effect Transistor Memory,” U.S. Patent 3,387,286, 1968

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SwiftRL: Towards Efficient Reinforcement Learning on Real Processing-In- Memory Systems,

K. Gogineni, S. S. Dayapule, J. Gómez-Luna, K. Gogineni, P. Wei, T. Lan, M. Sadrosadati, O. Mutlu, and G. Venkataramani, “SwiftRL: Towards Efficient Reinforcement Learning on Real Processing-In- Memory Systems,” in ISPASS, 2024

2024
[215]

SecNDP: Secure Near-Data Processing with Untrusted Memory,

W. Xiong, L. Ke, D. Jankov, M. Kounavis, X. Wang, E. Northup, J. A. Yang, B. Acun, C.-J. Wu, P. T. P. Tang et al., “SecNDP: Secure Near-Data Processing with Untrusted Memory,” in HPCA, 2022

2022
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Invisimem: Smart Memory Defenses For Memory Bus Side Channel,

S. Aga and S. Narayanasamy, “Invisimem: Smart Memory Defenses For Memory Bus Side Channel,” ISCA, 2017

2017
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FracDRAM: Fractional Values in Off-the-Shelf DRAM,

F. Gao, G. Tziantzioulis, and D. Wentzlaff, “FracDRAM: Fractional Values in Off-the-Shelf DRAM,” in MICRO, 2022

2022
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DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips,

A. Olgun, H. Hassan, A. G. Ya ˘glıkçı, Y . C. Tu˘grul, L. Orosa, H. Luo, M. Patel, O. Ergin, and O. Mutlu, “DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips,” TCAD, 2023

2023
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MIMDRAM: An End-to-End Processing- Using-DRAM System for High-Throughput, Energy-Efficient and Programmer-Transparent Multiple-Instruction Multiple-Data Comput- ing,

G. F. Oliveira, A. Olgun, A. G. G. Yaglikçi, N. Bostanci, J. Gómez-Luna, S. Ghose, and O. Mutlu, “MIMDRAM: An End-to-End Processing- Using-DRAM System for High-Throughput, Energy-Efficient and Programmer-Transparent Multiple-Instruction Multiple-Data Comput- ing,” in HPCA, 2024

2024
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Functionally-Complete Boolean Logic in Real DRAM Chips: Experi- mental Characterization and Analysis,

I. E. Yuksel, Y . C. Tugrul, A. Olgun, F. N. Bostanci, A. G. Yaglikci, G. F. de Oliveira, H. Luo, J. G. Luna, M. Sadrosadati, and O. Mutlu, “Functionally-Complete Boolean Logic in Real DRAM Chips: Experi- mental Characterization and Analysis,” in HPCA, 2024

2024
[221]

Simultaneous Many-Row Activation in Off-the-Shelf DRAM Chips: Experimental Characterization and Analysis,

I. E. Yuksel, Y . C. Tugrul, F. N. Bostanci, G. F. de Oliveira, A. G. Yaglikci, A. Olgun, M. Soysal, H. Luo, J. G. Luna, M. Sadrosadati, and O. Mutlu, “Simultaneous Many-Row Activation in Off-the-Shelf DRAM Chips: Experimental Characterization and Analysis,” in DSN, 2024

2024
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PULSAR: Simultaneous Many-Row Activation for Reliable and High-Performance Computing in Off-the-Shelf DRAM Chips,

I. E. Yuksel, Y . C. Tugrul, F. N. Bostanci, A. G. Yaglikci, A. Olgun, G. F. Oliveira, M. Soysal, H. Luo, J. G. Luna, M. Sadrosadati, and O. Mutlu, “PULSAR: Simultaneous Many-Row Activation for Reliable and High-Performance Computing in Off-the-Shelf DRAM Chips,” arXiv:2312.02...

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M. J. Flynn, “Very High-Speed Computing Systems,” Proc. IEEE, 1966

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6th Generation Intel Core Processor Family Datasheet,

Intel Corp., “6th Generation Intel Core Processor Family Datasheet,” http://www.intel.com/content/www/us/en/processors/core/
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NVIDIA A100 Tensor Core GPU Architecture,

NVIDIA, “NVIDIA A100 Tensor Core GPU Architecture,” https://t.ly /rMUgA, 2020

2020
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SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies,

H. Hassan, N. Vijaykumar, S. Khan, S. Ghose, K. Chang, G. Pekhi- menko, D. Lee, O. Ergin, and O. Mutlu, “SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies,” in HPCA, 2017

2017
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A Low-Cost Reduced-Latency DRAM Architecture with Dynamic Reconfiguration of Row Decoder,

F. Bai, S. Wang, X. Jia, Y . Guo, B. Yu, H. Wang, C. Lai, Q. Ren, and H. Sun, “A Low-Cost Reduced-Latency DRAM Architecture with Dynamic Reconfiguration of Row Decoder,” TVLSI, 2022

2022
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High-Performance Low-Power Selective Precharge Schemes for Address Decoders,

M. A. Turi and J. G. Delgado-Frias, “High-Performance Low-Power Selective Precharge Schemes for Address Decoders,” TCAS-II, 2008

2008
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180-2: Secure Hash Standard (SHS),

National Institute of Standards and Technology (NIST), “180-2: Secure Hash Standard (SHS),” Federal Information Processing Standards Publications, 2012

2012
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A Statistical Test Suite for Random and Pseudorandom Number Generators for Cryptographic Applications,

L. Bassham, A. Rukhin, J. Soto, J. Nechvatal, M. Smid, S. Leigh, M. Levenson, M. Vangel, N. Heckert, and D. Banks, “A Statistical Test Suite for Random and Pseudorandom Number Generators for Cryptographic Applications,” NIST SP, 2010

2010
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JEDEC, JESD79-4C: DDR4 SDRAM , 2017

2017
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Memory-Centric Computing: Recent Advances in Processing-in-DRAM (Invited),

O. Mutlu, G. F. Oliveira, A. Olgun, and I. E. Yuksel, “Memory-Centric Computing: Recent Advances in Processing-in-DRAM (Invited),” in IEDM, 2024. 9

2024

Pith tools

Reviewed August 11, 2026 · model on record in the stance chip above.

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Sectored DRAM: An Energy-Efficient High-Throughput and Practical Fine-Grained DRAM Architecture,

A. Olgun, F. Bostanci, G. F. Oliveira, Y . C. Tugrul, R. Bera, A. G. Yaglikci, H. Hassan, O. Ergin, and O. Mutlu, “Sectored DRAM: An Energy-Efficient High-Throughput and Practical Fine-Grained DRAM Architecture,” TACO, 2024

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Memory Scaling: A Systems Architecture Perspective,

O. Mutlu, “Memory Scaling: A Systems Architecture Perspective,” in IMW, 2013

2013

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Research Problems and Opportunities in Memory Systems,

O. Mutlu and L. Subramanian, “Research Problems and Opportunities in Memory Systems,” SUPERFRI, 2014

2014

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The Tail at Scale,

J. Dean and L. A. Barroso, “The Tail at Scale,” CACM, 2013

2013

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Profiling a Warehouse-Scale Computer,

S. Kanev, J. P. Darago, K. Hazelwood, P. Ranganathan, T. Moseley, G.-Y . Wei, and D. Brooks, “Profiling a Warehouse-Scale Computer,” in ISCA, 2015

2015

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Clearing the Clouds: A Study of Emerging Scale-Out Workloads on Modern Hardware,

M. Ferdman, A. Adileh, O. Kocberber, S. V olos, M. Alisafaee, D. Jevdjic, C. Kaynak, A. D. Popescu, A. Ailamaki, and B. Falsafi, “Clearing the Clouds: A Study of Emerging Scale-Out Workloads on Modern Hardware,” in ASPLOS, 2012

2012

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BigDataBench: A Big Data Benchmark Suite from Internet Services,

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2014

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Enabling Practical Processing in and near Memory for Data-Intensive Computing,

O. Mutlu, S. Ghose, J. Gómez-Luna, and R. Ausavarungnirun, “Enabling Practical Processing in and near Memory for Data-Intensive Computing,” in DAC, 2019

2019