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Bayesian Optimization for Macro Placement
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Macro placement is the problem of placing memory blocks on a chip canvas. It can be formulated as a combinatorial optimization problem over sequence pairs, a representation which describes the relative positions of macros. Solving this problem is particularly challenging since the objective function is expensive to evaluate. In this paper, we develop a novel approach to macro placement using Bayesian optimization (BO) over sequence pairs. BO is a machine learning technique that uses a probabilistic surrogate model and an acquisition function that balances exploration and exploitation to efficiently optimize a black-box objective function. BO is more sample-efficient than reinforcement learning and therefore can be used with more realistic objectives. Additionally, the ability to learn from data and adapt the algorithm to the objective function makes BO an appealing alternative to other black-box optimization methods such as simulated annealing, which relies on problem-dependent heuristics and parameter-tuning. We benchmark our algorithm on the fixed-outline macro placement problem with the half-perimeter wire length objective and demonstrate competitive performance.
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Cited by 2 Pith papers
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BBOPlace-Bench: Benchmarking Black-Box Optimization for Chip Placement
BBOPlace-Bench is a unified benchmark for black-box optimization of chip placement, where evolutionary algorithms under mask-guided and hyperparameter formulations beat analytical and RL baselines on wirelength metrics.
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DAS-MP: Enabling High-Quality Macro Placement with Enhanced Dataflow Awareness
DAS-MP extracts macro-to-cell and cell-to-cell dataflow connections and adds area-aware and orientation fine-tuning, reporting 7.9% lower wirelength and 82.5% lower congestion overflow than RTL-MP on seven benchmarks.
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