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arxiv: 2606.07980 · v1 · pith:HXJPRP5Lnew · submitted 2026-06-06 · 💻 cs.IR

DeRes: Decoupling Residual Stability and Adaptivity for Scalable CTR Prediction

Wenzhuo Cheng , Shipeng Nie , Qixin Guo , Xuefeng Sun , Jianguo Lou , Zhengwei Zheng This is my paper

Pith reviewed 2026-06-27 19:22 UTC · model grok-4.3

classification 💻 cs.IR
keywords DeResresidual connectionsCTR predictionblock attention residualscaling lawspointwise attentiondual-path networkstransformer models
0
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The pith

DeRes decouples residual connections into parallel identity and block-attention paths with per-dimension gating to improve CTR scaling.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

Transformer CTR models lose early user-interest signals through repeated residual additions and cannot forget stale interests because each layer only connects to its immediate predecessor. DeRes addresses this by splitting each residual into an identity path that keeps first-order feature reuse and gradient flow intact, plus a block attention residual path that attends over compressed outputs from all prior blocks. A vector-wise gate blends the two paths per hidden dimension, and the attention uses SiLU instead of Softmax so multiple past blocks can activate together while irrelevant ones receive negative weights. On industrial-scale CTR data the design yields higher AUC than twelve baselines at under 5 percent extra FLOPs and produces a steeper compute-AUC scaling curve, so an eight-layer DeRes reaches the accuracy of a sixteen-layer baseline.

Core claim

DeRes routes each layer through an Identity residual path that preserves first-order feature reuse and a Block Attention Residual path that attends over compressed outputs of all earlier blocks, combined with a vector-wise gate and SiLU replacing Softmax in the cross-layer attention, resulting in higher AUC and a steeper compute-AUC scaling law than standard or attention-based residuals.

What carries the argument

Dual-path residual consisting of an identity skip plus a Block Attention Residual that attends over prior block outputs, blended by a vector-wise gate and using SiLU for simultaneous multi-block activation and negative forgetting weights.

If this is right

  • DeRes reaches up to 0.32 percent higher AUC than twelve baselines at less than 5 percent extra FLOPs.
  • An eight-layer DeRes matches the AUC of a sixteen-layer OneTrans, delivering roughly 2x compute saving at equivalent accuracy.
  • The dual-path design outperforms either the identity path or the block-attention path used alone.
  • Identity residuals outperform learnable residuals, and SiLU outperforms Softmax inside the cross-layer attention.
  • DeRes exhibits a compute-AUC exponent of 0.118 versus 0.071 for OneTrans.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same dual-path split could be tested in non-CTR transformer stacks where early-token signals also degrade with depth.
  • Industrial pipelines that currently scale depth for marginal AUC gains might instead allocate saved compute to wider embeddings or more training data.
  • If the vector-wise gate learns to suppress entire dimensions on some paths, it may reduce effective parameter count without explicit pruning.

Load-bearing premise

The block attention residual, when attending over compressed prior outputs and combined with the vector-wise gate and SiLU, will reliably capture long-range cross-layer dependencies and enable forgetting without instability or overfitting.

What would settle it

A replication on held-out CTR datasets in which the measured compute-AUC slope for DeRes falls to the same value as OneTrans or in which the AUC gains vanish beyond twelve layers would falsify the central claim.

Figures

Figures reproduced from arXiv: 2606.07980 by Jianguo Lou, Qixin Guo, Shipeng Nie, Wenzhuo Cheng, Xuefeng Sun, Zhengwei Zheng.

Figure 1
Figure 1. Figure 1: DeRes architecture. (a) CTR pipeline: embedding, channel split ( [PITH_FULL_IMAGE:figures/full_fig_p004_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Block-granularity Pareto frontier (Industrial). [PITH_FULL_IMAGE:figures/full_fig_p009_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Interpretability analysis (Industrial). (a) Cross-layer attention heatmap: diagonal flow with persistent [PITH_FULL_IMAGE:figures/full_fig_p010_3.png] view at source ↗
Figure 5
Figure 5. Figure 5: Scaling law (Industrial): AUC vs. FLOPs (log scale). [PITH_FULL_IMAGE:figures/full_fig_p010_5.png] view at source ↗
read the original abstract

Transformer-based CTR models face a growing bottleneck at the residual connection: under Pre-Norm, early user-interest signals are diluted layer by layer; the identity skip cannot forget stale interests; and each layer sees only its immediate predecessor, losing long-range cross-layer dependencies. Recent attention-based residual variants (AttnRes) address parts of this in language models, but drop the protective identity skip and have not been tried in recommendation. Drawing on Dual Path Networks (DPN) and the HORNN view of residuals, we present DeRes, which routes each layer through two parallel paths -- an Identity residual path that preserves first-order feature reuse and gradient flow, and a Block Attention Residual path that attends over compressed outputs of all earlier blocks for high-order recall. A vector-wise gate decides, per hidden dimension, the weight given to each path. We further propose Pointwise AttnRes, replacing the Softmax in the cross-layer attention with SiLU so that multiple past blocks can be activated simultaneously and irrelevant ones receive negative (forgetting) weights -- better aligned with CTR's parallel multi-interest patterns. On a large-scale industrial dataset (331M interactions from a major social-media platform), Criteo (45M), and Avazu (40M), DeRes outperforms twelve baselines including OneTrans, TokenMixer-Large, UniMixer, mHC, and AttnRes, achieving up to +0.32% AUC at under 5% extra FLOPs. Beyond a single operating point, DeRes fits a markedly steeper compute-AUC scaling law (gamma=0.118 vs. 0.071 for OneTrans, a 1.66x gap), so an 8-layer DeRes matches a 16-layer OneTrans -- about 2x compute saving at equivalent AUC. Ablations confirm that the dual-path design outperforms either single path, Identity beats learnable residuals, and SiLU beats Softmax.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The paper proposes DeRes, a dual-path residual for transformer CTR models consisting of an identity path for stability and a Block Attention Residual path (with vector-wise gate and SiLU replacing Softmax) for adaptivity and cross-layer recall. It reports outperformance over 12 baselines (OneTrans, TokenMixer-Large, UniMixer, mHC, AttnRes) on Criteo, Avazu and a 331M-interaction industrial dataset, with gains up to +0.32% AUC at <5% extra FLOPs, plus a steeper compute-AUC scaling law (γ=0.118 vs 0.071) implying an 8-layer DeRes matches a 16-layer OneTrans.

Significance. If the scaling-law difference holds under controlled conditions, the result would be significant for efficient scaling of production CTR models. The design draws explicitly on DPN and HORNN ideas and is supported by ablations showing dual-path superiority, identity over learnable residuals, and SiLU over Softmax. Multi-dataset evaluation and explicit FLOPs reporting are strengths.

major comments (2)
  1. [Abstract] Abstract and scaling-law paragraph: the reported γ values (0.118 vs 0.071) and the claim that 'an 8-layer DeRes matches a 16-layer OneTrans' are load-bearing for the central efficiency claim, yet no details are given on the functional form fitted, the range of depths or widths used, or whether the same random seeds and data order were used across all scaling points.
  2. [Experiments] Experimental section (baseline comparisons): the +0.32% AUC gains are presented against OneTrans, TokenMixer-Large, etc., but the manuscript does not state whether all baselines were re-implemented with the identical optimizer schedule, embedding dimension, and negative-sampling strategy as DeRes; without this, attribution of gains to the dual-path design remains uncertain.
minor comments (2)
  1. [Abstract] The abstract states 'under 5% extra FLOPs' but no table or appendix lists the exact FLOPs or parameter counts for each model variant at each depth.
  2. [Method] Notation for the vector-wise gate and the compressed outputs of earlier blocks is introduced without an accompanying equation or diagram in the main text.

Simulated Author's Rebuttal

2 responses · 0 unresolved

Thank you for the constructive feedback. We address the two major comments below and will revise the manuscript accordingly to improve clarity and reproducibility.

read point-by-point responses

  1. Referee: [Abstract] Abstract and scaling-law paragraph: the reported γ values (0.118 vs 0.071) and the claim that 'an 8-layer DeRes matches a 16-layer OneTrans' are load-bearing for the central efficiency claim, yet no details are given on the functional form fitted, the range of depths or widths used, or whether the same random seeds and data order were used across all scaling points.

    Authors: We agree that the scaling-law analysis requires additional methodological details for full reproducibility. In the revised version we will explicitly state the fitted functional form (AUC = a · compute^γ), the exact range of depths (2–16 layers) and widths used to generate the scaling points, and confirm that identical random seeds and data ordering were used for all compared models at each scale. revision: yes

  2. Referee: [Experiments] Experimental section (baseline comparisons): the +0.32% AUC gains are presented against OneTrans, TokenMixer-Large, etc., but the manuscript does not state whether all baselines were re-implemented with the identical optimizer schedule, embedding dimension, and negative-sampling strategy as DeRes; without this, attribution of gains to the dual-path design remains uncertain.

    Authors: All baselines were re-implemented under identical hyper-parameters, optimizer schedule, embedding dimension, and negative-sampling strategy as DeRes. We will add an explicit statement to this effect in the experimental section of the revised manuscript. revision: yes

Circularity Check

0 steps flagged

No significant circularity

full rationale

The paper's central claims consist of an architectural proposal (dual-path residual with vector-wise gating and SiLU-based Pointwise AttnRes) whose benefits are asserted via direct empirical measurement on three external datasets against twelve independent baselines, plus an observed difference in fitted scaling exponents. No derivation chain reduces any claimed performance quantity to a fitted parameter or self-citation by construction; the scaling-law comparison is presented as an empirical outcome rather than a model-derived prediction, and external citations (DPN, HORNN, AttnRes) supply only high-level motivation without load-bearing uniqueness theorems. The derivation is therefore self-contained against external benchmarks.

Axiom & Free-Parameter Ledger

0 free parameters · 2 axioms · 2 invented entities

The central claim rests on the effectiveness of the newly introduced dual-path residual and SiLU modification, whose benefits are shown only through the reported experiments.

axioms (2)
  • domain assumption Identity residual path preserves first-order feature reuse and gradient flow
    Invoked to motivate the identity path in the dual-path design.
  • domain assumption Block attention over compressed prior-block outputs can supply high-order recall
    Core premise of the Block Attention Residual path.
invented entities (2)
  • DeRes dual-path residual with vector-wise gate no independent evidence
    purpose: To decouple stability from adaptivity in transformer residuals for CTR
    New architectural component introduced in this work.
  • Pointwise AttnRes using SiLU no independent evidence
    purpose: To permit simultaneous multi-block activation and negative forgetting weights
    Novel attention variant proposed here.

pith-pipeline@v0.9.1-grok · 5903 in / 1369 out tokens · 40266 ms · 2026-06-27T19:22:27.537586+00:00 · methodology

discussion (0)

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Reference graph

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