PuDHammer: Experimental Analysis of Read Disturbance Effects of Processing-using-DRAM in Real DRAM Chips

A. Giray Ya\u{g}l{\i}k\c{c}{\i}; Akash Sood; Ataberk Olgun; F. Nisa Bostanc{\i}; Haocong Luo; Ismail Emir Yuksel; Mohammad Sadrosadati; Onur Mutlu; O\u{g}uzhan Canpolat

REVIEW 4 major objections 4 minor 272 references

PuDHammer: Experimental Analysis of Read Disturbance Effects of Processing-using-DRAM in Real DRAM Chips

T0 review · 4 major / 4 minor · reviewed 2026-08-07 · deepseek-v4-flash

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Pith's one-line read This paper shows that Processing-using-DRAM's multiple-row activation patterns, called PuDHammer, make real DDR4 DRAM chips far more vulnerable to read disturbance, cutting the hammer count needed for a first bitflip by up to 158.58x…

desk verdict Genuinely new read-disturbance result, but the 158.58x headline is a cross-vendor minima ratio and needs rewording. read the letter →

arxiv 2506.12947 v1 pith:LNV2T3SV submitted 2025-06-15 cs.AR cs.CR

Ismail Emir Yuksel , Akash Sood , Ataberk Olgun , Oğuzhan Canpolat , Haocong Luo , F. Nisa Bostanc{i} , Mohammad Sadrosadati , A. Giray Yağl{i}kç{i}

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Onur Mutlu

This is my paper · ORCID

classification cs.ARcs.CR

keywords PuDHammerreaddisturbanceRowHammerProcessing-using-DRAMmultiple-rowactivationCoMRASiTargetRefresh

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper tries to establish that the multiple-row activations used by Processing-using-DRAM, which differ fundamentally from ordinary one-row-at-a-time accesses, dramatically worsen DRAM's read disturbance problem. Testing 316 commercial DDR4 chips from four manufacturers, it shows that consecutive multiple-row activation (CoMRA) lowers the minimum hammer count for the first bitflip across all tested vendors, while simultaneous multiple-row activation (SiMRA), observed in one vendor's chips, cuts that count to as low as 26 operations. It also shows that combining PuDHammer with RowHammer is more effective than RowHammer alone, and that PuDHammer can bypass a sampling-based Target Row Refresh mechanism in a tested module. If correct, future in-memory compute systems must treat read disturbance as a first-order design constraint rather than only an attack vector.

What carries the argument

The load-bearing objects are two multiple-row activation patterns: CoMRA, which consecutively activates a source and destination row in the same subarray as used for in-DRAM copy, and SiMRA, which issues an ACT-PRE-ACT sequence to simultaneously activate 2 to 32 rows as used for in-DRAM bitwise operations. The central metric is HC_first, the minimum number of hammer cycles needed to induce the first bitflip in a victim row, measured for each victim row with a bisection search. The argument runs through direct FPGA-controlled experiments on real chips, comparing HC_first against RowHammer and RowPress baselines across temperature, data pattern, timing parameters, and spatial location, and testing the same patterns against a reverse-engineered sampling TRR mechanism.

What would settle it

Run the identical ACT-PRE-ACT SiMRA pattern with 3ns timing on a Samsung, Micron, or Nanya DDR4 module at 80 degrees Celsius: if no simultaneous row activation occurs or HC_first remains at RowHammer levels, the 158.58x reduction claim does not generalize beyond the observed chips. Conversely, testing a second SK Hynix module with a different die revision under the same TRR-bypass procedure would settle whether the 11340x bitflip ratio is reproducible or specific to the one tested module.

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Extended reading notes

Core claim

The central discovery is that multiple-row activation patterns are not just a new way to trigger RowHammer but a categorically more damaging read disturbance mechanism. Both CoMRA and SiMRA reduce the minimum hammer count required for the first bitflip, HC_first, with the lowest observed value for double-sided SiMRA being 26 versus 4123 for RowHammer. The effect is not proportional to the number of simultaneously activated rows, is sensitive to data pattern and row-on time, and flips bits in the opposite direction from RowHammer, suggesting a different underlying physical mechanism. Against a sampling-based TRR mechanism in one SK Hynix module, SiMRA induced 11340x more bitflips than RowHammer, and the paper concludes that PuD operations turn read disturbance into a serious reliability and security concern for future systems.

Load-bearing premise

The central claim assumes that the dramatic HC_first reductions, especially SiMRA's 158.58x result and the TRR bypass, observed in the chips where they appear will hold for other vendors, die revisions, and future DDR5 or LPDDR PuD hardware; the paper itself reports SiMRA was not observed in Samsung, Micron, or Nanya chips and does not know whether these operations can be performed in COTS LPDDRx or DDR5 chips.

Editorial extensions

If this is right

PuD accelerators must budget for bitflip risk: on one tested module, just 26 SiMRA operations can flip a bit before a periodic refresh, a time span far shorter than the refresh window.
Existing RowHammer mitigations such as TRR are insufficient against PuDHammer, because the two-command SiMRA pattern evades sampling-based TRR and induces far more bitflips than RowHammer.
Adapting the industry-standard PRAC mitigation to PuDHammer would require updating counters for every simultaneously activated row, and the paper's evaluation shows this costs an average 48.26% system performance overhead.
Combining RowHammer with CoMRA and SiMRA cuts HC_first by 1.66x on average compared to RowHammer alone, so even workloads that mix conventional accesses with PuD operations face elevated read disturbance risk.
Future PuD chip designs should separate compute rows from storage rows, cluster simultaneous activations, or weight activation counts per operation type to keep read disturbance under control.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

Our inference: the opposite bitflip direction and different temperature dependence suggest SiMRA is not simply RowHammer with more aggressor rows; a device-level model of the simultaneous-activation mechanism would likely explain why HC_first reductions are non-monotonic with row count.
Our inference: because SiMRA was not observed in Samsung, Micron, or Nanya chips in this study, the 158.58x reduction and the TRR bypass may be vendor- and die-specific; DDR5 and LPDDR5 testing will determine whether PuDHammer is a general threat or a targeted one.
Our inference: a practical defensive extension would be a runtime scan that identifies SiMRA-capable chips and disables simultaneous-activation PuD operations on those modules, or applies weighted activation counting only when such capability is detected.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Two things to know. First, this paper reports a genuinely new phenomenon: read disturbance from consecutive and simultaneous multi-row activation (CoMRA/SiMRA) in real DDR4 chips, with a large sample (316 chips, four vendors) and careful experimental controls. That alone makes it worth engaging with. Second, the signature number—"up to 158.58x reduction in HC_first"—does not mean what the abstract implies. The stress-test note is right: 158.58 = 4123/26, where 4123 is the lowest RowHammer HC_first measured (on a Micron chip) and 26 is the lowest SiMRA HC_first measured (on an SK Hynix chip). On the SK Hynix module that gives 26, the RowHammer minimum is 25,000. So the headline is a cross-vendor, cross-die ratio of minima, not a same-chip comparison. The paper sometimes phrases it as "one tested victim row shows a 158.58x reduction," which the data cannot support. The honest same-module ratio would be 25,000/26 ≈ 961x, a different and arguably more striking number—but the point stands that the current wording overstates the causal effect.

What the paper does well: the methodology is solid—refresh disabled, ECC-free modules, bisection search, vendor-specific row mapping, and enough chips to see distributions. The observations that CoMRA reduces HC_first across 99% of rows, that SiMRA is data-pattern and temperature sensitive with opposite bitflip direction to RowHammer, and that a tested TRR mechanism fails against SiMRA are all new and worth taking seriously. The paper also self-limits in several places: SiMRA was only observed in SK Hynix, the TRR bypass is on one module, and the authors admit DDR5/LPDDR behavior is unknown.

Soft spots beyond the headline: no raw data or scripts are shipped, which matters for an empirical study this large. The PRAC overhead result (48.26%) depends on self-measured weighted counters (SiMRA=200, CoMRA=10) and a synthetic PuD workload; it's a reasonable first estimate, not a definitive number. And the abstract/introduction over-generalize the four-vendor claim for SiMRA when only one vendor exhibited it.

Overall: this is a solid experimental paper with an over-claimed headline. It deserves serious peer review. A good referee should push for a reworded severity estimate and clearer separation of cross-vendor vs same-chip comparisons, but the core finding is credible and important for anyone working on PuD or read disturbance.

Referee Report

4 major / 4 minor

Summary. This paper presents the first experimental study of read-disturbance effects caused by multiple-row activation (PuD) operations in real DDR4 DRAM chips. The authors use a DRAM Bender FPGA infrastructure to test 316 chips from SK Hynix, Micron, Samsung, and Nanya, disabling refresh within the refresh window and using ECC-free modules. They define HC_first and characterize CoMRA and SiMRA under various data patterns, temperatures, timing parameters, and row locations; study combined RowHammer+PuD patterns; show TRR bypass in one SK Hynix module; and adapt PRAC with weighted counting, reporting 48.26% average system performance overhead. The paper reports 26 observations and 9 takeaways.

Significance. The study addresses a genuinely open and timely question: PuD operations deliberately violate single-row activation assumptions, so their read-disturbance behavior cannot be inferred from RowHammer studies. The experimental infrastructure is a strength: a large multi-vendor chip sample, careful elimination of interference (refresh disabled within the refresh window, ECC-free modules), bisection-based HC_first search with a 1% convergence criterion, and vendor-specific logical-to-physical row mapping. The finding that double-sided SiMRA can flip bits after 26 operations in a SK Hynix module and can bypass TRR in a tested module is important for the security and reliability of future PuD systems, as is the observation that CoMRA lowers HC_first across all four vendors. These contributions are clouded by the unsupported cross-vendor derivation of the headline 158.58x ratio and by an overstatement that SiMRA was observed in all four manufacturers; the paper's own Section 5.3 limits SiMRA to SK Hynix chips. The appended limitation discussion about DDR5/LPDDR is honest and appropriate.

major comments (4)

[Abstract; §5.3, Observation 12; Fig. 13] The claim that 'PuDHammer... causing up to 158.58x reduction in HC_first compared to RowHammer' and the Observation 12 sentence 'one tested victim row shows a 158.58x reduction' are not supported as per-row comparisons. Fig. 13 (right) shows that 158.58 = 4,123 / 26, where 4,123 is the RowHammer minimum from a Micron F-die chip and 26 is the SiMRA minimum from a SK Hynix A-die chip. Table 2 reports that the same SK Hynix module whose SiMRA minimum is 26 has a RowHammer minimum of 25,000, so no victim row in that module can exhibit a 158.58x reduction relative to its own RowHammer HC_first. Because this ratio is the first quantitative claim in the abstract, the wording must be corrected: either report it as a cross-chip minimum-to-minimum comparison (and remove the 'one tested victim row' wording) or provide a same-module paired comparison; for that module the same-module ratio is 25,000/26 ≈ 961x, which is even larger but has a different meaning.
[Introduction, p. 2; §5.3] The Introduction states that 'both CoMRA and SiMRA decrease the minimum hammer count required to induce the first bitflip (HC_first) in all tested DRAM chips from four manufacturers.' This is contradicted by §5.3, which says 'we do not observe SiMRA in Samsung, Micron, and Nanya chips.' The vendor-generality of SiMRA is therefore overstated; CoMRA appears to be the only pattern observed across all four manufacturers. Please revise the Introduction (and any summary that repeats this claim) to attribute CoMRA to all four vendors and SiMRA only to SK Hynix, or to add an explicit qualifier.
[§5.3, Observation 12; Fig. 13] Observation 12 cites a 124.94x reduction 'when performing double-sided SiMRA with 4-row activation (32-row activation).' This conflicts with the text immediately preceding it, which states that no activated row group for 32-row activation sandwiches a victim row, so double-sided SiMRA is shown only up to SiMRA-16. The value 124.94 corresponds to 4,123/33, the SiMRA-16 minimum in Fig. 13 (right), so the parenthetical should read 16-row activation, not 32-row activation. This correction is important because the example is used to support the non-monotonicity claim.
[§8.2, PRAC-PO-WC] The security assertion that 'PRAC-PO securely prevents all read disturbance bitflips when configured for an RDT of≈20' is not supported for combined access patterns. The weights (200 for SiMRA, 10 for CoMRA) are derived from the global single-pattern minima (4K/20 and 4K/400), but §6 demonstrates that RowHammer combined with CoMRA/SiMRA reduces HC_first beyond RowHammer alone. The paper does not test whether a mixed sequence whose weighted sum is below RDT can induce a bitflip before the counter triggers an RFM. Please either add such validation or qualify the security claim and the 48.26% overhead conclusion as applying only to single-pattern PuDHammer, not to the combined patterns characterized in §6.

minor comments (4)

[Section 3 heading] The heading 'Metholodogy' should be 'Methodology'.
[Section 4.2] The line 'HC f irstHC f irstHC f irst Algorithm' appears to be a text duplication artifact; the heading should be a single 'HC_first Algorithm'.
[Fig. 13] The axis labels contain typos: '#Simultaneosly Activated Rows' should be '#Simultaneously Activated Rows', and 'HCﬁrst Change' should be 'HC_first Change'.
[Section 8.2] The text says 'lowest HC_first values for RowHammer, CoMRA, and SiMRA are ≈4K, ≈400, and ≈20' but Table 2 reports 4,123, 447, and 26; the rounding is acceptable if stated as approximate, but please make the relationship explicit to avoid confusion with the later RDT of 20.

Circularity Check

0 steps flagged · score 1.0 of 10

No significant circularity; the empirical derivation is self-contained, though the 158.58x headline is a cross-chip minima ratio and the PRAC overhead depends on internally measured weights.

full rationale

We find no circular step in the paper's central chain. The main results (HC_first values, bitflip counts, and TRR bypass) are direct measurements from 316 COTS chips using the DRAM Bender infrastructure; they are not outputs of a model whose inputs are the conclusions. The 158.58x figure is the quotient of the global minima plotted in Fig. 13 (4123/26), so the abstract's wording that PuDHammer 'causes' this reduction on a victim row is not supported as a paired same-row comparison; this is a validity caveat, not circularity, because the ratio is still computed from raw measurements rather than from a fitted parameter. Similarly, the PRAC analysis in Section 8.2 sets weights (SiMRA=200, CoMRA=10) from this paper's own lowest HC_first values, so the 48.26% overhead is conditional on internally calibrated thresholds; the paper presents this as an adaptation/evaluation with stated assumptions, not as an independent prediction. Appendix B explicitly limits external validity to DDR4 and notes that it does not know whether SiMRA or CoMRA can be performed in COTS LPDDRx/DDR5 chips; this limits generality but does not make the derivation circular. Self-citations (DRAM Bender, U-TRR, and prior multiple-row-activation demonstrations) are methodology and tooling citations, and the paper independently reverse-engineers subarray boundaries and simultaneously activated rows, so no load-bearing argument reduces to a self-citation. Score 1 reflects only the minor self-measurement dependence in the mitigation exercise.

Assumptions & free parameters 2 free parameters · 3 assumptions · 0 invented entities

The central characterization has no fitted model parameters; HC_first values are measurements. The free parameters listed affect only the mitigation evaluation in Section 8.2, where thresholds and multipliers are taken from this paper's own measured minima. The axioms are the standard DRAM-testing assumptions plus the load-bearing representativeness assumption described under weakest_assumption.

free parameters (2)

PRAC-PO read disturbance threshold (RDT) = approximately 20 activations
Set in Section 8.2 to the lowest SiMRA HC_first measured in this same paper; used for the naive PRAC-PO baseline and as the basis for weighted counting. It is a design parameter derived from the paper's own data, not an independent external value.
PRAC weighted-count multipliers for SiMRA and CoMRA = SiMRA=200, CoMRA=10, relative to RowHammer=1
Chosen in Section 8.2 as ratios of measured HC_first minima, roughly 4K/20 and 4K/400. These multipliers drive the reported 48.26% average overhead and are not validated against independent chips or real PuD workloads.

assumptions (3)

domain assumption Issuing the timing-violating ACT and PRE command sequences described in Sections 4.1 and 5.1 produces the same data operations as real PuD hardware, with CoMRA for copy and SiMRA for bitwise compute.
The paper relies on the established PuD characterization literature, but the equivalence between these timing-violating sequences on COTS chips and future PuD implementations is assumed, not proven here.
ad hoc to paper The tested 316-chip sample represents the read disturbance behavior of modern DRAM broadly, and of future PuD-enabled DRAM.
SiMRA was only observed in SK Hynix chips, TRR bypass only in one SK Hynix module, and Appendix B admits DDR5 and LPDDR behavior is unknown. This representativeness assumption is load-bearing for the headline claims.
domain assumption Disabling periodic refresh and testing within the refresh window isolates read disturbance bitflips from retention failures.
This is the standard methodology from prior works used in Section 3.1; the experiment assumes refresh interference is fully eliminated by these controls.

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Pith. "Pith review of PuDHammer: Experimental Analysis of Read Disturbance Effects of Processing-using-DRAM in Real DRAM Chips." pith.science (2026). https://pith.science/paper/LNV2T3SV

@misc{pith2026250612947,
  author       = {Pith},
  title        = {Pith review of: PuDHammer: Experimental Analysis of Read Disturbance Effects of Processing-using-DRAM in Real DRAM Chips},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/LNV2T3SV}},
  note         = {Machine review of arXiv:2506.12947}
}

abstract

Processing-using-DRAM (PuD) is a promising paradigm for alleviating the data movement bottleneck using DRAM's massive internal parallelism and bandwidth to execute very wide operations. Performing a PuD operation involves activating multiple DRAM rows in quick succession or simultaneously, i.e., multiple-row activation. Multiple-row activation is fundamentally different from conventional memory access patterns that activate one DRAM row at a time. However, repeatedly activating even one DRAM row (e.g., RowHammer) can induce bitflips in unaccessed DRAM rows because modern DRAM is subject to read disturbance. Unfortunately, no prior work investigates the effects of multiple-row activation on DRAM read disturbance. In this paper, we present the first characterization study of read disturbance effects of multiple-row activation-based PuD (which we call PuDHammer) using 316 real DDR4 DRAM chips from four major DRAM manufacturers. Our detailed characterization show that 1) PuDHammer significantly exacerbates the read disturbance vulnerability, causing up to 158.58x reduction in the minimum hammer count required to induce the first bitflip ($HC_{first}$), compared to RowHammer, 2) PuDHammer is affected by various operational conditions and parameters, 3) combining RowHammer with PuDHammer is more effective than using RowHammer alone to induce read disturbance error, e.g., doing so reduces $HC_{first}$ by 1.66x on average, and 4) PuDHammer bypasses an in-DRAM RowHammer mitigation mechanism (Target Row Refresh) and induces more bitflips than RowHammer. To develop future robust PuD-enabled systems in the presence of PuDHammer, we 1) develop three countermeasures and 2) adapt and evaluate the state-of-the-art RowHammer mitigation standardized by industry, called Per Row Activation Counting (PRAC). We show that the adapted PRAC incurs large performance overheads (48.26%, on average).

Figures

Figures reproduced from arXiv: 2506.12947 by the authors.

**Figure 2.** Our DRAM Bender [75] based experimental setup. Eliminating Interference Sources. To observe read disturbance bitflips at the circuit level, we eliminate potential sources of interference, by taking three measures, similar to the methodology used by prior works [125,144–146,153]. First, we disable periodic refresh during the execution of test programs to prevent potential on-DRAM-die TRR mechanisms [119,125] from re… view at source ↗

**Figure 3.** Example of a double-sided CoMRA attack (a), a single [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗

Figures from the paper (19 more)

**Figure 4.** Figure 4: Distribution of the change in HCf irst with doublesided CoMRA compared to double-sided RowHammer (left) and the lowest HCf irst observed with double-sided CoMRA and RowHammer (right) for each manufacturer. Observation 1. Hammering with double-sided CoMRA significantl…

**Figure 5.** Figure 5: HCf irst distribution of double-sided CoMRA with different aggressor data patterns. Victim rows have negated aggressor data pattern. Observation 3. CheckerBoard pattern (i.e., 0x55/0xAA) is, in general, the most effective data pattern among the ones tested. When perfor…

**Figure 7.** Figure 7: HCf irst of single-sided CoMRA and RowHammer. Observation 5. Single-sided CoMRA decreases HCf irst compared to single-sided RowHammer and exhibits similar HCf irst distribution with far double-sided RowHammer. We observe that, for all four manufacturers, single-sided C…

**Figure 6.** Figure 6: HCf irst distribution of hammering with double-sided CoMRA at different DRAM chip temperatures. 1Due to the complicated true/anti cell pattern of Nanya chips, we could not observe bitflips within a refresh window with 0xFF and 0x00 data patterns. Observation 4. Read di…

**Figure 9.** Figure 9: HCf irst distribution of double-sided CoMRA for varying numbers of latency. 7.5ns to 12ns, average HCf irst increases by 3.10×, 1.18×, 1.17×, and 3.01× for SK Hynix, Micron, Samsung, and Nanya. We hypothesize that the CoMRA access pattern becomes more of a RowHammer a…

**Figure 8.** Figure 8: HCf irst distribution of double-sided CoMRA and RowPress with different tAggOn values. Observation 6. When performing double-sided CoMRA, increasing tAggOn significantly reduces HCf irst. For example, in Micron chips, CoMRA with tAggOn=70.2µs leads to a 78.74× reductio…

**Figure 11.** Figure 11: HCf irst of double-sided CoMRA based on the victim row’s location in a subarray. Observation 10. HCf irst varies based on the victim row’s location in a subarray. We observe that the physical location of the victim row in the subarray can lead to variations in average…

**Figure 12.** Figure 12: Example of (a) double-sided SiMRA attack, (b) singlesided SiMRA attack, and (c) their access pattern. Access Pattern & Operation. Fig. 12c illustrates our access pattern to hammer using SiMRA. Our attack consists of two key steps. First, we issue an ACT-PRE-ACT comma…

**Figure 13.** Figure 13: Distribution of the change in HCf irst change with double-sided SiMRA compared to double-sided RowHammer (left) and the lowest HCf irst observed with double-sided SiMRA and RowHammer (right). For double-sided SiMRA with 2-, 4-, 8- and 16-row activation, respectively …

**Figure 15.** Figure 15: HCf irst distribution of double-sided SiMRA at different temperatures and numbers of simultaneously activated rows. Observation 15. HCf irst decreases as temperature increases. Increasing temperature consistently decreases HCf irst for all N. For example, from 50◦C …

**Figure 14.** Figure 14: HCf irst distribution of double-sided SiMRA for different aggressor data patterns and numbers of activated rows. Victim rows have negated aggressor data pattern. Observation 13. Data pattern significantly affects HCf irst. We observe that, across all tested N values,…

**Figure 16.** Figure 16: HCf irst distribution of single-sided SiMRA with varying numbers of activated rows and RowHammer. Observation 17. HCf irst consistently decreases as the number of simultaneously activated rows increases when performing single-sided SiMRA. For example, average (lowes…

**Figure 19.** Figure 19: HCf irst distribution of double-sided SiMRA based on the victim row’s location in a subarray. Observation 21. The effectiveness of SiMRA depends on the victim row’s location in a subarray. HCf irst varies across different victim row locations in a subarray, and this v…

**Figure 17.** Figure 17: HCf irst distribution of RowPress and SiMRA with varying numbers of row activations and tAggOn values. Observation 18. HCf irst decreases greatly as tAggOn increases. For example, when tAggOn increases from 36ns to 70.2µs with SiMRA, average HCf irst decreases by bet…

**Figure 18.** Figure 18: HCf irst distribution of double-sided SiMRA for different timing delays between ACT-PRE and PRE-ACT. Observation 19. Increasing PRE-ACT latency slightly decreases HCf irst. For example, SiMRA-16 with ACT→PRE=3ns, average HCf irst decreases by 1.23× when PRE→ACT incr…

**Figure 22.** Figure 22: Change in HCf irst (left) and absolute HCf irst values (right) when combining RowHammer and SiMRA. Hammer count of 0% represents performing RowHammer only. Observation 23. DRAM rows tend to experience lower HCf irst when performing combined RowHammer and SiMRA. Combin…

**Figure 23.** Figure 23: shows the change in HCf irst when we combine doublesided RowHammer with CoMRA and SiMRA together (e.g., Fig. 20b- 3 ). 0 10 50 90 Hammer Count as a Percentage of SiMRA’s HCfirst 25 0 −25 −50 −75 HC −100 first Change Hammer Count as a Percentage of CoMRA’s HCfirst 0 1…

**Figure 24.** Figure 24: Number of bitflips in victim rows averaged across [PITH_FULL_IMAGE:figures/full_fig_p012_24.png]

**Figure 25.** Figure 25: Performance impact of evaluated PRAC-PO imple [PITH_FULL_IMAGE:figures/full_fig_p014_25.png]

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Reference graph

Works this paper leans on

272 extracted references · 73 canonical work pages

[1]

Processing Data Where It Makes Sense: Enabling In-Memory Computation,

O. Mutlu, S. Ghose, J. Gómez-Luna, and R. Ausavarungnirun, “Processing Data Where It Makes Sense: Enabling In-Memory Computation, ” inMicroprocessors and Microsystems, 2019

2019
[2]

A Modern Primer on Processing in Memory,

O. Mutlu, S. Ghose, J. Gómez-Luna, and R. Ausavarungnirun, “A Modern Primer on Processing in Memory, ” inEmerging Computing: From Devices to Systems — Looking Beyond Moore and Von Neumann. Springer, 2021. [Online]. Available: https://arxiv.org/abs/2012.03112

arXiv 2021
[3]

Memory Scaling: A Systems Architecture Perspective,

O. Mutlu, “Memory Scaling: A Systems Architecture Perspective, ” inIMW, 2013

2013
[4]

Research Problems and Opportunities in Memory Systems,

O. Mutlu and L. Subramanian, “Research Problems and Opportunities in Memory Systems, ”SUPERFRI, 2014

2014
[5]

The Tail at Scale,

J. Dean and L. A. Barroso, “The Tail at Scale, ”CACM, 2013

2013
[6]

Profiling a Warehouse-Scale Computer,

S. Kanev, J. P. Darago, K. Hazelwood, P. Ranganathan, T. Moseley, G.-Y. Wei, and D. Brooks, “Profiling a Warehouse-Scale Computer, ” inISCA, 2015

2015
[7]

Clearing the Clouds: A Study of Emerging Scale-Out Workloads on Modern Hardware,

M. Ferdman, A. Adileh, O. Kocberber, S. Volos, M. Alisafaee, D. Jevdjic, C. Kaynak, A. D. Popescu, A. Ailamaki, and B. Falsafi, “Clearing the Clouds: A Study of Emerging Scale-Out Workloads on Modern Hardware, ” inASPLOS, 2012. 15

2012
[8]

Bigdatabench: A Big Data Benchmark Suite from Internet Services,

L. Wang, J. Zhan, C. Luo, Y. Zhu, Q. Yang, Y. He, W. Gao, Z. Jia, Y. Shi, S. Zhanget al., “Bigdatabench: A Big Data Benchmark Suite from Internet Services, ” inHPCA, 2014

2014

Show all 272 references

[9]

Enabling Practical Processing in and Near Memory For Data-Intensive Computing,

O. Mutlu, S. Ghose, J. Gómez-Luna, and R. Ausavarungnirun, “Enabling Practical Processing in and Near Memory For Data-Intensive Computing, ” inDAC, 2019

2019
[10]

Intelligent Architectures for Intelligent Machines,

O. Mutlu, “Intelligent Architectures for Intelligent Machines, ” inVLSI-DAT, 2020

2020
[11]

Processing-in- Memory: A Workload-Driven Perspective,

S. Ghose, A. Boroumand, J. S. Kim, J. Gómez-Luna, and O. Mutlu, “Processing-in- Memory: A Workload-Driven Perspective, ”IBM JRD, 2019

2019
[12]

DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks,

G. F. Oliveira, J. Gómez-Luna, L. Orosa, S. Ghose, N. Vijaykumar, I. Fernandez, M. Sadrosadati, and O. Mutlu, “DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks, ”IEEE Access, 2021

2021
[13]

Google Workloads for Con- sumer Devices: Mitigating Data Movement Bottlenecks,

A. Boroumand, S. Ghose, Y. Kim, R. Ausavarungnirun, E. Shiu, R. Thakur, D. Kim, A. Kuusela, A. Knies, P. Ranganathan, and O. Mutlu, “Google Workloads for Con- sumer Devices: Mitigating Data Movement Bottlenecks, ” inASPLOS, 2018

2018
[14]

Google Neural Network Models for Edge Devices: Analyzing and Mitigating Machine Learning Inference Bottlenecks,

A. Boroumand, S. Ghose, B. Akin, R. Narayanaswami, G. F. Oliveira, X. Ma, E. Shiu, and O. Mutlu, “Google Neural Network Models for Edge Devices: Analyzing and Mitigating Machine Learning Inference Bottlenecks, ” inPACT, 2021

2021
[15]

Reducing Data Movement Energy via Online Data Clustering and Encoding,

S. Wang and E. Ipek, “Reducing Data Movement Energy via Online Data Clustering and Encoding, ” inMICRO, 2016

2016
[16]

Quantifying the Energy Cost of Data Movement for Emerging Smart Phone Workloads on Mobile Platforms,

D. Pandiyan and C.-J. Wu, “Quantifying the Energy Cost of Data Movement for Emerging Smart Phone Workloads on Mobile Platforms, ” inIISWC, 2014

2014
[17]

EDEN: Enabling Energy-Efficient, High-Performance Deep Neural Network Inference Using Approximate DRAM,

S. Koppula, L. Orosa, A. G. Yağlıkçı, R. Azizi, T. Shahroodi, K. Kanellopoulos, and O. Mutlu, “EDEN: Enabling Energy-Efficient, High-Performance Deep Neural Network Inference Using Approximate DRAM, ” inMICRO, 2019

2019
[18]

Co-Architecting Controllers and DRAM to Enhance DRAM Process Scaling,

U. Kang, H.-S. Yu, C. Park, H. Zheng, J. Halbert, K. Bains, S. Jang, and J. S. Choi, “Co-Architecting Controllers and DRAM to Enhance DRAM Process Scaling, ” in The Memory Forum, 2014

2014
[19]

Reflections on the Memory Wall

S. A. McKeeet al., “Reflections on the Memory Wall.”CF, 2004

2004
[20]

The Memory Gap and the Future of High Performance Memories,

M. V. Wilkes, “The Memory Gap and the Future of High Performance Memories, ” CAN, 2001

2001
[21]

A Case for Exploiting Subarray-Level Parallelism (SALP) in DRAM,

Y. Kim, V. Seshadri, D. Lee, J. Liu, O. Mutlu, Y. Kim, V. Seshadri, D. Lee, J. Liu, and O. Mutlu, “A Case for Exploiting Subarray-Level Parallelism (SALP) in DRAM, ” in ISCA, 2012

2012
[22]

Hitting the Memory Wall: Implications of the Obvious,

W. A. Wulf and S. A. McKee, “Hitting the Memory Wall: Implications of the Obvious, ” CAN, 1995

1995
[23]

Demystifying Complex Workload–DRAM Interactions: An Experimental Study,

S. Ghose, T. Li, N. Hajinazar, D. S. Cali, and O. Mutlu, “Demystifying Complex Workload–DRAM Interactions: An Experimental Study, ” inSIGMETRICS, 2020

2020
[24]

A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing,

J. Ahn, S. Hong, S. Yoo, O. Mutlu, and K. Choi, “A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing, ” inISCA, 2015

2015
[25]

PIM-Enabled Instructions: A Low-Overhead, Locality-Aware Processing-in-Memory Architecture,

J. Ahn, S. Yoo, O. Mutlu, and K. Choi, “PIM-Enabled Instructions: A Low-Overhead, Locality-Aware Processing-in-Memory Architecture, ” inISCA, 2015

2015
[26]

Transparent Offloading and Mapping (TOM): Enabling Programmer-Transparent Near-Data Processing in GPU Systems,

K. Hsieh, E. Ebrahimi, G. Kim, N. Chatterjee, M. O’Connor, N. Vijaykumar, O. Mutlu, and S. W. Keckler, “Transparent Offloading and Mapping (TOM): Enabling Programmer-Transparent Near-Data Processing in GPU Systems, ” inISCA, 2016

2016
[27]

FIGARO: Improving System Performance via Fine-Grained In-DRAM Data Relocation and Caching,

Y. Wang, L. Orosa, X. Peng, Y. Guo, S. Ghose, M. Patel, J. S. Kim, J. G. Luna, M. Sadrosadati, N. M. Ghiasiet al., “FIGARO: Improving System Performance via Fine-Grained In-DRAM Data Relocation and Caching, ” inMICRO, 2020

2020
[28]

It’s the Memory, Stupid!

R. Sites, “It’s the Memory, Stupid!”MPR, 1996

1996
[29]

Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology,

V. Seshadri, D. Lee, T. Mullins, H. Hassan, A. Boroumand, J. Kim, M. A. Kozuch, O. Mutlu, P. B. Gibbons, and T. C. Mowry, “Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology, ” inMICRO, 2017

2017
[30]

Fast Bulk Bitwise AND and OR in DRAM,

V. Seshadri, K. Hsieh, A. Boroumand, D. Lee, M. A. Kozuch†, O. Mutlu, P. B. Gibbons, and T. C. Mowry, “Fast Bulk Bitwise AND and OR in DRAM, ” inCAL, 2015

2015
[31]

In-DRAM Bulk Bitwise Execution Engine,

V. Seshadri and O. Mutlu, “In-DRAM Bulk Bitwise Execution Engine, ” arXiv:1905.09822, 2019

1905 arXiv
[32]

SIMDRAM: A Framework for Bit-Serial SIMD Processing Using DRAM,

N. Hajinazar, G. F. Oliveira, S. Gregorio, J. D. Ferreira, N. M. Ghiasi, M. Patel, M. Alser, S. Ghose, J. Gómez-Luna, and O. Mutlu, “SIMDRAM: A Framework for Bit-Serial SIMD Processing Using DRAM, ” inASPLOS, 2021

2021
[33]

Memory-Centric Computing: Recent Advances in Processing-in-DRAM,

O. Mutlu, A. Olgun, G. F. Oliveira, and I. E. Yuksel, “Memory-Centric Computing: Recent Advances in Processing-in-DRAM, ” inIEDM, 2024

2024
[34]

Memory-Centric Computing: Solving Com- puting’s Memory Problem,

O. Mutlu, A. Olgun, and I. E. Yuksel, “Memory-Centric Computing: Solving Com- puting’s Memory Problem, ” inIMW, 2025

2025
[35]

Bitmap Index Design and Evaluation,

C.-Y. Chan and Y. E. Ioannidis, “Bitmap Index Design and Evaluation, ” inSIGMOD, 1998

1998
[36]

Bitmap Index Design Choices and Their Perfor- mance Implications,

E. O’Neil, P. O’Neil, and K. Wu, “Bitmap Index Design Choices and Their Perfor- mance Implications, ” inIDEAS, 2007

2007
[37]

WideTable: An Accelerator for Analytical Data Processing,

Y. Li and J. M. Patel, “WideTable: An Accelerator for Analytical Data Processing, ” VLDB, 2014

2014
[38]

BitWeaving: Fast Scans for Main Memory Data Processing,

——, “BitWeaving: Fast Scans for Main Memory Data Processing, ” inSIGMOD, 2013

2013
[39]

BitFunnel: Revisiting Signatures for Search,

B. Goodwin, M. Hopcroft, D. Luu, A. Clemmer, M. Curmei, S. Elnikety, and Y. He, “BitFunnel: Revisiting Signatures for Search, ” inSIGIR, 2017

2017
[40]

RowClone: Fast and Energy- Efficient In-DRAM Bulk Data Copy and Initialization,

V. Seshadri, Y. Kim, C. Fallin, D. Lee, R. Ausavarungnirun, G. Pekhimenko, Y. Luo, O. Mutlu, P. B. Gibbons, M. A. Kozuch, and T. Mowry, “RowClone: Fast and Energy- Efficient In-DRAM Bulk Data Copy and Initialization, ” inMICRO, 2013

2013
[41]

FastBit: An Efficient Indexing Technology for Accelerating Data-Intensive Science,

K. Wu, “FastBit: An Efficient Indexing Technology for Accelerating Data-Intensive Science, ” inJournal of Physics: Conference Series, 2005

2005
[42]

Encoded Bitmap Indexing for Data Warehouses,

M.-C. Wu and A. P. Buchmann, “Encoded Bitmap Indexing for Data Warehouses, ” inICDE, 1998

1998
[43]

Redis bitmaps,

Redis, “Redis bitmaps, ” https://redis.io/docs/data-types/bitmaps/
[44]

Understanding Bulk-Bitwise Processing In-Memory Through Database Analytics,

B. Perach, R. Ronen, B. Kimelfeld, and S. Kvatinsky, “Understanding Bulk-Bitwise Processing In-Memory Through Database Analytics, ”ETC, 2023

2023
[45]

Bluedbm: An Appliance for Big Data Analytics,

S.-W. Jun, M. Liu, S. Lee, J. Hicks, J. Ankcorn, M. King, and S. Xu, “Bluedbm: An Appliance for Big Data Analytics, ”ISCA, 2015

2015
[46]

Catalina: In-Storage Processing Acceleration for Scalable Big Data Analytics,

M. Torabzadehkashi, S. Rezaei, A. Heydarigorji, H. Bobarshad, V. Alves, and N. Bagherzadeh, “Catalina: In-Storage Processing Acceleration for Scalable Big Data Analytics, ” inPDP, 2019

2019
[47]

SmartSSD: FPGA Accelerated Near-Storage Data Analytics on SSD,

J. H. Lee, H. Zhang, V. Lagrange, P. Krishnamoorthy, X. Zhao, and Y. S. Ki, “SmartSSD: FPGA Accelerated Near-Storage Data Analytics on SSD, ”CAL, 2020

2020
[48]

SISA: Set- Centric Instruction Set Architecture for Graph Mining on Processing-in-Memory Systems,

M. Besta, R. Kanakagiri, G. Kwasniewski, R. Ausavarungnirun, J. Beránek, K. Kanel- lopoulos, K. Janda, Z. Vonarburg-Shmaria, L. Gianinazzi, I. Stefanet al., “SISA: Set- Centric Instruction Set Architecture for Graph Mining on Processing-in-Memory Systems, ” inMICRO, 2021

2021
[49]

Direction-Optimizing Breadth-First Search,

S. Beamer, K. Asanovic, and D. Patterson, “Direction-Optimizing Breadth-First Search, ” inSC, 2012

2012
[50]

Pinatubo: A Processing-in-Memory Architecture for Bulk Bitwise Operations in Emerging Non-Volatile Memories,

S. Li, C. Xu, Q. Zou, J. Zhao, Y. Lu, and Y. Xie, “Pinatubo: A Processing-in-Memory Architecture for Bulk Bitwise Operations in Emerging Non-Volatile Memories, ” in DAC, 2016

2016
[51]

Parabit: Processing Parallel Bitwise Operations in NAND Flash Memory Based SSDs,

C. Gao, X. Xin, Y. Lu, Y. Zhang, J. Yang, and J. Shu, “Parabit: Processing Parallel Bitwise Operations in NAND Flash Memory Based SSDs, ” inMICRO, 2021

2021
[52]

Gatekeeper: A New Hardware Architecture For Accelerating Pre-Alignment In DNA Short Read Mapping,

M. Alser, H. Hassan, H. Xin, O. Ergin, O. Mutlu, and C. Alkan, “Gatekeeper: A New Hardware Architecture For Accelerating Pre-Alignment In DNA Short Read Mapping, ” inBioinformatics, 2017

2017
[53]

BitPAl: A Bit-Parallel, General Integer- Scoring Sequence Alignment Algorithm,

J. Loving, Y. Hernandez, and G. Benson, “BitPAl: A Bit-Parallel, General Integer- Scoring Sequence Alignment Algorithm, ”Bioinformatics, 2014

2014
[54]

Shifted Hamming Distance: A Fast and Accurate SIMD-Friendly Filter to Accelerate Alignment Verification in Read Mapping,

H. Xin, J. Greth, J. Emmons, G. Pekhimenko, C. Kingsford, C. Alkan, and O. Mutlu, “Shifted Hamming Distance: A Fast and Accurate SIMD-Friendly Filter to Accelerate Alignment Verification in Read Mapping, ”Bioinformatics, 2015

2015
[55]

GenASM: A High- Performance, Low-Power Approximate String Matching Acceleration Framework for Genome Sequence Analysis,

D. S. Cali, G. S. Kalsi, Z. Bingöl, C. Firtina, L. Subramanian, J. S. Kim, R. Ausavarung- nirun, M. Alser, J. Gomez-Luna, A. Boroumandet al., “GenASM: A High- Performance, Low-Power Approximate String Matching Acceleration Framework for Genome Sequence Analysis, ” inMICRO, 2020

2020
[56]

GRIM-Filter: Fast Seed Filtering in Read Mapping using Emerging Memory Technologies,

J. S. Kim, D. Senol, H. Xin, D. Lee, S. Ghose, M. Alser, H. Hassan, O. Ergin, C. Alkan, and O. Mutlu, “GRIM-Filter: Fast Seed Filtering in Read Mapping using Emerging Memory Technologies, ” inAPBC, 2017

2017
[57]

A Fast Bit-Vector Algorithm for Approximate String Matching Based on Dynamic Programming,

G. Myers, “A Fast Bit-Vector Algorithm for Approximate String Matching Based on Dynamic Programming, ”JACM, 1999

1999
[58]

Optical Image Encryption Based on XOR Operations,

J. Han, C.-S. Park, D.-H. Ryu, and E.-S. Kim, “Optical Image Encryption Based on XOR Operations, ”Optical Engineering, 1999

1999
[59]

XOR-based Visual Cryptog- raphy Schemes,

P. Tuyls, H. D. Hollmann, J. V. Lint, and L. Tolhuizen, “XOR-based Visual Cryptog- raphy Schemes, ”Des. Codes, Cryptogr., 2005

2005
[60]

Sparse Distributed Memory and Related Models,

P. Kanerva, “Sparse Distributed Memory and Related Models, ” Tech. Rep., 1992

1992
[61]

Hyperdimensional Computing: An Introduction to Computing in Distributed Representation with High-Dimensional Random Vectors,

——, “Hyperdimensional Computing: An Introduction to Computing in Distributed Representation with High-Dimensional Random Vectors, ”Cognitive Computation, 2009

2009
[62]

In-memory Hyperdimensional Computing,

G. Karunaratne, M. Le Gallo, G. Cherubini, L. Benini, A. Rahimi, and A. Sebastian, “In-memory Hyperdimensional Computing, ”Nature Electronics, 2020

2020
[63]

PAPI: Exploiting Dynamic Parallelism in Large Language Model Decoding with a Processing-In-Memory-Enabled Computing System,

Y. He, H. Mao, C. Giannoula, M. Sadrosadati, J. Gómez-Luna, H. Li, X. Li, Y. Wang, and O. Mutlu, “PAPI: Exploiting Dynamic Parallelism in Large Language Model Decoding with a Processing-In-Memory-Enabled Computing System, ”ASPLOS, 2025

2025
[64]

PIM Is All You Need: A CXL-Enabled GPU-Free System for Large Language Model Inference,

Y. Gu, A. Khadem, S. Umesh, N. Liang, X. Servot, O. Mutlu, R. Iyer, and R. Das, “PIM Is All You Need: A CXL-Enabled GPU-Free System for Large Language Model Inference, ”ASPLOS, 2025

2025
[65]

TransPIM: A Memory-Based Acceleration via Software-Hardware Co-Design for Transformer,

M. Zhou, W. Xu, J. Kang, and T. Rosing, “TransPIM: A Memory-Based Acceleration via Software-Hardware Co-Design for Transformer, ” inHPCA, 2022

2022
[66]

AttAcc! Unleashing the Power of PIM for Batched Transformer-based Generative Model Inference,

J. Park, J. Choi, K. Kyung, M. J. Kim, Y. Kwon, N. S. Kim, and J. H. Ahn, “AttAcc! Unleashing the Power of PIM for Batched Transformer-based Generative Model Inference, ” inASPLOS, 2024

2024
[67]

IANUS: Integrated Accelerator based on NPU-PIM Unified Memory System,

M. Seo, X. T. Nguyen, S. J. Hwang, Y. Kwon, G. Kim, C. Park, I. Kim, J. Park, J. Kim, W. Shinet al., “IANUS: Integrated Accelerator based on NPU-PIM Unified Memory System, ” inASPLOS, 2024

2024
[68]

Duplex: A Device for Large Language Models with Mixture of Experts, Grouped Query Attention, and Continuous Batching,

S. Yun, K. Kyung, J. Cho, J. Choi, J. Kim, B. Kim, S. Lee, K. Sohn, and J. H. Ahn, “Duplex: A Device for Large Language Models with Mixture of Experts, Grouped Query Attention, and Continuous Batching, ” inMICRO, 2024

2024
[69]

Neupims: Npu-pim Heterogeneous Acceleration for Batched LLM Inferencing,

G. Heo, S. Lee, J. Cho, H. Choi, S. Lee, H. Ham, G. Kim, D. Mahajan, and J. Park, “Neupims: Npu-pim Heterogeneous Acceleration for Batched LLM Inferencing, ” in ASPLOS, 2024

2024
[70]

Language Models are Few-Shot Learners,

T. B. Brown, B. Mann, N. Ryder, M. Subbiah, J. Kaplan, P. Dhariwal, A. Nee- lakantan, P. Shyam, G. Sastry, A. Askell, S. Agarwal, A. Herbert-Voss, G. Krueger, T. Henighan, R. Child, A. Ramesh, D. M. Ziegler, J. Wu, C. Winter, C. Hesse, M. Chen, E. Sigler, M. Litwin, S. Gray, B...

2020
[71]

BERT: Pre-training of Deep Bidirectional Transformers for Language Understanding,

J. Devlin, M.-W. Chang, K. Lee, and K. Toutanova, “BERT: Pre-training of Deep Bidirectional Transformers for Language Understanding, ” inNAACL, 2019

2019
[72]

Generative Adversarial Networks,

I. Goodfellow, J. Pouget-Abadie, M. Mirza, B. Xu, D. Warde-Farley, S. Ozair, A. Courville, and Y. Bengio, “Generative Adversarial Networks, ”NIPS, 2014

2014
[73]

ComputeDRAM: In-Memory Compute Using Off-the-Shelf DRAMs,

F. Gao, G. Tziantzioulis, and D. Wentzlaff, “ComputeDRAM: In-Memory Compute Using Off-the-Shelf DRAMs, ” inMICRO, 2019

2019
[74]

FracDRAM: Fractional Values in Off-the-Shelf DRAM,

——, “FracDRAM: Fractional Values in Off-the-Shelf DRAM, ” inMICRO, 2022

2022
[75]

DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips,

A. Olgun, H. Hassan, A. G. Yağlıkçı, Y. C. Tuğrul, L. Orosa, H. Luo, M. Patel, O. Ergin, and O. Mutlu, “DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips, ”TCAD, 2023

2023
[76]

QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips,

A. Olgun, M. Patel, A. G. Yağlıkçı, H. Luo, J. S. Kim, N. Bostancı, N. Vijaykumar, O. Ergin, and O. Mutlu, “QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips, ” inISCA, 2021

2021
[77]

PiDRAM: A Holistic End-to-end FPGA-based Framework for Processing-in-DRAM,

A. Olgun, J. G. Luna, K. Kanellopoulos, B. Salami, H. Hassan, O. Ergin, and O. Mutlu, 16 “PiDRAM: A Holistic End-to-end FPGA-based Framework for Processing-in-DRAM, ” TACO, 2022

2022
[78]

Functionally-Complete Boolean Logic in Real DRAM Chips: Experimental Characterization and Analysis,

I. E. Yuksel, Y. C. Tugrul, A. Olgun, F. N. Bostanci, A. G. Yaglikci, G. F. de Oliveira, H. Luo, J. G. Luna, M. Sadrosadati, and O. Mutlu, “Functionally-Complete Boolean Logic in Real DRAM Chips: Experimental Characterization and Analysis, ” inHPCA, 2024

2024
[79]

Simultaneous Many- Row Activation in Off-the-Shelf DRAM Chips: Experimental Characterization and Analysis,

I. E. Yuksel, Y. C. Tugrul, F. N. Bostanci, G. F. de Oliveira, A. G. Yaglikci, A. Olgun, M. Soysal, H. Luo, J. G. Luna, M. Sadrosadati, and O. Mutlu, “Simultaneous Many- Row Activation in Off-the-Shelf DRAM Chips: Experimental Characterization and Analysis, ” inDSN, 2024

2024
[80]

MIMDRAM: An End-to-End Processing-Using-DRAM System for High- Throughput, Energy-Efficient and Programmer-Transparent Multiple-Instruction Multiple-Data Processing,

G. F. Oliveira, A. Olgun, A. G. G. Yaglikçi, N. Bostanci, J. Gómez-Luna, S. Ghose, and O. Mutlu, “MIMDRAM: An End-to-End Processing-Using-DRAM System for High- Throughput, Energy-Efficient and Programmer-Transparent Multiple-Instruction Multiple-Data Processing, ” HPCA, 2024

2024
[81]

Buddy-RAM: Improving the Performance and Efficiency of Bulk Bitwise Operations Using DRAM,

V. Seshadri, D. Lee, T. Mullins, H. Hassan, A. Boroumand, J. Kim, M. A. Kozuch, O. Mutlu, P. B. Gibbons, and T. C. Mowry, “Buddy-RAM: Improving the Performance and Efficiency of Bulk Bitwise Operations Using DRAM, ” arXiv, 2016

2016
[82]

The Processing Using Memory Paradigm: In-DRAM Bulk Copy, Initialization, Bitwise AND and OR,

V. Seshadri and O. Mutlu, “The Processing Using Memory Paradigm: In-DRAM Bulk Copy, Initialization, Bitwise AND and OR, ” arXiv:1610.09603, 2016

2016 arXiv
[83]

RowClone: Accelerating Data Movement and Initialization Using DRAM,

V. Seshadri, Y. Kim, C. Fallin, D. Lee, R. Ausavarungnirun, G. Pekhimenko, Y. Luo, O. Mutlu, P. B. Gibbons, M. A. Kozuch, and T. C. Mowry, “RowClone: Accelerating Data Movement and Initialization Using DRAM, ” arXiv, 2018

2018
[84]

MajorK: Majority Based Kmer Matching in Commodity DRAM,

Z. Jahshan and L. Yavits, “MajorK: Majority Based Kmer Matching in Commodity DRAM, ”CAL, 2024

2024
[85]

Exploiting Hardware Vulnera- bilities to Attack Embedded System Devices: A Survey of Potent Microarchitectural Attacks,

A. P. Fournaris, L. Pocero Fraile, and O. Koufopavlou, “Exploiting Hardware Vulnera- bilities to Attack Embedded System Devices: A Survey of Potent Microarchitectural Attacks, ”Electronics, 2017

2017
[86]

Attacking Deterministic Signature Schemes using Fault Attacks,

D. Poddebniak, J. Somorovsky, S. Schinzel, M. Lochter, and P. Rösler, “Attacking Deterministic Signature Schemes using Fault Attacks, ” inEuroS&P, 2018

2018
[87]

Throwhammer: Rowhammer Attacks Over the Network and Defenses,

A. Tatar, R. K. Konoth, E. Athanasopoulos, C. Giuffrida, H. Bos, and K. Razavi, “Throwhammer: Rowhammer Attacks Over the Network and Defenses, ” inUSENIX ATC, 2018

2018
[88]

OpenSSL Bellcore’s Protection Helps Fault Attack,

S. Carre, M. Desjardins, A. Facon, and S. Guilley, “OpenSSL Bellcore’s Protection Helps Fault Attack, ” inDSD, 2018

2018
[89]

Software-Only Reverse Engi- neering of Physical DRAM Mappings for Rowhammer Attacks,

A. Barenghi, L. Breveglieri, N. Izzo, and G. Pelosi, “Software-Only Reverse Engi- neering of Physical DRAM Mappings for Rowhammer Attacks, ” inIVSW, 2018

2018
[90]

Triggering Rowhammer Hardware Faults on ARM: A Revisit,

Z. Zhang, Z. Zhan, D. Balasubramanian, X. Koutsoukos, and G. Karsai, “Triggering Rowhammer Hardware Faults on ARM: A Revisit, ” inASHES, 2018

2018
[91]

Advanced Fault Attacks in Software: Exploiting the Rowhammer Bug,

S. Bhattacharya and D. Mukhopadhyay, “Advanced Fault Attacks in Software: Exploiting the Rowhammer Bug, ” inFault Tolerant Architectures for Cryptography and Hardware Security, 2018

2018
[92]

Exploiting the DRAM Rowhammer Bug to Gain Kernel Privileges,

M. Seaborn and T. Dullien, “Exploiting the DRAM Rowhammer Bug to Gain Kernel Privileges, ” http://googleprojectzero.blogspot.com.tr/2015/03/exploiting-dram-ro whammer-bug-to-gain.html, 2015

2015
[93]

Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors,

Y. Kim, R. Daly, J. Kim, C. Fallin, J. H. Lee, D. Lee, C. Wilkerson, K. Lai, and O. Mutlu, “Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors, ” inISCA, 2014

2014
[94]

RowHammer — GitHub Repository,

SAFARI Research Group, “RowHammer — GitHub Repository, ” https://github.com /CMU-SAFARI/rowhammer, 2014

2014
[95]

Exploiting the DRAM Rowhammer Bug to Gain Kernel Privileges,

M. Seaborn and T. Dullien, “Exploiting the DRAM Rowhammer Bug to Gain Kernel Privileges, ”Black Hat, 2015

2015
[96]

Drammer: Deterministic Rowhammer Attacks on Mobile Platforms,

V. van der Veen, Y. Fratantonio, M. Lindorfer, D. Gruss, C. Maurice, G. Vigna, H. Bos, K. Razavi, and C. Giuffrida, “Drammer: Deterministic Rowhammer Attacks on Mobile Platforms, ” inCCS, 2016

2016
[97]

Rowhammer.js: A Remote Software-Induced Fault Attack in Javascript,

D. Gruss, C. Maurice, and S. Mangard, “Rowhammer.js: A Remote Software-Induced Fault Attack in Javascript, ” inDIMV A, 2016

2016
[98]

Flip Feng Shui: Hammering a Needle in the Software Stack,

K. Razavi, B. Gras, E. Bosman, B. Preneel, C. Giuffrida, and H. Bos, “Flip Feng Shui: Hammering a Needle in the Software Stack, ” inUSENIX Security, 2016

2016
[99]

DRAMA: Exploiting DRAM Addressing for Cross-CPU Attacks,

P. Pessl, D. Gruss, C. Maurice, M. Schwarz, and S. Mangard, “DRAMA: Exploiting DRAM Addressing for Cross-CPU Attacks, ” inUSENIX Security, 2016

2016
[100]

One Bit Flips, One Cloud Flops: Cross-VM Row Hammer Attacks and Privilege Escalation,

Y. Xiao, X. Zhang, Y. Zhang, and R. Teodorescu, “One Bit Flips, One Cloud Flops: Cross-VM Row Hammer Attacks and Privilege Escalation, ” inUSENIX Security, 2016

2016
[101]

Dedup Est Machina: Memory Deduplication as An Advanced Exploitation Vector,

E. Bosman, K. Razavi, H. Bos, and C. Giuffrida, “Dedup Est Machina: Memory Deduplication as An Advanced Exploitation Vector, ” inS&P, 2016

2016
[102]

Curious Case of Rowhammer: Flipping Secret Exponent Bits Using Timing Analysis,

S. Bhattacharya and D. Mukhopadhyay, “Curious Case of Rowhammer: Flipping Secret Exponent Bits Using Timing Analysis, ” inCHES, 2016

2016
[103]

Invited: Who is the Major Threat to Tomorrow’s Security? You, the Hardware Designer,

W. Burleson, O. Mutlu, and M. Tiwari, “Invited: Who is the Major Threat to Tomorrow’s Security? You, the Hardware Designer, ” inDAC, 2016

2016
[104]

A New Approach for RowHammer Attacks,

R. Qiao and M. Seaborn, “A New Approach for RowHammer Attacks, ” inHOST, 2016

2016
[105]

Can’t Touch This: Software-Only Mitigation Against Rowhammer Attacks Targeting Kernel Memory,

F. Brasser, L. Davi, D. Gens, C. Liebchen, and A.-R. Sadeghi, “Can’t Touch This: Software-Only Mitigation Against Rowhammer Attacks Targeting Kernel Memory, ” inUSENIX Security, 2017

2017
[106]

SGX-Bomb: Locking Down the Processor via Rowhammer Attack,

Y. Jang, J. Lee, S. Lee, and T. Kim, “SGX-Bomb: Locking Down the Processor via Rowhammer Attack, ” inSOSP, 2017

2017
[107]

When Good Protections Go Bad: Exploiting Anti-DoS Measures to Accelerate Rowhammer Attacks,

M. T. Aga, Z. B. Aweke, and T. Austin, “When Good Protections Go Bad: Exploiting Anti-DoS Measures to Accelerate Rowhammer Attacks, ” inHOST, 2017

2017
[108]

The RowHammer Problem and Other Issues We May Face as Memory Becomes Denser,

O. Mutlu, “The RowHammer Problem and Other Issues We May Face as Memory Becomes Denser, ” inDATE, 2017

2017
[109]

Defeating Software Mitigations Against Rowhammer: A Surgical Precision Hammer,

A. Tatar, C. Giuffrida, H. Bos, and K. Razavi, “Defeating Software Mitigations Against Rowhammer: A Surgical Precision Hammer, ” inRAID, 2018

2018
[110]

Another Flip in the Wall of Rowhammer Defenses,

D. Gruss, M. Lipp, M. Schwarz, D. Genkin, J. Juffinger, S. O’Connell, W. Schoechl, and Y. Yarom, “Another Flip in the Wall of Rowhammer Defenses, ” inS&P, 2018

2018
[111]

Nethammer: Inducing Rowhammer Faults Through Network Requests,

M. Lipp, M. T. Aga, M. Schwarz, D. Gruss, C. Maurice, L. Raab, and L. Lam- ster, “Nethammer: Inducing Rowhammer Faults Through Network Requests, ” arXiv:1805.04956 [cs.CR], 2018

2018 arXiv
[112]

GuardION: Practical Mitigation of DMA-Based Rowhammer Attacks on ARM,

V. van der Veen, M. Lindorfer, Y. Fratantonio, H. P. Pillai, G. Vigna, C. Kruegel, H. Bos, and K. Razavi, “GuardION: Practical Mitigation of DMA-Based Rowhammer Attacks on ARM, ” inDIMV A, 2018

2018
[113]

Grand Pwning Unit: Accelerating Microarchitectural Attacks with the GPU,

P. Frigo, C. Giuffrida, H. Bos, and K. Razavi, “Grand Pwning Unit: Accelerating Microarchitectural Attacks with the GPU, ” inS&P, 2018

2018
[114]

Exploiting Correcting Codes: On the Effectiveness of ECC Memory Against Rowhammer Attacks,

L. Cojocar, K. Razavi, C. Giuffrida, and H. Bos, “Exploiting Correcting Codes: On the Effectiveness of ECC Memory Against Rowhammer Attacks, ” inS&P, 2019

2019
[115]

Pinpoint Rowhammer: Suppressing Unwanted Bit Flips on Rowhammer Attacks,

S. Ji, Y. Ko, S. Oh, and J. Kim, “Pinpoint Rowhammer: Suppressing Unwanted Bit Flips on Rowhammer Attacks, ” inASIACCS, 2019

2019
[116]

RowHammer: A Retrospective,

O. Mutlu and J. S. Kim, “RowHammer: A Retrospective, ”TCAD, 2019

2019
[117]

Terminal Brain Damage: Exposing the Graceless Degradation in Deep Neural Networks Under Hardware Fault Attacks,

S. Hong, P. Frigo, Y. Kaya, C. Giuffrida, and T. Dumitraş, “Terminal Brain Damage: Exposing the Graceless Degradation in Deep Neural Networks Under Hardware Fault Attacks, ” inUSENIX Security, 2019

2019
[118]

RAMBleed: Reading Bits in Memory Without Accessing Them,

A. Kwong, D. Genkin, D. Gruss, and Y. Yarom, “RAMBleed: Reading Bits in Memory Without Accessing Them, ” inS&P, 2020

2020
[119]

TRRespass: Exploiting the Many Sides of Target Row Refresh,

P. Frigo, E. Vannacci, H. Hassan, V. van der Veen, O. Mutlu, C. Giuffrida, H. Bos, and K. Razavi, “TRRespass: Exploiting the Many Sides of Target Row Refresh, ” in S&P, 2020

2020
[120]

Are We Susceptible to Rowhammer? An End-to-End Methodology for Cloud Providers,

L. Cojocar, J. Kim, M. Patel, L. Tsai, S. Saroiu, A. Wolman, and O. Mutlu, “Are We Susceptible to Rowhammer? An End-to-End Methodology for Cloud Providers, ” in S&P, 2020

2020
[121]

JackHammer: Efficient Rowhammer on Heterogeneous FPGA–CPU Platforms,

Z. Weissman, T. Tiemann, D. Moghimi, E. Custodio, T. Eisenbarth, and B. Sunar, “JackHammer: Efficient Rowhammer on Heterogeneous FPGA–CPU Platforms, ” arXiv:1912.11523 [cs.CR], 2020

1912 arXiv
[122]

PThammer: Cross- User-Kernel-Boundary Rowhammer through Implicit Accesses,

Z. Zhang, Y. Cheng, D. Liu, S. Nepal, Z. Wang, and Y. Yarom, “PThammer: Cross- User-Kernel-Boundary Rowhammer through Implicit Accesses, ” inMICRO, 2020

2020
[123]

Deephammer: Depleting the Intelligence of Deep Neural Networks Through Targeted Chain of Bit Flips,

F. Yao, A. S. Rakin, and D. Fan, “Deephammer: Depleting the Intelligence of Deep Neural Networks Through Targeted Chain of Bit Flips, ” inUSENIX Security, 2020

2020
[124]

SMASH: Syn- chronized Many-Sided Rowhammer Attacks from JavaScript,

F. de Ridder, P. Frigo, E. Vannacci, H. Bos, C. Giuffrida, and K. Razavi, “SMASH: Syn- chronized Many-Sided Rowhammer Attacks from JavaScript, ” inUSENIX Security, 2021

2021
[125]

Uncovering in-DRAM RowHammer Protection Mechanisms: A New Methodology, Custom RowHammer Patterns, and Implications,

H. Hassan, Y. C. Tugrul, J. S. Kim, V. v. d. Veen, K. Razavi, and O. Mutlu, “Uncovering in-DRAM RowHammer Protection Mechanisms: A New Methodology, Custom RowHammer Patterns, and Implications, ” inMICRO, 2021

2021
[126]

Blacksmith: Scalable Rowhammering in the Frequency Domain,

P. Jattke, V. van der Veen, P. Frigo, S. Gunter, and K. Razavi, “Blacksmith: Scalable Rowhammering in the Frequency Domain, ” inS&P, 2022

2022
[127]

Toward Realistic Backdoor Injection Attacks on DNNs using RowHammer,

M. C. Tol, S. Islam, B. Sunar, and Z. Zhang, “Toward Realistic Backdoor Injection Attacks on DNNs using RowHammer, ” arXiv:2110.07683, 2022

2022 arXiv
[128]

Half-Double: Hammering From the Next Row Over,

A. Kogler, J. Juffinger, S. Qazi, Y. Kim, M. Lipp, N. Boichat, E. Shiu, M. Nissler, and D. Gruss, “Half-Double: Hammering From the Next Row Over, ” inUSENIX Security, 2022

2022
[129]

SpyHammer: Using RowHammer to Remotely Spy on Temperature,

L. Orosa, U. Rührmair, A. G. Yaglikci, H. Luo, A. Olgun, P. Jattke, M. Patel, J. Kim, K. Razavi, and O. Mutlu, “SpyHammer: Using RowHammer to Remotely Spy on Temperature, ”IEEE Access, 2022

2022
[130]

Implicit Hammer: Cross-Privilege-Boundary Rowhammer through Implicit Accesses,

Z. Zhang, W. He, Y. Cheng, W. Wang, Y. Gao, D. Liu, K. Li, S. Nepal, A. Fu, and Y. Zou, “Implicit Hammer: Cross-Privilege-Boundary Rowhammer through Implicit Accesses, ”IEEE TDSC, 2022

2022
[131]

Generating Robust DNN with Resistance to Bit-Flip based Adversarial Weight Attack,

L. Liu, Y. Guo, Y. Cheng, Y. Zhang, and J. Yang, “Generating Robust DNN with Resistance to Bit-Flip based Adversarial Weight Attack, ”IEEE TC, 2022

2022
[132]

HammerScope: Observing DRAM Power Consumption Using Rowham- mer,

Y. Cohen, K. S. Tharayil, A. Haenel, D. Genkin, A. D. Keromytis, Y. Oren, and Y. Yarom, “HammerScope: Observing DRAM Power Consumption Using Rowham- mer, ” inCCS, 2022

2022
[133]

TrojViT: Trojan Insertion in Vision Transformers,

M. Zheng, Q. Lou, and L. Jiang, “TrojViT: Trojan Insertion in Vision Transformers, ” arXiv:2208.13049, 2022

2022 arXiv
[134]

When Frodo Flips: End-to-End Key Recovery on FrodoKEM via Rowhammer,

M. Fahr Jr, H. Kippen, A. Kwong, T. Dang, J. Lichtinger, D. Dachman-Soled, D. Genkin, A. Nelson, R. Perlner, A. Yerukhimovichet al., “When Frodo Flips: End-to-End Key Recovery on FrodoKEM via Rowhammer, ”CCS, 2022

2022
[135]

SpecHammer: Combining Spectre and Rowhammer for New Speculative Attacks,

Y. Tobah, A. Kwong, I. Kang, D. Genkin, and K. G. Shin, “SpecHammer: Combining Spectre and Rowhammer for New Speculative Attacks, ” inS&P, 2022

2022
[136]

DeepSteal: Advanced Model Extractions Leveraging Efficient Weight Stealing in Memories,

A. S. Rakin, M. H. I. Chowdhuryy, F. Yao, and D. Fan, “DeepSteal: Advanced Model Extractions Leveraging Efficient Weight Stealing in Memories, ” inS&P, 2022

2022
[137]

Statistical Distributions of Row-Hammering Induced Failures in DDR3 Components,

K. Park, D. Yun, and S. Baeg, “Statistical Distributions of Row-Hammering Induced Failures in DDR3 Components, ”Microelectronics Reliability, 2016

2016
[138]

Experiments and Root Cause Analysis for Active-Precharge Hammering Fault in DDR3 SDRAM under 3xnm Technology,

K. Park, C. Lim, D. Yun, and S. Baeg, “Experiments and Root Cause Analysis for Active-Precharge Hammering Fault in DDR3 SDRAM under 3xnm Technology, ” Microelectronics Reliability, 2016

2016
[139]

Active Precharge Hammering to Monitor Displace- ment Damage Using High-Energy Protons in 3x-nm SDRAM,

C. Lim, K. Park, and S. Baeg, “Active Precharge Hammering to Monitor Displace- ment Damage Using High-Energy Protons in 3x-nm SDRAM, ”TNS, 2017

2017
[140]

Overcoming the Reliability Limitation in the Ultimately Scaled DRAM using Silicon Migration Technique by Hydrogen Annealing,

S.-W. Ryu, K. Min, J. Shin, H. Kwon, D. Nam, T. Oh, T.-S. Jang, M. Yoo, Y. Kim, and S. Hong, “Overcoming the Reliability Limitation in the Ultimately Scaled DRAM using Silicon Migration Technique by Hydrogen Annealing, ” inIEDM, 2017

2017
[141]

Study of TID Effects on One Row Hammering using Gamma in DDR4 SDRAMs,

D. Yun, M. Park, C. Lim, and S. Baeg, “Study of TID Effects on One Row Hammering using Gamma in DDR4 SDRAMs, ” inIRPS, 2018

2018
[142]

Trap-Assisted DRAM Row Hammer Effect,

T. Yang and X.-W. Lin, “Trap-Assisted DRAM Row Hammer Effect, ”EDL, 2019

2019
[143]

On DRAM RowHammer and the Physics on Insecurity,

A. J. Walker, S. Lee, and D. Beery, “On DRAM RowHammer and the Physics on Insecurity, ”IEEE TED, 2021

2021
[144]

Revis- iting RowHammer: An Experimental Analysis of Modern Devices and Mitigation Techniques,

J. S. Kim, M. Patel, A. G. Yağlıkçı, H. Hassan, R. Azizi, L. Orosa, and O. Mutlu, “Revis- iting RowHammer: An Experimental Analysis of Modern Devices and Mitigation Techniques, ” inISCA, 2020

2020
[145]

A Deeper Look into RowHammer’s Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses,

L. Orosa, A. G. Yağlıkçı, H. Luo, A. Olgun, J. Park, H. Hassan, M. Patel, J. S. Kim, and 17 O. Mutlu, “A Deeper Look into RowHammer’s Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses, ” inMICRO, 2021

2021
[146]

Understanding RowHammer Under Reduced Wordline Voltage: An Experimental Study Using Real DRAM Devices,

A. G. Yağlıkcı, H. Luo, G. F. De Oliviera, A. Olgun, M. Patel, J. Park, H. Hassan, J. S. Kim, L. Orosa, and O. Mutlu, “Understanding RowHammer Under Reduced Wordline Voltage: An Experimental Study Using Real DRAM Devices, ” inDSN, 2022

2022
[147]

Analysis of Row Hammer Attack on STTRAM,

M. N. I. Khan and S. Ghosh, “Analysis of Row Hammer Attack on STTRAM, ” in ICCD, 2018

2018
[148]

Rowhammer for Spin Torque based Memory: Problem or not?

S. Agarwal, H. Dixit, D. Datta, M. Tran, D. Houssameddine, D. Shum, and F. Benistant, “Rowhammer for Spin Torque based Memory: Problem or not?” in INTERMAG, 2018

2018
[149]

Write Disturb Analyses on Half-Selected Cells of Cross-Point RRAM Arrays,

H. Li, H.-Y. Chen, Z. Chen, B. Chen, R. Liu, G. Qiu, P. Huang, F. Zhang, Z. Jiang, B. Gao, L. Liu, X. Liu, S. Yu, H.-S. P. Wong, and J. Kang, “Write Disturb Analyses on Half-Selected Cells of Cross-Point RRAM Arrays, ” inIRPS, 2014

2014
[150]

Write Disturb in Ferroelectric FETs and Its Implication for 1T-FeFET AND Memory Arrays,

K. Ni, X. Li, J. A. Smith, M. Jerry, and S. Datta, “Write Disturb in Ferroelectric FETs and Its Implication for 1T-FeFET AND Memory Arrays, ”IEEE EDL, 2018

2018
[151]

On the Reliability of FeFET On-Chip Memory,

P. R. Genssler, V. M. van Santen, J. Henkel, and H. Amrouch, “On the Reliability of FeFET On-Chip Memory, ”TC, 2022

2022
[152]

Fundamentally Understanding and Solving RowHammer,

O. Mutlu, A. Olgun, and A. G. Yaglikci, “Fundamentally Understanding and Solving RowHammer, ” inASP-DAC, 2023

2023
[153]

RowPress: Amplifying Read Disturbance in Modern DRAM Chips,

H. Luo, A. Olgun, A. G. Yağlıkçı, Y. C. Tuğrul, S. Rhyner, M. B. Cavlak, J. Lindegger, M. Sadrosadati, and O. Mutlu, “RowPress: Amplifying Read Disturbance in Modern DRAM Chips, ” inISCA, 2023

2023
[154]

An Experimental Characterization of Combined RowHammer and RowPress Read Disturbance in Modern DRAM Chips,

H. Luo, I. E. Yüksel, A. Olgun, A. G. Yağlıkçı, M. Sadrosadati, and O. Mutlu, “An Experimental Characterization of Combined RowHammer and RowPress Read Disturbance in Modern DRAM Chips, ” inDSN Disrupt, 2024

2024
[155]

Simple Operations in Memory to Reduce Data Movement,

V. Seshadri and O. Mutlu, “Simple Operations in Memory to Reduce Data Movement, ” inAdv. Comput., 2017

2017
[156]

DDR4 SDRAM Datasheet,

Micron, “DDR4 SDRAM Datasheet, ” inMicron, 2016, p. 380

2016
[157]

SoftTRR: Protect Page Tables against Rowhammer Attacks using Software-only Target Row Refresh,

Z. Zhang, Y. Cheng, M. Wang, W. He, W. Wang, S. Nepal, Y. Gao, K. Li, Z. Wang, and C. Wu, “SoftTRR: Protect Page Tables against Rowhammer Attacks using Software-only Target Row Refresh, ” inUSENIX ATC, 2022

2022
[158]

ProTRR: Principled yet Optimal In-DRAM Target Row Refresh,

M. Marazzi, P. Jattke, F. Solt, and K. Razavi, “ProTRR: Principled yet Optimal In-DRAM Target Row Refresh, ” inS&P, 2022

2022
[159]

DDR5 Spec Update Has All It Needs to End Rowhammer: Will It?

S. Saroiu, “DDR5 Spec Update Has All It Needs to End Rowhammer: Will It?” https://stefan.t8k2.com/rh/PRAC/index.html
[160]

Chronus: Understanding and Securing the Cutting-Edge Industry Solutions to DRAM Read Disturbance,

O. Canpolat, A. G. Yağlıkçı, G. F. Oliveira, A. Olgun, N. Bostancı, I. E. Yuksel, H. Luo, O. Ergin, and O. Mutlu, “Chronus: Understanding and Securing the Cutting-Edge Industry Solutions to DRAM Read Disturbance, ” inHPCA, 2025

2025
[161]

Understanding the Security Benefits and Overheads of Emerging Industry Solutions to DRAM Read Disturbance,

O. Canpolat, A. G. Yağlıkçı, G. F. Oliveira, A. Olgun, O. Ergin, and O. Mutlu, “Understanding the Security Benefits and Overheads of Emerging Industry Solutions to DRAM Read Disturbance, ”DRAMSec, 2024

2024
[162]

W. Kim, C. Jung, S. Yoo, D. Hong, J. Hwang, J. Yoon, O. Jung, J. Choi, S. Hyun, M. Kanget al., “A 1.1 V 16Gb DDR5 DRAM with Probabilistic-Aggressor Track- ing, Refresh-Management Functionality, Per-Row Hammer Tracking, a Multi-Step Precharge, and Core-Bias Modulation for Secur...

2023
[163]

JEDEC,JESD79-5c: DDR5 SDRAM Standard, 2024

2024
[164]

——,JESD209-5A: LPDDR5 SDRAM Standard, 2020

2020
[165]

——,JESD209-4B: Low Power Double Data Rate 4 (LPDDR4) Standard, 2017

2017
[166]

——,JESD79F: Double Data Rate (DDR) SDRAM Standard, 2008

2008
[167]

JEDEC,JESD79-4C: DDR4 SDRAM Standard, 2020

2020
[168]

DDR3 SDRAM Standard,

J. S. S. T. Associationet al., “DDR3 SDRAM Standard, ”JEDEC Standard, no. 79-3F, p. 226, 2012

2012
[169]

JEDEC,JESD79-5C: DDR5 SDRAM Standard, 2024

2024
[170]

——,JESD235D: High Bandwidth Memory DRAM (HBM1, HBM2), 2021

2021
[171]

Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture,

D. Lee, Y. Kim, V. Seshadri, J. Liu, L. Subramanian, and O. Mutlu, “Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture, ” inHPCA, 2013

2013
[172]

Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common-Case,

D. Lee, Y. Kim, G. Pekhimenko, S. Khan, V. Seshadri, K. Chang, and O. Mutlu, “Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common-Case, ” in HPCA, 2015

2015
[173]

Parallelism-Aware Batch Scheduling: Enhancing Both Performance and Fairness of Shared DRAM Systems,

O. Mutlu and T. Moscibroda, “Parallelism-Aware Batch Scheduling: Enhancing Both Performance and Fairness of Shared DRAM Systems, ” inISCA, 2008

2008
[174]

ATLAS: A Scalable and High- Performance Scheduling Algorithm for Multiple Memory Controllers,

Y. Kim, D. Han, O. Mutlu, and M. Harchol-Balter, “ATLAS: A Scalable and High- Performance Scheduling Algorithm for Multiple Memory Controllers, ” inHPCA, 2010

2010
[175]

RAIDR: Retention-Aware Intelligent DRAM Refresh,

J. Liu, B. Jaiyen, R. Veras, and O. Mutlu, “RAIDR: Retention-Aware Intelligent DRAM Refresh, ” inISCA, 2012

2012
[176]

AVATAR: A Variable- Retention-Time (VRT) Aware Refresh for DRAM Systems,

M. Qureshi, D.-H. Kim, S. Khan, P. Nair, and O. Mutlu, “AVATAR: A Variable- Retention-Time (VRT) Aware Refresh for DRAM Systems, ” inDSN, 2015

2015
[177]

An Experimental Study of Data Retention Behavior in Modern DRAM Devices,

J. Liu, B. Jaiyen, Y. Kim, C. Wilkerson, O. Mutlu, J. Liu, B. Jaiyen, Y. Kim, C. Wilker- son, and O. Mutlu, “An Experimental Study of Data Retention Behavior in Modern DRAM Devices, ” inISCA, 2013

2013
[178]

SDRAM, 4Gb: x4, x8, x16 DDR4 SDRAM Features,

Micron Technology, “SDRAM, 4Gb: x4, x8, x16 DDR4 SDRAM Features, ” 2014

2014
[179]

Retrospective: Flipping Bits in Memory without Accessing Them: An Experimental Study of DRAM Disturbance Errors,

O. Mutlu, “Retrospective: Flipping Bits in Memory without Accessing Them: An Experimental Study of DRAM Disturbance Errors, ”arXiv, 2023

2023
[180]

Low-Cost Inter-Linked Subarrays (LISA): Enabling Fast Inter-Subarray Data Movement in DRAM,

K. K. Chang, P. J. Nair, D. Lee, S. Ghose, M. K. Qureshi, and O. Mutlu, “Low-Cost Inter-Linked Subarrays (LISA): Enabling Fast Inter-Subarray Data Movement in DRAM, ” inHPCA, 2016

2016
[181]

ELP2IM: Efficient and Low Power Bitwise Operation Processing in DRAM,

X. Xin, Y. Zhang, and J. Yang, “ELP2IM: Efficient and Low Power Bitwise Operation Processing in DRAM, ” inHPCA, 2020

2020
[182]

DRISA: A DRAM- Based Reconfigurable In-Situ Accelerator,

S. Li, D. Niu, K. T. Malladi, H. Zheng, B. Brennan, and Y. Xie, “DRISA: A DRAM- Based Reconfigurable In-Situ Accelerator, ” inMICRO, 2017

2017
[183]

DrAcc: A DRAM Based Accelerator for Accurate CNN Inference,

Q. Deng, L. Jiang, Y. Zhang, M. Zhang, and J. Yang, “DrAcc: A DRAM Based Accelerator for Accurate CNN Inference, ” inDAC, 2018

2018
[184]

GraphiDe: A Graph Processing Accelerator Leveraging In-DRAM-Computing,

S. Angizi and D. Fan, “GraphiDe: A Graph Processing Accelerator Leveraging In-DRAM-Computing, ” inGLSVLSI, 2019

2019
[186]

pLUTo: In-DRAM Lookup Tables to Enable Massively Parallel General-Purpose Computation,

J. D. Ferreira, G. Falcao, J. Gómez-Luna, M. Alser, L. Orosa, M. Sadrosadati, J. S. Kim, G. F. Oliveira, T. Shahroodi, A. Nori, and O. Mutlu, “pLUTo: In-DRAM Lookup Tables to Enable Massively Parallel General-Purpose Computation, ” inMICRO, 2022

2022
[187]

LAcc: Exploiting Lookup Table-Based Fast and Accurate Vector Multiplication in DRAM-Based CNN Accelerator,

Q. Deng, Y. Zhang, M. Zhang, and J. Yang, “LAcc: Exploiting Lookup Table-Based Fast and Accurate Vector Multiplication in DRAM-Based CNN Accelerator, ” in DAC, 2019

2019
[188]

Look-Up-Table Based Processing-in-Memory Ar- chitecture with Programmable Precision-Scaling for Deep Learning Applications,

P. R. Sutradhar, S. Bavikadi, M. Connolly, S. Prajapati, M. A. Indovina, S. M. P. Dinakarrao, and A. Ganguly, “Look-Up-Table Based Processing-in-Memory Ar- chitecture with Programmable Precision-Scaling for Deep Learning Applications, ” TPDS, 2021

2021
[189]

pPIM: A Programmable Processor-in-Memory Architecture with Precision-Scaling For Deep Learning,

P. R. Sutradhar, M. Connolly, S. Bavikadi, S. M. P. Dinakarrao, M. A. Indovina, and A. Ganguly, “pPIM: A Programmable Processor-in-Memory Architecture with Precision-Scaling For Deep Learning, ” inCAL, 2020

2020
[190]

SCOPE: A Stochastic Computing Engine for DRAM-Based In-Situ Accelerator,

S. Li, A. O. Glova, X. Hu, P. Gu, D. Niu, K. T. Malladi, H. Zheng, B. Brennan, and Y. Xie, “SCOPE: A Stochastic Computing Engine for DRAM-Based In-Situ Accelerator, ” inMICRO, 2018

2018
[191]

D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput,

J. S. Kim, M. Patel, H. Hassan, L. Orosa, and O. Mutlu, “D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput, ” inHPCA, 2019

2019
[192]

The DRAM Latency PUF: Quickly Evaluating Physical Unclonable Functions by Exploiting the Latency–Reliability Tradeoff in Modern Commodity DRAM Devices,

J. S. Kim, M. Patel, H. Hassan, and O. Mutlu, “The DRAM Latency PUF: Quickly Evaluating Physical Unclonable Functions by Exploiting the Latency–Reliability Tradeoff in Modern Commodity DRAM Devices, ” inHPCA, 2018

2018
[193]

Accelerating Neural Network Inference with Processing-in-DRAM: From the Edge to the Cloud,

G. F. Oliveira, J. Gómez-Luna, S. Ghose, A. Boroumand, and O. Mutlu, “Accelerating Neural Network Inference with Processing-in-DRAM: From the Edge to the Cloud, ” IEEE Micro, 2022

2022
[194]

Proteus: Achieving High-Performance Processing-Using-DRAM via Dynamic Precision Bit-Serial Arithmetic,

G. F. Oliveira, M. Kabra, Y. Guo, K. Chen, A. G. Yağlıkçı, M. Soysal, M. Sadrosadati, J. O. Bueno, S. Ghose, J. Gómez-Lunaet al., “Proteus: Achieving High-Performance Processing-Using-DRAM via Dynamic Precision Bit-Serial Arithmetic, ”ICS, 2025

2025
[195]

HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the- Shelf DRAM Chips,

A. G. Yağlikci, A. Olgun, M. Patel, H. Luo, H. Hassan, L. Orosa, O. Ergin, and O. Mutlu, “HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the- Shelf DRAM Chips, ” inMICRO, 2022

2022
[196]

DRAM Bender — GitHub Repository,

SAFARI Research Group, “DRAM Bender — GitHub Repository, ” https://github.c om/CMU-SAFARI/DRAM-Bender, 2022

2022
[197]

SoftMC: A Flexible and Practical Open-Source Infrastruc- ture for Enabling Experimental DRAM Studies,

H. Hassan, N. Vijaykumar, S. Khan, S. Ghose, K. Chang, G. Pekhimenko, D. Lee, O. Ergin, and O. Mutlu, “SoftMC: A Flexible and Practical Open-Source Infrastruc- ture for Enabling Experimental DRAM Studies, ” inHPCA, 2017

2017
[198]

SoftMC — GitHub Repository,

SAFARI Research Group, “SoftMC — GitHub Repository, ” https://github.com/CMU -SAFARI/softmc, 2017

2017
[199]

Xilinx Alveo U200 FPGA Board,

Xilinx Inc., “Xilinx Alveo U200 FPGA Board, ” https://www.xilinx.com/products/bo ards-and-kits/alveo/u200.html
[200]

FT20X User Manual,

Maxwell, “FT20X User Manual, ” https://www.maxwell-fa.com/upload/files/base/8/ m/311.pdf
[201]

Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics,

M. Patel, J. Kim, T. Shahroodi, H. Hassan, and O. Mutlu, “Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics, ” inMICRO, 2020

2020
[202]

HARP: Practically and Effectively Identifying Uncorrectable Errors in Main Memory Chips That Use On-Die ECC,

M. Patel, G. F. de Oliveira Jr., and O. Mutlu, “HARP: Practically and Effectively Identifying Uncorrectable Errors in Main Memory Chips That Use On-Die ECC, ” in MICRO, 2021

2021
[203]

Laser Programmable Redundancy and Yield Improvement in a 64K DRAM,

R. T. Smith, J. D. Chlipala, J. F. Bindels, R. G. Nelson, F. H. Fischer, and T. F. Mantz, “Laser Programmable Redundancy and Yield Improvement in a 64K DRAM, ”JSSC, 1981

1981
[204]

Redundancy Techniques for High-Density DRAMs,

M. Horiguchi, “Redundancy Techniques for High-Density DRAMs, ” inISIS, 1997

1997
[205]

Keeth and R

B. Keeth and R. Baker,DRAM Circuit Design: A Tutorial. John Wiley & Sons, 2001

2001
[206]

Itoh,VLSI Memory Chip Design

K. Itoh,VLSI Memory Chip Design. Springer, 2001

2001
[207]

Gather-Scatter DRAM: In-DRAM Address Translation to Improve the Spatial Locality of Non-Unit Strided Accesses,

V. Seshadri, T. Mullins, A. Boroumand, O. Mutlu, P. B. Gibbons, M. A. Kozuch, and T. C. Mowry, “Gather-Scatter DRAM: In-DRAM Address Translation to Improve the Spatial Locality of Non-Unit Strided Accesses, ” inMICRO, 2015

2015
[208]

PARBOR: An Efficient System-Level Technique to Detect Data-Dependent Failures in DRAM,

S. Khan, D. Lee, and O. Mutlu, “PARBOR: An Efficient System-Level Technique to Detect Data-Dependent Failures in DRAM, ” inDSN, 2016

2016
[209]

Detecting and Mitigating Data-Dependent DRAM Failures by Exploiting Current Memory Content,

S. Khan, C. Wilkerson, Z. Wang, A. R. Alameldeen, D. Lee, and O. Mutlu, “Detecting and Mitigating Data-Dependent DRAM Failures by Exploiting Current Memory Content, ” inMICRO, 2017

2017
[210]

Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms,

D. Lee, S. Khan, L. Subramanian, S. Ghose, R. Ausavarungnirun, G. Pekhimenko, V. Seshadri, and O. Mutlu, “Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms, ” inSIG- METRICS, 2017

2017
[211]

Spatial Variation-Aware Read Disturbance Defenses: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions,

A. G. Yağlıkçı, G. F. Oliveira, Y. C. Tuğrul, I. E. Yuksel, A. Olgun, H. Luo, and O. Mutlu, “Spatial Variation-Aware Read Disturbance Defenses: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions, ” inHPCA, 2024

2024
[212]

Address and Data Scrambling: Causes and Impact on Memory Tests,

A. van de Goor and I. Schanstra, “Address and Data Scrambling: Causes and Impact on Memory Tests, ” inDELTA, 2002

2002
[213]

The Efficacy of Error Mitigation Techniques for DRAM Retention Failures: A Comparative Experimental Study,

S. Khan, D. Lee, Y. Kim, A. R. Alameldeen, C. Wilkerson, and O. Mutlu, “The Efficacy of Error Mitigation Techniques for DRAM Retention Failures: A Comparative Experimental Study, ” inSIGMETRICS, 2014

2014
[214]

Variable Read Disturbance: An Experimental Analysis of Temporal Variation in DRAM Read Disturbance,

A. Olgun, F. N. Bostanci, I. E. Yuksel, O. Canpolat, H. Luo, G. F. Oliveira, A. G. 18 Yaglikci, M. Patel, and O. Mutlu, “Variable Read Disturbance: An Experimental Analysis of Temporal Variation in DRAM Read Disturbance, ” inHPCA, 2025

2025
[215]

Understanding RowHammer Under Re- duced Refresh Latency: Experimental Analysis of Real DRAM Chips and Implica- tions on Future Solutions,

Y. C. Tugrul, A. G. Yaglikci, I. E. Yuksel, A. Olgun, O. Canpolat, N. Bostanci, M. Sadrosadati, O. Ergin, and O. Mutlu, “Understanding RowHammer Under Re- duced Refresh Latency: Experimental Analysis of Real DRAM Chips and Implica- tions on Future Solutions, ” inHPCA, 2025

2025
[216]

Read Disturbance in High Bandwidth Memory: A Detailed Experimental Study on HBM2 DRAM Chips,

A. Olgun, M. Osseiran, A. G. Yaglikci, Y. C. Tugrul, H. Luo, S. Rhyner, B. Salami, J. G. Luna, and O. Mutlu, “Read Disturbance in High Bandwidth Memory: A Detailed Experimental Study on HBM2 DRAM Chips, ” inDSN, 2024

2024
[217]

Double-sided Row Hammer Effect in Sub-20 nm DRAM: Physical Mechanism, Key Features and Mitigation,

L. Zhou, J. Li, Z. Qiao, P. Ren, Z. Sun, J. Wang, B. Wu, Z. Ji, R. Wang, K. Cao, and R. Huang, “Double-sided Row Hammer Effect in Sub-20 nm DRAM: Physical Mechanism, Key Features and Mitigation, ” inIRPS, 2023

2023
[218]

An Experimental Analysis of RowHammer in HBM2 DRAM Chips,

A. Olgun, M. Osseiran, A. G. Yaglikci, Y. C. Tugrul, H. Luo, S. Rhyner, B. Salami, J. Gomez Luna, and O. Mutlu, “An Experimental Analysis of RowHammer in HBM2 DRAM Chips, ” inDSN Disrupt, 2023

2023
[219]

Revisiting DRAM Read Disturbance: Identifying Inconsistencies Between Experimental Characterization and Device-Level Studies,

H. Luo, İ. E. Yüksel, A. Olgun, A. G. Yağlıkçı, and O. Mutlu, “Revisiting DRAM Read Disturbance: Identifying Inconsistencies Between Experimental Characterization and Device-Level Studies, ” inVTS, 2025

2025
[220]

Understanding the Competitive Interaction in Leakage Mechanisms for Effective Row Hammer Mitigation in Sub-20 nm DRAM,

J. Li, L. Zhou, S. Ye, Z. Qiao, and Z. Ji, “Understanding the Competitive Interaction in Leakage Mechanisms for Effective Row Hammer Mitigation in Sub-20 nm DRAM, ” IEEE Electron Device Letters, 2024

2024
[221]

Understanding the Physical Mechanism of RowPress at the Device-Level in Sub-20 nm DRAM,

L. Zhou, J. Li, P. Ren, S. Ye, D. Wang, Z. Qiao, and Z. Ji, “Understanding the Physical Mechanism of RowPress at the Device-Level in Sub-20 nm DRAM, ” inIRPS, 2024

2024
[222]

Unveiling RowPress in Sub-20 nm DRAM Through Comparative Analysis With Row Hammer: From Leakage Mechanisms to Key Features,

L. Zhou, S. Ye, R. Wang, and Z. Ji, “Unveiling RowPress in Sub-20 nm DRAM Through Comparative Analysis With Row Hammer: From Leakage Mechanisms to Key Features, ” inIEEE TED, 2024

2024
[223]

DDR4 SDRAM Unbuffered DIMM Based on 8Gb A-die HMA81GU7AFR8N-UH Module – Datasheet ,

S. Hynix, “DDR4 SDRAM Unbuffered DIMM Based on 8Gb A-die HMA81GU7AFR8N-UH Module – Datasheet , ” https://gzhls.at/blob/ldb/6/a/ 7/1/0c4ba46b0049c17756d92c180858965180a7.pdf, 2016

2016
[224]

“U-TRR, ” https://github.com/CMU-SAFARI/u-trr, 2021

2021
[225]

In-Memory Low-Cost Bit-Serial Addition Using Commodity DRAM Technology,

M. F. Ali, A. Jaiswal, and K. Roy, “In-Memory Low-Cost Bit-Serial Addition Using Commodity DRAM Technology, ” inTCAS I, 2019

2019
[226]

The Reach Profiler (REAPER): Enabling the Mitigation of DRAM Retention Failures via Profiling at Aggressive Conditions,

M. Patel, J. S. Kim, and O. Mutlu, “The Reach Profiler (REAPER): Enabling the Mitigation of DRAM Retention Failures via Profiling at Aggressive Conditions, ” ISCA, 2017

2017
[227]

ImPress: Securing DRAM Against Data- Disturbance Errors via Implicit Row-Press Mitigation,

M. Qureshi, A. Saxena, and A. Jaleel, “ImPress: Securing DRAM Against Data- Disturbance Errors via Implicit Row-Press Mitigation, ”MICRO, 2024

2024
[228]

JEDEC,JESD79-5: DDR5 SDRAM Standard, 2020

2020
[229]

BreakHammer: Enhancing RowHammer Mitigations by Carefully Throttling Suspect Threads,

O. Canpolat, A. G. Yağlıkçı, A. Olgun, İ. E. Yüksel, Y. C. Tuğrul, K. Kanellopoulos, O. Ergin, and O. Mutlu, “BreakHammer: Enhancing RowHammer Mitigations by Carefully Throttling Suspect Threads, ”MICRO, 2024

2024
[230]

Self-Managing DRAM: A Low-Cost Framework for Enabling Autonomous and Efficient DRAM Maintenance Operations,

H. Hassan, A. Olgun, A. G. Yağlıkçı, H. Luo, and O. Mutlu, “Self-Managing DRAM: A Low-Cost Framework for Enabling Autonomous and Efficient DRAM Maintenance Operations, ” inMICRO, 2024

2024
[231]

Panopticon: A Complete In- DRAM Rowhammer Mitigation,

T. Bennett, S. Saroiu, A. Wolman, and L. Cojocar, “Panopticon: A Complete In- DRAM Rowhammer Mitigation, ” inDRAMSec, 2021

2021
[232]

Ramulator V2.0,

S. R. Group, “Ramulator V2.0, ” https://github.com/CMU-SAFARI/ramulator2
[233]

Ramulator 2.0: A Modern, Modular, and Extensible DRAM Simulator,

H. Luo, Y. C. Tuğrul, F. N. Bostancı, A. Olgun, A. G. Yağlıkçı, , and O. Mutlu, “Ramulator 2.0: A Modern, Modular, and Extensible DRAM Simulator, ” 2023

2023
[234]

Ramulator — GitHub Repository,

SAFARI Research Group, “Ramulator — GitHub Repository, ” https://github.com/C MU-SAFARI/ramulator
[235]

Ramulator: A Fast and Extensible DRAM Simulator,

Y. Kim, W. Yang, and O. Mutlu, “Ramulator: A Fast and Extensible DRAM Simulator, ” CAL, 2016

2016
[236]

Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors,

O. Mutlu and T. Moscibroda, “Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors, ” inMICRO, 2007

2007
[237]

SPEC CPU 2006,

Standard Performance Evaluation Corp., “SPEC CPU 2006, ” http://www.spec.org/c pu2006/

2006
[238]

SPEC CPU2017 Benchmarks,

——, “SPEC CPU2017 Benchmarks, ” http://www.spec.org/cpu2017/
[239]

Transaction Processing Performance Council, TPC Benchmarks, http://www.tpc.org/information/benchmarks.asp
[240]

MediaBench II Video: Expediting the next Generation of Video Systems Research,

J. E. Fritts, F. W. Steiling, J. A. Tucek, and W. Wolf, “MediaBench II Video: Expediting the next Generation of Video Systems Research, ”Microprocess. Microsyst., 2009

2009
[241]

Benchmarking Cloud Serving Systems with YCSB,

B. Cooper, A. Silberstein, E. Tam, R. Ramakrishnan, and R. Sears, “Benchmarking Cloud Serving Systems with YCSB, ” inSoCC, 2010

2010
[242]

System-Level Performance Metrics for Multiprogram Workloads,

S. Eyerman and L. Eeckhout, “System-Level Performance Metrics for Multiprogram Workloads, ”IEEE Micro, 2008

2008
[243]

Symbiotic Jobscheduling for a Simultaneous Mut- lithreading Processor,

A. Snavely and D. M. Tullsen, “Symbiotic Jobscheduling for a Simultaneous Mut- lithreading Processor, ” inASPLOS, 2000

2000
[244]

Study of Proton Radiation Effect to Row Hammer Fault in DDR4 SDRAMs,

C. Lim, K. Park, G. Bak, D. Yun, M. Park, S. Baeg, S.-J. Wen, and R. Wong, “Study of Proton Radiation Effect to Row Hammer Fault in DDR4 SDRAMs, ”Microelectronics Reliability, 2018

2018
[245]

Blaster: Characterizing the blast radius of rowhammer,

Z. Lang, P. Jattke, M. Marazzi, and K. Razavi, “Blaster: Characterizing the blast radius of rowhammer, ” inDRAMSec, 2023

2023
[246]

Dramscope: Uncovering DRAM Microarchitecture and Characteristics by Issuing Memory Commands,

H. Nam, S. Baek, M. Wi, M. J. Kim, J. Park, C. Song, N. S. Kim, and J. H. Ahn, “Dramscope: Uncovering DRAM Microarchitecture and Characteristics by Issuing Memory Commands, ”ISCA, 2024

2024
[247]

WhistleBlower: A System-level Empirical Study on RowHammer,

W. He, Z. Zhang, Y. Cheng, W. Wang, W. Song, Y. Gao, Q. Zhang, K. Li, D. Liu, and S. Nepal, “WhistleBlower: A System-level Empirical Study on RowHammer, ”TC, 2023

2023
[248]

X-ray: Discovering DRAM Internal Structure and Error Characteristics by Issuing Memory Commands,

H. Nam, S. Baek, M. Wi, M. J. Kim, J. Park, C. Song, N. S. Kim, and J. H. Ahn, “X-ray: Discovering DRAM Internal Structure and Error Characteristics by Issuing Memory Commands, ”IEEE CAL, 2023

2023
[249]

Experimental Analysis of True Random Number Generation Using Simultaneous Multiple-Row Activation in Real DRAM Chips,

I. E. Yuksel, A. Olgun, F. N. Bostanci, O. Canpolat, G. F. Oliveira, M. Maakenkova, M. Sadrosadati, A. G. Yaglikci, and O. Mutlu, “Experimental Analysis of True Random Number Generation Using Simultaneous Multiple-Row Activation in Real DRAM Chips, ” arXiv, 2025

2025
[250]

TIMETEC PREMIUM DDR4 SODIMM Laptop Memory,

TimeTec, “TIMETEC PREMIUM DDR4 SODIMM Laptop Memory, ” https://timeteci nc.com/products/timetec-premium-ddr4-sodimm-laptop-memory
[251]

4Gb DDR4 SDRAM H5AN4G8NAFR-xxC H5AN4G8NAFR-xxI H5AN4G6NAFR-xxC H5AN4G6NAFR-xxI,

SK Hynix, “4Gb DDR4 SDRAM H5AN4G8NAFR-xxC H5AN4G8NAFR-xxI H5AN4G6NAFR-xxC H5AN4G6NAFR-xxI, ” https://www.datasheets360.com/pd f/63309412888179503804, 2017

2017
[252]

DDR4 SDRAM Unbuffered DIMM Based on 8Gb A-die,

——, “DDR4 SDRAM Unbuffered DIMM Based on 8Gb A-die, ” https://gzhls.at/blob/ ldb/6/a/7/1/0c4ba46b0049c17756d92c180858965180a7.pdf, 2016

2016
[253]

8Gb DDR4 SDRAM H5AN8G4NAFR-xxCH5AN8G8NAFR- xxCH5AN8G6NAFR-xxC,

——, “8Gb DDR4 SDRAM H5AN8G4NAFR-xxCH5AN8G8NAFR- xxCH5AN8G6NAFR-xxC, ” https://www.alldatasheet.com/datasheet-pdf/vie w/1424933/HYNIX/H5AN8G8NAFR-UHC.html, 2017

2017
[254]

KSM26ES8/16HC 16GB 1Rx8 2G x 72-Bit PC4-2666 CL19 288-Pin DIMM,

Kingston, “KSM26ES8/16HC 16GB 1Rx8 2G x 72-Bit PC4-2666 CL19 288-Pin DIMM, ” https://www.kingston.com/datasheets/KSM26ES8_16HC.pdf, 2021

2021
[255]

H5ANAG8NCJR-XNC,

SK Hynix, “H5ANAG8NCJR-XNC, ” 2021. [Online]. Available: https://www.digikey. com/en/products/detail/netlist-inc/H5ANAG8NCJR-XNC/20841590

2021
[256]

DDR4 SDRAM UDIMM Based on 8Gb D-die HMA851U6DJR6N HMA81GU6DJR8N HMA81GU7DJR8N HMA82GU6DJR8N HMA82GU7DJR8N,

——, “DDR4 SDRAM UDIMM Based on 8Gb D-die HMA851U6DJR6N HMA81GU6DJR8N HMA81GU7DJR8N HMA82GU6DJR8N HMA82GU7DJR8N, ” https://www.digchip.com/datasheets/parts/datasheet/2/202/HMA81GU7DJR8N-p df.php, 2020

2020
[257]

H5AN8G8NDJR-WMC,

——, “H5AN8G8NDJR-WMC, ” https://www.preduo.com/product/dram/ddr4/h5a n8g8ndjr-wmc
[258]

4GB 1Rx8 512M x 64-Bit PC4-2133 CL15 260-Pin SODIMM,

Kingston, “4GB 1Rx8 512M x 64-Bit PC4-2133 CL15 260-Pin SODIMM, ” https: //www.kingston.com/dataSheets/KVR21S15S8_4.pdf, 2015

2015
[259]

DDR4 SDRAM MT40A1G4 MT40A512M8 MT40A256M16,

Micron, “DDR4 SDRAM MT40A1G4 MT40A512M8 MT40A256M16, ” https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/2583/MT40A 1G4%2C%20512M8%2C%20256M16.pdf, 2015

2015
[260]

DDR4 SDRAM SODIMM Addendum,

——, “DDR4 SDRAM SODIMM Addendum, ” https://media-www.micron.com/-/m edia/client/global/documents/products/data-sheet/modules/sodimm/ddr4/atf4c 1gx64hz.pdf, 2019

2019
[261]

MT40A1G16KD-062E:E,

——, “MT40A1G16KD-062E:E, ” 2020. [Online]. Available: https://www.farnell.com/ datasheets/3151188.pdf

2020
[262]

MTA18ASF4G72HZ-3G2F1 Data Sheet,

——, “MTA18ASF4G72HZ-3G2F1 Data Sheet, ” https://www.micron.com/content/d am/micron/global/secure/products/data-sheet/modules/sodimm/ddr4/asf18c4g x72hz.pdf, 2015

2015
[263]

MT40A2G8SA-062E:F,

——, “MT40A2G8SA-062E:F, ” 2021. [Online]. Available: https://www.arrow.com/en /products/mt40a2g8sa-062e-itf/micron-technology

2021
[264]

KSM32ES8/8MR 8GB 1Rx8 1G x 72-Bit PC4-3200 CL22 288-Pin DIMM,

Kingston, “KSM32ES8/8MR 8GB 1Rx8 1G x 72-Bit PC4-3200 CL22 288-Pin DIMM, ” https://www.kingston.com/datasheets/KSM32ES8_8MR.pdf, 2021

2021
[265]

MT40A1G8SA-062E:R Data Sheet,

Micron, “MT40A1G8SA-062E:R Data Sheet, ” https://www.micron.com/content/dam /micron/global/secure/products/data-sheet/dram/ddr4/8gb-ddr4-sdram.pdf, 2015

2015
[266]

Unbuffered DIMM M378A2G43AB3-CWE,

Samsung, “Unbuffered DIMM M378A2G43AB3-CWE, ” https://semiconductor.sams ung.com/dram/module/udimm/m378a2g43ab3-cwe/
[267]

K4AAG085WA-BCWE

——, “K4AAG085WA-BCWE. ” [Online]. Available: https://semiconductor.samsung. com/dram/ddr/ddr4/k4aag085wa-bcwe/
[268]

Error correction code UDIMM / SODIMM M391A2G43BB2-CWE,

——, “Error correction code UDIMM / SODIMM M391A2G43BB2-CWE, ” https://semiconductor.samsung.com/dram/module/ecc-udimm-ecc-sodimm/m 391a2g43bb2-cwe/
[269]

Small outline DIMM M471A5244CB0-CRC,

——, “Small outline DIMM M471A5244CB0-CRC, ” https://semiconductor.samsung. com/dram/module/sodimm/m471a5244cb0-crc/
[270]

Small outline DIMM M471A4G43CB1-CWE,

——, “Small outline DIMM M471A4G43CB1-CWE, ” https://semiconductor.samsung. com/dram/module/sodimm/m471a4g43cb1-cwe/
[271]

DDR4 SDRAM SODIMM Addendum,

Micron, “DDR4 SDRAM SODIMM Addendum, ” https://media-www.micron.com/- /media/client/global/documents/products/data-sheet/modules/sodimm/ddr4/at f4c1gx64hz.pdf, 2019

2019
[272]

MT40A1G16RC-062E:B,

——, “MT40A1G16RC-062E:B, ” 2020. [Online]. Available: https: //www.micron.com/products/memory/dram-components/ddr4-sdram/part -catalog/part-detail/mt40a1g16rc-062e-b

2020
[273]

KVR24N17S8/8 8GB 1Rx8 1G x 64-Bit PC4-2400 CL17 288-Pin DIMM,

Kingston, “KVR24N17S8/8 8GB 1Rx8 1G x 64-Bit PC4-2400 CL17 288-Pin DIMM, ” https://www.kingston.com/datasheets/KVR24N17S8_8.pdf, 2016. 19 A. Tested DRAM Modules Table 2 shows the characteristics of the DDR4 DRAM modules we test and analyze. We provide the module and chip ident...

2016

Pith tools

Reviewed August 7, 2026 · model on record in the stance chip above.

[1] [1]

Processing Data Where It Makes Sense: Enabling In-Memory Computation,

O. Mutlu, S. Ghose, J. Gómez-Luna, and R. Ausavarungnirun, “Processing Data Where It Makes Sense: Enabling In-Memory Computation, ” inMicroprocessors and Microsystems, 2019

2019

[2] [2]

A Modern Primer on Processing in Memory,

O. Mutlu, S. Ghose, J. Gómez-Luna, and R. Ausavarungnirun, “A Modern Primer on Processing in Memory, ” inEmerging Computing: From Devices to Systems — Looking Beyond Moore and Von Neumann. Springer, 2021. [Online]. Available: https://arxiv.org/abs/2012.03112

arXiv 2021

[3] [3]

Memory Scaling: A Systems Architecture Perspective,

O. Mutlu, “Memory Scaling: A Systems Architecture Perspective, ” inIMW, 2013

2013

[4] [4]

Research Problems and Opportunities in Memory Systems,

O. Mutlu and L. Subramanian, “Research Problems and Opportunities in Memory Systems, ”SUPERFRI, 2014

2014

[5] [5]

The Tail at Scale,

J. Dean and L. A. Barroso, “The Tail at Scale, ”CACM, 2013

2013

[6] [6]

Profiling a Warehouse-Scale Computer,

S. Kanev, J. P. Darago, K. Hazelwood, P. Ranganathan, T. Moseley, G.-Y. Wei, and D. Brooks, “Profiling a Warehouse-Scale Computer, ” inISCA, 2015

2015

[7] [7]

Clearing the Clouds: A Study of Emerging Scale-Out Workloads on Modern Hardware,

M. Ferdman, A. Adileh, O. Kocberber, S. Volos, M. Alisafaee, D. Jevdjic, C. Kaynak, A. D. Popescu, A. Ailamaki, and B. Falsafi, “Clearing the Clouds: A Study of Emerging Scale-Out Workloads on Modern Hardware, ” inASPLOS, 2012. 15

2012

[8] [8]

Bigdatabench: A Big Data Benchmark Suite from Internet Services,

L. Wang, J. Zhan, C. Luo, Y. Zhu, Q. Yang, Y. He, W. Gao, Z. Jia, Y. Shi, S. Zhanget al., “Bigdatabench: A Big Data Benchmark Suite from Internet Services, ” inHPCA, 2014

2014