A comparative study on power delivery aspects of compute-in/near-memory approaches using DRAM

Lizy Kurian John; Siddhartha Raman Sundara Raman; Siyuan Ma

arxiv: 2604.04773 · v2 · pith:QBGDB2A6new · submitted 2026-04-06 · 💻 cs.AR

A comparative study on power delivery aspects of compute-in/near-memory approaches using DRAM

Siddhartha Raman Sundara Raman , Siyuan Ma , Lizy Kurian John This is my paper

Pith reviewed 2026-05-10 18:53 UTC · model grok-4.3

classification 💻 cs.AR

keywords compute-in-memoryDRAM PIMpower delivery networkvoltage droopPDN challengesnear-bank computingmemory architecturemitigation strategies

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The pith

DRAM-based compute-in-memory creates non-traditional current demands that require power delivery network aware designs for reliable scaling.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper surveys power delivery challenges in DRAM-based compute-in-memory systems. It introduces a taxonomy that sorts current behaviors by whether they are bursty or sustained over time and localized or distributed across space. This framework shows how techniques such as multi-row activation, row-buffer operations, and near-bank compute units produce voltage droops, IR drops, and thermal hotspots. The survey then examines mitigation approaches that reuse existing DRAM mechanisms including timing constraints, controller scheduling, data placement, and hierarchical power management. A sympathetic reader cares because these issues determine whether PIM systems can scale without reliability failures in real hardware.

Core claim

By classifying PIM-induced current patterns along temporal (burst versus sustained) and spatial (localized versus distributed) dimensions, the paper shows that representative DRAM PIM mechanisms stress the power delivery network through concurrent activations and large-scale parallel execution, producing voltage droop, IR drop, and thermal hotspots. It argues that DRAM-specific mitigations drawn from architectural timing, memory controller scheduling, data placement, and bank- and vault-level power management can address these stresses, establishing that PDN-aware design is necessary for scalable and reliable DRAM-based PIM systems.

What carries the argument

A unified taxonomy that classifies PIM-induced current behavior along temporal (burst vs. sustained) and spatial (localized vs. distributed) dimensions to map techniques to their PDN stresses.

Load-bearing premise

The representative PIM techniques surveyed capture the main current-demand patterns that will appear in future DRAM-based PIM deployments.

What would settle it

A measurement or simulation of a large-scale DRAM PIM system using multi-row activation and near-bank compute that runs heavy parallel workloads without producing significant voltage droops, IR drops, or thermal hotspots.

Figures

Figures reproduced from arXiv: 2604.04773 by Lizy Kurian John, Siddhartha Raman Sundara Raman, Siyuan Ma.

read the original abstract

Compute-in-memory (PIM) mitigates the memory wall by performing computation within memory, reducing data movement and improving energy efficiency. DRAM-based PIM is particularly attractive due to its high density, mature manufacturing ecosystem, and compatibility with existing systems. Recent works exploit multiple levels of the DRAM hierarchy - including subarrays, banks, and 3D-stacked organizations - to enable in-memory computation using mechanisms such as multi-row activation, row-buffer operations, and near-bank compute units. However, these approaches introduce non-traditional current demand patterns that challenge the power delivery network (PDN). This paper surveys PDN challenges in DRAM-based PIM systems and proposes a unified taxonomy that characterizes PIM-induced current behavior along temporal (burst vs. sustained) and spatial (localized vs. distributed) dimensions. Using this framework, we analyze how representative PIM techniques stress the PDN through bursty activations, multi-row concurrency, and large-scale parallel execution, leading to voltage droop, IR drop, and thermal hotspots. We further discuss DRAM-specific mitigation strategies leveraging existing architectural and circuit-level mechanisms, including timing constraints, memory controller scheduling, data placement, and bank- and vault-level power management. This survey highlights the importance of PDN-aware design for scalable and reliable DRAM-based PIM systems and outlines key future research directions.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Desk Editor's Note private letter to a colleague

This is a survey that organizes existing DRAM PIM work around a temporal-spatial current taxonomy but adds no new measurements or derivations of its own.

read the letter

The main point is that this paper surveys power delivery network issues in DRAM-based compute-in-memory and proposes a simple taxonomy to classify current demands as burst versus sustained and localized versus distributed. It uses that frame to discuss how techniques like multi-row activation, row-buffer ops, and near-bank compute create voltage droop, IR drop, and thermal problems, then lists standard mitigations such as controller scheduling, timing constraints, and bank-level power management. The taxonomy itself is the clearest new element, as a synthesis that pulls scattered observations into one grid. The paper does a clean job of connecting the representative mechanisms to PDN stress and of pointing out that existing DRAM features can help without requiring entirely new hardware. The discussion of future directions stays practical and focused on data placement and vault-level controls. The soft spots are straightforward and proportional. The analysis stays qualitative with no fresh simulations, quantitative summaries, or error bars from the cited works, so the severity of the claimed problems rests on whatever the prior papers already showed. The three example techniques may not exhaust the space of possible current patterns, especially if future PIM designs use different subarray concurrency or vault organizations that fall outside the four quadrants. Without a coverage argument or additional cases, the taxonomy and mitigation recommendations could turn out incomplete for some deployments. This paper is for engineers and researchers already working on memory systems or AI accelerators who need a quick map of the power issues rather than a primary result. It can save time for someone entering the area but will not replace reading the original measurements. It deserves a serious referee because the taxonomy is a reasonable organizing tool, the citations appear solid, and the topic matters for energy-efficient designs, even though the contribution is organizational rather than empirical.

Referee Report

1 major / 2 minor

Summary. This survey paper examines power delivery network (PDN) challenges arising in DRAM-based compute-in/near-memory (PIM) systems. It proposes a taxonomy that classifies PIM-induced current demands along temporal (burst vs. sustained) and spatial (localized vs. distributed) dimensions. The authors apply the taxonomy to analyze representative techniques—multi-row activation, row-buffer operations, and near-bank compute—and the resulting stresses including voltage droop, IR drop, and thermal hotspots. The manuscript reviews mitigation approaches based on timing constraints, memory-controller scheduling, data placement, and bank/vault-level power management, and concludes by stressing the need for PDN-aware design in scalable DRAM-PIM systems while listing future research directions.

Significance. If the taxonomy proves robust, the survey could serve as a useful organizing lens for designers and researchers working on DRAM-PIM, encouraging earlier consideration of power-delivery constraints. Its primary contribution is synthesis of existing literature rather than new quantitative results or proofs; therefore its impact will depend on how comprehensively and accurately it maps the space of current-demand patterns.

major comments (1)

The central claim that the proposed taxonomy enables characterization of PDN stresses for scalable DRAM-PIM systems rests on the representativeness of the three chosen mechanisms (multi-row activation, row-buffer operations, near-bank compute). No coverage metric, exhaustive enumeration of alternative organizations (e.g., subarray-level logic or different vault configurations), or argument that these techniques exhaust the relevant current-signature space is supplied. This assumption is load-bearing for the taxonomy's claimed utility and for the derived mitigation recommendations.

minor comments (2)

The abstract and introduction would benefit from an explicit statement of how many PIM techniques are analyzed and which sections contain the detailed mapping onto the taxonomy quadrants.
Several mitigation strategies are described qualitatively; adding even brief pointers to quantitative results or simulation data from the cited works would improve clarity without altering the survey nature of the manuscript.

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for the constructive feedback on our survey. We address the single major comment below, acknowledging the gap in explicit coverage discussion while strengthening the manuscript's presentation of the taxonomy's scope.

read point-by-point responses

Referee: The central claim that the proposed taxonomy enables characterization of PDN stresses for scalable DRAM-PIM systems rests on the representativeness of the three chosen mechanisms (multi-row activation, row-buffer operations, near-bank compute). No coverage metric, exhaustive enumeration of alternative organizations (e.g., subarray-level logic or different vault configurations), or argument that these techniques exhaust the relevant current-signature space is supplied. This assumption is load-bearing for the taxonomy's claimed utility and for the derived mitigation recommendations.

Authors: We agree that the manuscript does not supply an exhaustive enumeration, coverage metric, or formal argument that the three mechanisms exhaust the current-signature space. These techniques were selected because they are prominent in the surveyed literature and map distinctly onto the taxonomy axes (multi-row activation as burst-localized, row-buffer operations as sustained-distributed, and near-bank compute as high-parallelism). In the revised version we will add a new subsection following the taxonomy definition that (1) states the selection rationale, (2) explicitly lists example alternative organizations such as subarray-level logic and varied HBM vault configurations, and (3) clarifies that the taxonomy is offered as a general organizing lens rather than a complete enumeration. This makes the scope and limitations transparent while preserving the survey's synthesis contribution. revision: yes

Circularity Check

0 steps flagged

No circularity: survey taxonomy and analysis are self-contained organizational contributions

full rationale

This paper is a survey that proposes a taxonomy along temporal and spatial dimensions to characterize current-demand patterns in DRAM-based PIM and then applies it to representative techniques drawn from prior literature. No equations, fitted parameters, predictions, or first-principles derivations appear in the provided text. The central claim that PDN-aware design is important rests on qualitative analysis of existing mechanisms rather than any reduction to quantities defined by the paper's own inputs or self-citations. The taxonomy is presented as a new organizational lens, not as a result forced by or equivalent to the surveyed data. External citations are to independent prior works and do not form a load-bearing self-citation chain.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

As a survey the paper rests on standard computer-architecture assumptions about DRAM hierarchy and power delivery networks; no free parameters, ad-hoc axioms, or invented entities are introduced in the abstract.

pith-pipeline@v0.9.0 · 5540 in / 1094 out tokens · 38319 ms · 2026-05-10T18:53:26.408278+00:00 · methodology

discussion (0)

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Citations machine-checked in the Pith Canon. Every link opens the source theorem in the public Lean library.

IndisputableMonolith/Foundation/RealityFromDistinction.lean reality_from_one_distinction unclear

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unclear
Relation between the paper passage and the cited Recognition theorem.

subarray-level PIM... bank-level PIM... 3D level PIM... mitigation strategies leveraging existing architectural and circuit-level mechanisms

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