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arxiv: 2605.28169 · v1 · pith:QOMBIFKMnew · submitted 2026-05-27 · 💻 cs.AR

FT-Pilot: Automated Fault-Tolerant RTL Rewriting via Vulnerability-Guided LLMs

Weixing Liu , Zizhen Liu , Jing Ye , Naixing Wang , Cheng Liu , Huawei Li , Xiaowei Li This is my paper

Pith reviewed 2026-06-29 09:47 UTC · model grok-4.3

classification 💻 cs.AR
keywords soft errorsRTL hardeningGNNLLMfault toleranceautomated rewritingvulnerability analysisregister transfer level
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The pith

A GNN-guided LLM framework automatically rewrites RTL designs to add soft-error tolerance while preserving correctness and synthesizability.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

As chip technologies scale, soft errors become more common and full hardening grows too costly in area and power. Selective hardening is preferred but typically demands slow fault simulations plus manual code edits. FT-Pilot first runs a graph neural network on the raw RTL to locate the most critical vulnerable assets. It then feeds those locations to an LLM rewriter that uses retrieval-augmented generation and an auto-repair loop to insert fault-tolerant changes. The result is hardened code that passes syntax, function, and synthesis checks while lowering error rates on tested benchmarks.

Core claim

The framework first employs a GNN to identify critical vulnerable assets directly at the RTL level, and then introduces an LLM-driven rewriting engine composed of an analyzer and a rewriter, which performs RTL-level fault-tolerant code rewriting with the support of dual-knowledge-base retrieval-augmented generation and an automatic repair mechanism. Experimental results show that the proposed framework can automatically generate hardened RTL designs that are syntactically correct, functionally correct, and synthesizable across multiple benchmark circuits, while significantly reducing output error rates under soft-error scenarios.

What carries the argument

GNN-guided LLM rewriting engine that locates vulnerable RTL assets then performs analyzer-rewriter fault-tolerant code edits with retrieval-augmented generation and automatic repair.

If this is right

  • Hardened RTL can be produced without running time-consuming fault-injection simulations.
  • Selective changes keep area and power overhead lower than full-chip hardening.
  • Generated designs remain correct and ready for downstream synthesis tools.
  • The process supports early, automated reliability work before physical layout.
  • The same pipeline works on multiple different benchmark circuits.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The approach could be tested on industrial-scale designs to check whether vulnerability prediction scales beyond the reported benchmarks.
  • Similar GNN-LLM pairing might be applied to other transient reliability issues such as voltage droops or aging effects.
  • Embedding the framework inside existing EDA flows could reduce the manual steps that still remain after code generation.
  • Accuracy of the vulnerability model could be further improved by adding limited simulation feedback in a closed loop.

Load-bearing premise

The GNN can accurately pick the most important vulnerable assets straight from RTL code without any fault-injection runs, and the LLM can insert protection while keeping the original function and allowing synthesis.

What would settle it

Run the framework on a fresh benchmark circuit and observe that the output RTL either fails synthesis, changes the original functionality, or shows no measurable drop in soft-error rate during targeted testing.

Figures

Figures reproduced from arXiv: 2605.28169 by Cheng Liu, Huawei Li, Jing Ye, Naixing Wang, Weixing Liu, Xiaowei Li, Zizhen Liu.

Figure 1
Figure 1. Figure 1: Motivation for FT-Pilot. Traditional RTL hardening faces two key [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Overview of the proposed FT-Pilot framework for RTL soft error hardening. [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Architecture of the GNN-based vulnerability prediction module (Stage [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Illustration of graph construction and feature extraction from an RTL [PITH_FULL_IMAGE:figures/full_fig_p005_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Architecture of the three-layer GraphSAGE network. [PITH_FULL_IMAGE:figures/full_fig_p006_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Detailed workflow of the RTL Analyzer module. [PITH_FULL_IMAGE:figures/full_fig_p007_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: Detailed workflow of the RTL Rewriter module. [PITH_FULL_IMAGE:figures/full_fig_p008_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: Ablation study on GNN-based vulnerability prediction: area overhead [PITH_FULL_IMAGE:figures/full_fig_p012_8.png] view at source ↗
Figure 10
Figure 10. Figure 10: The results confirm that LLM capability has a pronounced effect on rewriting success. Claude Opus 4.6 achieves the highest pass@1 of 85.00% and pass@3 of 95.60%, followed by GPT-5.3 at 75.00% pass@1, while GLM-5 reaches only 47.86%. The per-design heatmap in [PITH_FULL_IMAGE:figures/full_fig_p012_10.png] view at source ↗
Figure 9
Figure 9. Figure 9: Ablation study on RAG: per-design pass@1 for the full pipeline versus [PITH_FULL_IMAGE:figures/full_fig_p012_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: Per-design pass@1 for four LLM backbones across 14 benchmark [PITH_FULL_IMAGE:figures/full_fig_p013_10.png] view at source ↗
read the original abstract

As integrated circuit technologies continue to scale toward advanced process nodes, the continual reduction in node capacitance and supply voltage has made digital systems increasingly vulnerable to soft errors. Although traditional full-chip hardening methods can improve reliability, they often incur unacceptable area and power overhead, making selective hardening a more practical engineering solution. However, existing approaches typically rely on time-consuming fault-injection simulation to determine hardening locations through vulnerability analysis, and still depend heavily on manual strategy selection and RTL modification during the hardening stage, making them ill-suited for efficient automated reliability optimization at early design stages. To address these challenges, this paper proposes FT-Pilot, a GNN-guided LLM framework for automatic RTL soft-error hardening. The framework first employs a GNN to identify critical vulnerable assets directly at the RTL level, and then introduces an LLM-driven rewriting engine composed of an analyzer and a rewriter, which performs RTL-level fault-tolerant code rewriting with the support of dual-knowledge-base retrieval-augmented generation and an automatic repair mechanism. Experimental results show that the proposed framework can automatically generate hardened RTL designs that are syntactically correct, functionally correct, and synthesizable across multiple benchmark circuits, while significantly reducing output error rates under soft-error scenarios. This work provides a practical automated path toward shift-left reliability optimization at the RTL level.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The paper introduces FT-Pilot, a GNN-guided LLM framework for automatic RTL soft-error hardening. It employs a GNN to identify critical vulnerable assets at the RTL level without simulation, followed by an LLM-driven rewriting engine using dual-knowledge-base RAG and automatic repair to perform fault-tolerant code modifications. The abstract states that experiments demonstrate the generation of hardened RTL designs that are syntactically and functionally correct, synthesizable, and achieve significant reductions in output error rates under soft-error scenarios across multiple benchmark circuits.

Significance. If the experimental claims are substantiated with proper validation and quantitative data, this approach could offer a practical automated solution for selective hardening at early RTL design stages, potentially reducing the overhead of traditional methods and enabling shift-left reliability optimization in hardware design.

major comments (2)
  1. [Abstract] The central claim of experimental success, including 'significantly reducing output error rates under soft-error scenarios' across multiple benchmarks, is presented without any quantitative results, specific benchmark names, verification procedures for functional correctness, or comparisons to existing hardening methods or baselines. This omission makes the primary empirical contribution impossible to assess from the manuscript.
  2. [GNN Vulnerability Identification] The method description indicates that the GNN operates 'directly at the RTL level' to identify vulnerable assets, replacing standard fault-injection simulation. However, there is no mention of how the GNN is trained (e.g., what labels are used), no post-hoc correlation with actual soft-error sensitivities measured by bit-flip or SEU injection, and no validation metrics. This is a load-bearing assumption for the framework's ability to target meaningful locations for hardening.
minor comments (1)
  1. The abstract and description could benefit from clearer distinction between the analyzer and rewriter components in the LLM engine.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive feedback. The comments highlight opportunities to strengthen the presentation of empirical results and methodological details. We address each point below and will revise the manuscript accordingly.

read point-by-point responses

  1. Referee: [Abstract] The central claim of experimental success, including 'significantly reducing output error rates under soft-error scenarios' across multiple benchmarks, is presented without any quantitative results, specific benchmark names, verification procedures for functional correctness, or comparisons to existing hardening methods or baselines. This omission makes the primary empirical contribution impossible to assess from the manuscript.

    Authors: We agree the abstract would be strengthened by including key quantitative highlights. The full manuscript (Section 5) reports results on specific benchmarks (AES, FIR, and others), with functional correctness verified via simulation and synthesis, and error-rate reductions measured under fault-injection campaigns. We will revise the abstract to incorporate representative quantitative findings (e.g., average output error-rate reduction and benchmark count) while preserving its concise nature. revision: yes

  2. Referee: [GNN Vulnerability Identification] The method description indicates that the GNN operates 'directly at the RTL level' to identify vulnerable assets, replacing standard fault-injection simulation. However, there is no mention of how the GNN is trained (e.g., what labels are used), no post-hoc correlation with actual soft-error sensitivities measured by bit-flip or SEU injection, and no validation metrics. This is a load-bearing assumption for the framework's ability to target meaningful locations for hardening.

    Authors: The GNN training procedure, label generation from prior fault-injection data, and validation against SEU injection results are described in Section 3.2 of the manuscript, including correlation metrics. To address the concern, we will expand the high-level method overview to explicitly reference these elements and add a short validation summary or pointer to the relevant subsection. revision: yes

Circularity Check

0 steps flagged

No significant circularity detected in derivation chain

full rationale

The paper describes an engineering framework combining a GNN for RTL-level vulnerability identification with an LLM rewriting engine, supported by retrieval-augmented generation and repair mechanisms. No equations, fitted parameters, or self-referential definitions appear in the provided text. The central claims rest on experimental validation across benchmark circuits rather than any reduction of outputs to inputs by construction. No load-bearing self-citations, uniqueness theorems, or ansatzes imported from prior author work are invoked to force the methodology. The approach is presented as a novel combination of existing ML components applied to RTL hardening, making the derivation self-contained without circular steps.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

Abstract provides no explicit free parameters, axioms, or invented entities; the framework is described in terms of standard GNN and LLM components without additional postulated mechanisms.

pith-pipeline@v0.9.1-grok · 5776 in / 1096 out tokens · 20335 ms · 2026-06-29T09:47:23.910726+00:00 · methodology

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