Pith. sign in

REVIEW 4 major objections 3 minor 1 cited by

A nested MLMC framework for efficient simulations on FPGAs

T0 review · 4 major / 3 minor · reviewed 2026-08-08 · deepseek-v4-flash

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗

Pith's one-line read Nested MLMC with cheap normals and tuned bit-widths claims 5–7x savings.

desk verdict Genuinely novel integration of per-variable, per-level fixed-point bit-width optimization with nested MLMC and approximate normals, but the headline 5-7x savings rest on an unmeasured cost constant and no FPGA implementation yet. read the letter →

arxiv 2502.07123 v1 pith:WIGVES46 submitted 2025-02-10 q-fin.CP cs.NAmath.NA

Irina-Beatrice Haas , Michael B. Giles This is my paper · ORCID
classification q-fin.CPcs.NAmath.NA MSC 65C0565C3065G5091G60
keywords MultilevelMonteCarlonestedMLMCfixed-pointarithmeticbit-widthoptimizationapproximaterandomnumbersFPGAoptionpricingroundingerror
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper proposes a way to make Multilevel Monte Carlo (MLMC) option pricing cheaper by running the vast majority of simulated price paths in very low precision on FPGAs, with only a small correction computed in full precision. The authors build on a nested MLMC estimator that decomposes each level's payoff difference into a cheap low-precision average and a full-precision correction, and they design approximate normal random variables that can be generated almost for free on the FPGA. A rounding-error model based on algorithmic differentiation then assigns optimized fixed-point bit-widths to every intermediate variable on every level, so that the low-precision paths stay accurate enough while costing far less. Under their cost model, the per-level cost drops by a factor of 7 on the coarsest level and 5 on the next compared with standard MLMC, which is where most paths are generated. If the cost assumptions hold on real hardware, this would make FPGA acceleration of MLMC substantially more effective than existing mixed-precision schemes that use uniform precision.

What carries the argument

The central machinery is the nested MLMC estimator, which splits each level's expectation into a low-precision term and a correction term so that cheap approximate paths can be used without bias. Around it, three pieces carry the argument: (1) approximate inverse-CDF normal generators (piecewise-constant LUT, sum-of-variables with an iteratively optimized LUT, and piecewise-linear dyadic intervals) that make low-precision increments nearly free on FPGA; (2) an error model using first-order Taylor expansion and algorithmic differentiation, giving variance bounds V_indep and V_corr that express the output error as a sum over variables of sensitivity times rounding error; and (3) a cost model for fixed-point operations that makes the bit-width optimization separable per variable, solved with a Lagrange multiplier and golden-section search.

What would settle it

Implement the low-precision path generator on an actual FPGA with the proposed LUT-based RNG, measure the true ratio of CPU normal-generation cost to FPGA per-step cost, and measure the variance of the correction ΔP−~ΔP with the optimized bit-widths; if the measured cost ratio falls well below $10^{4}$ or the correction variance exceeds the independent-error bound V_indep, the reported factor-7/5 savings will not be realized.

Watch

Extended reading notes

Core claim

The paper's central claim is that the cost of MLMC for Geometric Brownian motion can be cut by using approximate normal increments and fixed-point arithmetic with per-variable, per-level bit-widths, while keeping the estimator unbiased through the nested decomposition E[ΔP_l]=E[~ΔP_l]+E[ΔP_l−~ΔP_l]. The numerical results in Matlab, based on a cost model in which a full-precision CPU normal costs C_RNG=$10^{4}$ and the FPGA fixed-point path is much cheaper, show cost savings of a factor 7 at level 0 and a factor 5 at level 1 relative to standard MLMC, with optimized bit-widths outperforming the best uniform bit-width at every level. The authors further show that their framework improves on the existing mixed-precision MLMC framework by optimizing each intermediate variable separately rather than using a single precision for the whole level, and they observe that the per-variable squared errors stay roughly balanced over levels, which the fixed-precision approach cannot maintain.

Load-bearing premise

The savings hinge on the cost premise that generating one full-precision normal on the CPU costs about $10^{4}$ times as much as the entire fixed-point path on the FPGA, so the cheap paths are effectively free; that ratio is assumed, not measured, and the paper notes it may fail on fine levels.

Editorial extensions

If this is right

  • On levels 0 and 1, where most MLMC paths are generated, the estimated cost saving is a factor 7 and 5 respectively; the overall saving is significant because MLMC concentrates samples on coarse levels.
  • The bit-width optimization is done off-line and is independent of the target accuracy ε, so the on-line simulation is no more complex than standard MLMC.
  • Because the error model only needs payoff sensitivities from algorithmic differentiation, the same framework extends to other payoff functions and SDEs driven by approximate normals.
  • For the Milstein scheme, which puts an even larger fraction of work on coarse levels, the savings would be larger than for Euler–Maruyama.
  • Adapting bit-widths across levels keeps the per-variable rounding error roughly constant relative to the time step, so accuracy degrades like h rather than saturating as it would with fixed precision.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • A hardware implementation measuring the true ratio of CPU random-normal cost to FPGA fixed-point path cost would settle whether the factor-7 claim survives; the assumed C_RNG=10^4 is the single most consequential constant in the paper.
  • The independent-error bound V_indep used to allocate bit-widths is optimistic by construction; if rounding errors are positively correlated, real correction variances will be larger, requiring wider bit-widths or more samples than the optimization predicts.
  • The same per-variable bit-width optimization could be applied to half-precision floating point on GPUs, and the comparison would reveal whether FPGAs are the right target or merely a convenient one.
  • The approximate-RNG methods are analysed only for their MSE, not for the correlation between approximate and full-precision increments; if that correlation is weaker than assumed, the nested correction term's variance grows and erodes savings.
Share X Bluesky LinkedIn Reddit HN

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 3 minor

Summary. This paper proposes an extension of multilevel Monte Carlo in which, on each level, the expectation E[ΔP_ℓ] is split into a low-precision FPGA estimator E[~ΔP_ℓ] and a full-precision CPU correction E[ΔP_ℓ − ~ΔP_ℓ]. The low-precision path generation uses approximate inverse-CDF normal random numbers and fixed-point arithmetic; the bit-widths of every intermediate variable are chosen off-line by minimising an approximate level cost (Eq. (34)) under a linearised variance bound (Eqs. (26)-(28)) obtained via algorithmic differentiation. Three approximate RNG constructions are compared: piecewise-constant LUT, summed LUT variables, and dyadic piecewise-linear approximation. Numerical experiments in Matlab validate the error bounds on two levels and produce optimised bit-widths; using the cost model C_ℓ≈2^ℓ C_RNG with C_RNG=10^4, the paper reports a factor 5-7 saving at levels 0-1 relative to standard MLMC. No FPGA implementation or hardware measurements are presented.

Significance. The paper makes a useful methodological contribution: the linear rounding-error model with algorithmic differentiation, the off-line bit-width optimisation, and the coupled construction of approximate and full-precision normal variates are clearly stated, and the two-level Matlab validation in §4.4 provides evidence that the error bounds are not vacuous. The nested estimator with approximate normals inherits a rigorous cancellation structure from [11]. If the cost and variance assumptions were confirmed on hardware, the framework could be attractive for FPGA-accelerated option pricing, particularly on coarse MLMC levels where most paths are generated. The main reservation is that the headline savings are computed from the same model used to choose the bit-widths; the unmeasured constant C_RNG=10^4 and the untested assumption ~V_ℓ≈V_ℓ are load-bearing. The paper is honest about the absence of hardware measurements, which makes the central claim a plausible conjecture rather than an established result.

major comments (4)
  1. [§5 and §6.1, Eq. (34), Figure 5] The headline factor 5-7 saving is not an independent result: the level-cost ratio in Eq. (34) and Figure 5 is evaluated with the same cost model C_ℓ≈2^ℓ C_RNG and the same variance bound V_indep that were used to optimise the bit-widths. The constant C_RNG=10^4 (Section 5, Section 6.1) is neither measured nor cited, and the sensitivity is material: replacing C_RNG=10^4 by C_RNG=100 changes ~C_0/C_0 from 0.0041 to 0.41, which, after adding sqrt(V^Δ_0/V_0) in Eq. (34), removes the level-0 saving. A load-bearing claim therefore needs either measured CPU/FPGA costs or a parameter sweep showing the savings persist over a credible range of C_RNG.
  2. [§6, Eq. (33)] The assumption ~V_ℓ≈V_ℓ introduced before Eq. (33) is load-bearing because ~V_ℓ enters the minimised level cost and the optimal number of low-precision samples N~ℓ=λ*sqrt(~V_ℓ/~C_ℓ). No experiment in §4.4 or §6 reports ~V_ℓ for the optimised bit-widths or for the Section 3 RNG methods. If ~V_ℓ/V_ℓ is larger than 1, the first term in Eq. (33) increases and the savings in Figure 5 shrink. Please tabulate ~V_ℓ and V_ℓ by level.
  3. [Abstract, §7] The abstract claims 'higher computational savings than the existing mixed-precision MLMC frameworks', but no quantitative comparison with [3] or [23] is supplied; Figure 5 compares nested with standard MLMC only. This claim should either be backed by a benchmark against the earlier mixed-precision frameworks or be narrowed to savings relative to standard MLMC.
  4. [§4.4] The validation of the error model in §4.4 covers only a single level with N=1 and one correction level with N=16 time steps, and Figure 2 uses truncated full-precision normals; the text states that approximate-RNG cases were tested but provides no plot or table. Since the bit-width optimisation is run for levels 0-10 (Figure 4), the paper should either extend the validation to the levels used in the optimisation or explicitly limit the error-model claims to the tested configurations.
minor comments (3)
  1. [§3.2, Eq. (17)] The relationship between J and j is implicit; please state explicitly that j is obtained from the leading d bits of J, since Eq. (17) otherwise reads ambiguously.
  2. [Figure 5] The y-axis label '√~C/C + √~V/V' does not match Eq. (34), where the second term uses V^Δ, not ~V; please align the notation between the figure and the equation.
  3. [§6.2] The symbol d*_{i,ℓ}=d_{i,ℓ} conflates the real-valued Lagrange solution with the rounded integer bit-width; a separate notation for the rounded values would prevent confusion.

Circularity Check

1 steps flagged · score 4.0 of 10

The factor-7/5 savings are the in-sample value of the same level-cost objective used to choose the bit-widths, resting on the unmeasured CPU RNG cost constant C_RNG=10^4.

  1. fitted input called prediction [Section 6.1, Eq. (34) and Figure 5; cost constants from Section 5]
    "To optimise the bit-widths of all variables in the nested MLMC framework, at each level the aim is to minimise the level cost (33) which, using the fact that Cℓ≫ ˜Cℓ, is approximated as √Vℓ ˜Cℓ + √V∆ℓ Cℓ. ... The numerical results in Figure 5 show that the cost factor for both uniform and optimised bit-widths is smaller than 1 ... our Figure 5 shows a factor 7 in computational cost savings at level 0 and a factor 5 at level 1."

    The bit-widths are selected by minimizing the level cost (34), and Figure 5 reports exactly that same level-cost expression at the selected widths. The FPGA costs 41/277 come from the same cost model (31) used in the objective, and the CPU baseline is the assumed constant C_RNG=10^4 from Section 5, with no measurement or external benchmark. Hence the factor-7/5 'savings' are the value of the optimized objective under the model's own assumptions: a restatement of the cost model and optimization criterion, not an independent prediction. The error model has independent support from Section 4.4 fixed-point tests, but the absolute savings claim reduces to the unvalidated cost-model input.

full rationale

The derivation chain for the estimator and the error model is mostly self-contained: the nested MLMC decomposition, the variance bounds Vindep/Vcorr, and the fixed-point bit-width rounding model are all derived in the paper and checked numerically against Matlab Fixed-Point Designer simulations (Section 4.4), so those steps are not circular. The self-citations to [11,12] are prior mathematical results by the co-author and are used as foundations, not as a way to forbid alternatives; they do not by themselves create circularity. The genuinely problematic step is the conversion of the optimization into a claimed speedup: the bit-widths are optimized against Eq. (34), and Figure 5 evaluates the same Eq. (34), while the CPU cost baseline C_RNG = 10^4 is assumed rather than measured. Consequently the reported factor-5/7 savings are an in-sample evaluation of an objective function rather than an out-of-sample or hardware-validated prediction. This is partial circularity in the central comparative claim, though independent content in the error model prevents the whole paper from reducing to its inputs.

Assumptions & free parameters 3 free parameters · 7 assumptions · 0 invented entities

The central savings prediction rests on several empirical constants (C_RNG, exponents, sensitivities) and modeling assumptions (linear error propagation, independence, negligible FPGA RNG cost). No new physical entities are postulated.

free parameters (3)
  • C_RNG = 10^4
    Assumed CPU cost per full-precision normal random number in Section 5; directly sets the claimed savings.
  • exponents e_i = from 10^6 paths
    Section 4.1: max-absolute-value scaling for each fixed-point variable; enters the error model and bit-width optimization.
  • sensitivities xbar_i = AD on 10^6 paths
    Section 4.2: payoff sensitivities used in the linear error model; estimated, not derived analytically.
assumptions (7)
  • standard math Validity of the MLMC telescoping sum and optimal sample allocation formulas (Eqs. 3, 8).
    Section 2.1 uses these standard MLMC results without proof.
  • domain assumption The first-order Taylor expansion (Eq. 23) captures the payoff error from rounding.
    Section 4.2 linearizes P - tilde P in the rounding errors and ignores higher-order terms.
  • domain assumption Sensitivities and rounding errors are independent; the optimistic bound also assumes independence across variables.
    Section 4.2, before Eq. (26), states this independence assumption to obtain Vindep.
  • domain assumption Rounding errors are uniformly distributed on the quantization interval.
    Section 4.1, Eq. (22), yields the constant factor in Vindep.
  • domain assumption Variance of a low-precision sample equals the full-precision variance, tilde V_l ≈ V_l.
    Section 6, paragraph before Eq. (33), states this approximation.
  • domain assumption CPU path cost is dominated by normal random number generation, C_l ≈ 2^l C_RNG >> tilde C_l.
    Section 5 and Eq. (34); the cost saving hinges on this.
  • ad hoc to paper The level cost objective is convex in the bit-widths.
    Section 6.1 admits convexity is not proved formally but uses golden section search.

how reviews work

0 comments
Cite this review

Pith. "Pith review of A nested MLMC framework for efficient simulations on FPGAs." pith.science (2026). https://pith.science/paper/WIGVES46

@misc{pith2026250207123,
  author       = {Pith},
  title        = {Pith review of: A nested MLMC framework for efficient simulations on FPGAs},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/WIGVES46}},
  note         = {Machine review of arXiv:2502.07123}
}
read the original abstract

Multilevel Monte Carlo (MLMC) reduces the total computational cost of financial option pricing by combining SDE approximations with multiple resolutions. This paper explores a further avenue for reducing cost and improving power efficiency through the use of low precision calculations on configurable hardware devices such as Field-Programmable Gate Arrays (FPGAs). We propose a new framework that exploits approximate random variables and fixed-point operations with optimised precision to generate most SDE paths with a lower cost and reduce the overall cost of the MLMC framework. We first discuss several methods for the cheap generation of approximate random Normal increments. To set the bit-width of variables in the path generation we then propose a rounding error model and optimise the precision of all variables on each MLMC level. With these key improvements, our proposed framework offers higher computational savings than the existing mixed-precision MLMC frameworks.

Figures

Figures reproduced from arXiv: 2502.07123 by the authors.

Figure 1
Figure 1. Mean-squared error for RNG methods 1, 2 (before and a [PITH_FULL_IMAGE:figures/full_fig_p007_1.png] view at source ↗
Figure 2
Figure 2. Simulated variance of the error and variance estimates th [PITH_FULL_IMAGE:figures/full_fig_p010_2.png] view at source ↗
Figure 3
Figure 3. q C/C ˜ + q V /V ˜ versus λ for levels 0 and 8. for a value of the Lagrange multiplier λ which gives the desired C˜ ℓ(d). Hence, the Lagrange multiplier λ controls the trade-off between cost and variance. Note also that because of the form of the variance bound (26) and cost (31), equation (35) gives a set of uncoupled nonlinear scalar equations for each pair i, ℓ, which are easily solved to obtain di,ℓ. Similarly, … view at source ↗
Figures from the paper (2 more)
Figure 4
Figure 4. Figure 4: Optimal bit-widths for each variable, best uniform bit-width, and required RNG ac￾curacy, all versus level. 0 2 4 6 8 10 0.1 0.15 0.2 0.25 0.3 0.35 0.4 uniform optimised [PITH_FULL_IMAGE:figures/full_fig_p013_4.png]
Figure 7
Figure 7. Figure 7: Upper bounds 1 12E[¯x 2 i ]4ei,ℓ−di,ℓ on the expected squared errors E[¯x 2 i δx2 i ]. 7 Conclusion and future directions In this paper we proposed a nested MLMC framework that offers important computational savings by performing most calculations in low precision and …

Discussion (0). Continue with ORCID to comment.

Forward citations

Cited by 1 Pith paper

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. Eliciting Fine-Tuned Transformer Capabilities via Inference-Time Techniques

    cs.LG 2025-06 reject novelty 2.0 of 10

    The paper claims that in-context learning with finite example sets can approximate supervised fine-tuning in transformers, but the proof assumes the very approximation it sets out to establish.

Reference graph

Works this paper leans on

26 extracted references · 21 canonical work pages · cited by 1 Pith paper

  1. [3]

    Brugger, C

    C. Brugger, C. de Schryver, N. Wehn, S. Omland, M. Hefter, K. Ritter, A. Kostiuk, and R. Korn. Mixed precision Multilevel Monte Carlo on hybrid computing sy stems. In Pro- ceedings of the IEEE Conference on Computational Intellige nce for Financial Engineering & Economics (CIFEr) , pages 215–222. IEEE, 2014. doi:10.1109/CIFEr.2014.6924076

    work page arXiv 2014

  2. [11]

    Giles and O

    M. Giles and O. Sheridan-Methven. Analysis of nested multilevel M onte Carlo using ap- proximate normal random variables. SIAM/ASA J. Uncertain. Quantif. , 10:200–226, 2021. doi:10.1137/21M1399385

    work page doi:10.1137/21m1399385 2021

  3. [23]

    Sheridan-Methven and M

    O. Sheridan-Methven and M. Giles. Rounding error using low prec ision approximate random variables. SIAM J. Sci. Comput. , 46(4), 2024. doi:10.1137/23M1552814

    work page doi:10.1137/23m1552814 2024

  4. [1]

    Arciniega and E

    A. Arciniega and E. Allen. Rounding error in numerical solution of st ochastic differential equations. Stoch. Anal. Appl. , 21(2):281–300, 2003. doi:10.1081/SAP-120019286

    work page doi:10.1081/sap-120019286 2003

  5. [2]

    Boutros, B

    A. Boutros, B. Grady, M. Abbas, and P. Chow. Build fast, trade fast: FPGA- based high-frequency trading using high-level synthesis. In 2017 International Con- ference on ReConFigurable Computing and FPGAs (ReConFig) , pages 1–6, 2017. doi:10.1109/RECONFIG.2017.8279781

    arXiv 2017

  6. [4]

    Cheung, D.-U

    R. Cheung, D.-U. Lee, W. Luk, and J. Villasenor. Hardware gener ation of arbi- trary random number distributions from uniform distributions via th e inversion method. IEEE Transactions on Very Large Scale Integration (VLSI) Sy stems, 15:952–962, 2007. doi:10.1109/TVLSI.2007.900748

    work page arXiv 2007

  7. [5]

    G. Chow, A. Tse, Q. Jin, W. Luk, P. Leong, and D. Thomas. A mixed precision Monte Carlo methodology for reconfigurable accelerator systems. In Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays , FPGA ’12, page 57–66, New York, NY, USA, 2012. Association for Computing Machinery. doi:10.1 145/2145694.2145705

    work page arXiv 2012

  8. [6]

    de Schryver, P

    C. de Schryver, P. Torruella, and N. Wehn. A multi-level Monte Ca rlo FPGA accelerator for option pricing in the Heston model. 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) , pages 248–253, 2013. doi:10.7873/DATE.2013.063

    work page doi:10.7873/date.2013.063 2013

Show all 26 references
  1. [7]

    Gaffar, O

    A. Gaffar, O. Mencer, W. Luk, P. Cheung, and N. Shirazi. Floating -point bitwidth analysis via automatic differentiation. In 2002 IEEE International Conference on Field-Programmable Technology, pages 79–88, 2002. doi:10.1109/FPT.2002.1188677

    2002 arXiv

  2. [8]

    Gaffar, O

    A. Gaffar, O. Mencer, W. Luk, and P. Cheung. Unifying bit-width o ptimisation for fixed- point and floating-point designs. In 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines , pages 79–88, 2004. doi:10.5555/1025123.1025818

    2004

  3. [9]

    M. Giles. Multilevel Monte Carlo path simulation. Oper. Res. , 56(3):607–617, 2008. doi:10.1287/opre.1070.0496

    2008

  4. [10]

    M. Giles. Multilevel Monte Carlo methods. Acta Numer. , 24:259–328, 2015. doi:10.1017/S096249291500001X

    2015 doi

  5. [12]

    Giles and O

    M. Giles and O. Sheridan-Methven. Approximating inverse cumula tive distribution functions to produce approximate random variables. ACM Trans. Math. Software , 49(3), sep 2023. doi:10.1145/3604935

    2023 doi

  6. [13]

    Glasserman

    P. Glasserman. Monte Carlo Methods in Financial Engineering . Springer, New York, 2004. doi:10.1007/978-0-387-21617-1

    2004 doi

  7. [14]

    Developer reference for Intel ® oneAPI Math Kernel Library for C

    Intel. Developer reference for Intel ® oneAPI Math Kernel Library for C. v?CdfNormInv. Available at : https://www.intel.com/content/www/us/en/docs/onemkl/ developer-reference-c/2024-1/v-cdfnorminv .html. (Accessed: 21 November 2024)

    2024

  8. [15]

    Leber, B

    C. Leber, B. Geib, and H. Litz. High frequency trading accelera tion using FPGAs. In 2011 21st International Conference on Field Programmable Logic and Applications, pages 317–322,

    2011

  9. [16]

    D.-U. Lee, W. Luk, J. D. Villasenor, and P. Y. K. Cheung. A Gauss ian noise genera- tor for hardware-based simulations. IEEE Trans. Comput. , 53(12):1523–1534, Dec 2004. doi:10.1109/TC.2004.106

    2004 doi

  10. [17]

    D.-U. Lee, A. Gaffar, R. Cheung, O. Mencer, W. Luk, and G. Con stan- tinides. Accuracy-guaranteed bit-width optimization. IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems , 25(10):1990–2000, October 2006. doi:10.1109/TCAD.2006.873887

    1990

  11. [18]

    D.-U. Lee, R. Cheung, W. Luk, and J. Villasenor. Hierarchical se gmentation for hardware function evaluation. IEEE Transactions on Very Large Scale Integration (VLSI) Sy stems, 17 (1):103–116, 2009. doi:10.1109/TVLSI.2008.2003165

    2009

  12. [19]

    Lindsey, M

    B. Lindsey, M. Leslie, and W. Luk. A Domain Specific Language for accelerated Mul- tilevel Monte Carlo simulations. In Proceedings of the IEEE 27th International Confer- ence on Application-specific Systems, Architectures and Pr ocessors (ASAP) . IEEE, 2016. doi:10.1109/ASAP.201...

    2016

  13. [20]

    J. S. Malik and A. Hemani. Gaussian random number generation: A survey on hardware architectures. ACM Comput. Surv. , 49(3), Nov. 2016. doi:10.1145/2980052

    2016 doi

  14. [21]

    Fixed-Point Designer documentation

    MathWorks. Fixed-Point Designer documentation. Available at : https://uk.mathworks. com/help/fixedpoint/. (Accessed: November 2024)

    2024

  15. [22]

    Menon, M

    H. Menon, M. Lam, D. Osei-Kuffuor, M. Schordan, S. Lloyd, K. M ohror, and J. Hittinger. ADAPT: Algorithmic differentiation applied to floating-point precision t uning. In SC18: In- ternational Conference for High Performance Computing, Ne tworking, Storage and Analysis , pages 61...

    2018

  16. [24]

    Thomas, L

    D. Thomas, L. Howes, and W. Luk. A comparison of CPUs, GPUs, FPGAs, and mas- sively parallel processor arrays for random number generation. I n Symposium on Field Pro- grammable Gate Arrays , 2009. doi:10.1145/1508128.1508139

    2009

  17. [25]

    Woods, J

    R. Woods, J. McAllister, G. Lightbody, and Y. Yi. FPGA-based implementation of signal processing systems. John Wiley & Sons, 2008. doi:10.1002/9781119079231. 16

    2008 doi

  18. [2011]

    doi:10.1109/FPL.2011.64. 15

    2011 doi

Pith tools

Reviewed August 8, 2026 · model on record in the stance chip above.