Paper Citation Record · LEDGER

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs

As of 10 August 2026, this Paper Citation Record lists 37 of 37 outbound references and 0 inbound Pith citation observations for arXiv:2607.18519.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2607.18519 v1

Coverage vector

measured 37 of 37 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-08-01T15:14:12.820102Z

measured 37 of 37 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-10T06:31:04.303077+00:00

measured 0 of 0 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: cited_works

Reference resolution

37 of 37 outbound references displayed

verified exact0
verified fuzzy0
unresolved37
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

Observation 2e7217d6-0a67-4c06-8ebf-cf6259a24198 · outbound

This paper cites an unresolved cited work.

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs Unresolved cited work

Reference 1

Resolution: unresolved; no resolver link, observed 2026-08-01T15:14:07.393241Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 9216e046-780c-494f-b1e6-49799cb8c8cb · outbound

This paper cites ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learning.

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learning

Reference 2

Resolution: unresolved; no resolver link, observed 2026-08-01T15:14:07.521389Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 674566bb-f673-4551-95f6-2a9dee002336 · outbound

This paper cites SysVCoder: An LLM-Driven Framework for Systematic Generation of System-Level Design.

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs SysVCoder: An LLM-Driven Framework for Systematic Generation of System-Level Design

Reference 3

Resolution: unresolved; no resolver link, observed 2026-08-01T15:14:07.703079Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation bb988a77-a737-459a-a205-4406b1b913ab · outbound

This paper cites HDLCoRe: A Training-Free Framework for Mitigating Hallucinations in LLM-Generated HDL.

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs HDLCoRe: A Training-Free Framework for Mitigating Hallucinations in LLM-Generated HDL

Reference 4

Resolution: unresolved; no resolver link, observed 2026-08-01T15:14:07.817816Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation dacfc319-dc93-49ba-b839-33efbcb8a193 · outbound

This paper cites Lorecast: Layout-Aware Performance and Power Forecasting from Natural Language.

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs Lorecast: Layout-Aware Performance and Power Forecasting from Natural Language

Reference 5

Resolution: unresolved; no resolver link, observed 2026-08-01T15:14:07.949106Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 95a63cc0-226e-4a3a-8e25-67824024296a · outbound

This paper cites VeriOpt: PPA-Aware High-Quality Verilog Generation via Multi-Role LLMs.

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs VeriOpt: PPA-Aware High-Quality Verilog Generation via Multi-Role LLMs

Reference 6

Resolution: unresolved; no resolver link, observed 2026-08-01T15:14:08.080737Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 9ca06918-6dad-4ca7-8c3a-c635438c53a2 · outbound

This paper cites an unresolved cited work.

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs Unresolved cited work

Reference 7

Resolution: unresolved; no resolver link, observed 2026-08-01T15:14:08.217872Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation dc824629-bea8-437c-9813-9a024cd2f868 · outbound

This paper cites VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs.

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs

Reference 8

Resolution: unresolved; no resolver link, observed 2026-08-01T15:14:08.339342Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 9d0840b7-0517-4f72-bf98-67f684ac7785 · outbound

This paper cites Veritas: Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Form.

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs Veritas: Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Form

Reference 9

Resolution: unresolved; no resolver link, observed 2026-08-01T15:14:08.515995Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 2ab44f95-b489-4c65-b1ed-f519c8970ca5 · outbound

This paper cites Abstractions-of-Thought: Intermediate Representations for LLM Reasoning in Hardware Design.

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs Abstractions-of-Thought: Intermediate Representations for LLM Reasoning in Hardware Design

Reference 10

Resolution: unresolved; no resolver link, observed 2026-08-01T15:14:08.698321Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 85db7099-3a60-476f-95e5-0859342f8015 · outbound

This paper cites an unresolved cited work.

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs Unresolved cited work

Reference 11

Resolution: unresolved; no resolver link, observed 2026-08-01T15:14:08.808527Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation bc39b5c6-f78e-4d96-8e2a-ca939a8b7f77 · outbound

This paper cites From Natural Language to Silicon: The Representation Bottleneck in LLM Hardware Design.

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs From Natural Language to Silicon: The Representation Bottleneck in LLM Hardware Design

Reference 12

Resolution: unresolved; no resolver link, observed 2026-08-01T15:14:09.045687Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 57b4523f-46df-4a3e-9eb7-314bb9dedfc6 · outbound

This paper cites an unresolved cited work.

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs Unresolved cited work

Reference 13

Resolution: unresolved; no resolver link, observed 2026-08-01T15:14:09.201514Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 0f5b084a-3eef-4454-872e-7eda4e8d3c92 · outbound

This paper cites an unresolved cited work.

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs Unresolved cited work

Reference 14

Resolution: unresolved; no resolver link, observed 2026-08-01T15:14:09.390240Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 1a3b745f-0b98-43a7-b38c-9f5c029bb83d · outbound

This paper cites SecFSM: Knowledge Graph-Guided Verilog Code Generation for Secure Finite State Machines in Systems-on-Chip.

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs SecFSM: Knowledge Graph-Guided Verilog Code Generation for Secure Finite State Machines in Systems-on-Chip

Reference 15

Resolution: unresolved; no resolver link, observed 2026-08-01T15:14:09.660598Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation b17f3a37-d7e0-4099-b032-6dffdbd62362 · outbound

This paper cites an unresolved cited work.

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs Unresolved cited work

Reference 16

Resolution: unresolved; no resolver link, observed 2026-08-01T15:14:09.820065Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 1ea5fa0f-71d0-43a1-ac9b-7773c4e905f5 · outbound

This paper cites an unresolved cited work.

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs Unresolved cited work

Reference 17

Resolution: unresolved; no resolver link, observed 2026-08-01T15:14:09.944723Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 390532dc-74c7-4949-9ef9-913104731f2b · outbound

This paper cites an unresolved cited work.

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs Unresolved cited work

Reference 18

Resolution: unresolved; no resolver link, observed 2026-08-01T15:14:10.076147Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation f7bda274-0105-40af-9963-f906113e0188 · outbound

This paper cites CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair.

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair

Reference 19

Resolution: unresolved; no resolver link, observed 2026-08-01T15:14:10.263615Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 38e487f1-7e1f-4023-b565-213c27043dbd · outbound

This paper cites an unresolved cited work.

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs Unresolved cited work

Reference 20

Resolution: unresolved; no resolver link, observed 2026-08-01T15:14:10.456132Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation dcb741c7-cff9-4950-9f93-ae623c66a507 · outbound

This paper cites an unresolved cited work.

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs Unresolved cited work

Reference 21

Resolution: unresolved; no resolver link, observed 2026-08-01T15:14:10.682488Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation e9acc4c0-7104-4903-ac2f-38da49ae631f · outbound

This paper cites VeriMoA: A Mixture-of-Agents Framework for Spec-to-HDL Generation.

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs VeriMoA: A Mixture-of-Agents Framework for Spec-to-HDL Generation

Reference 22

Resolution: unresolved; no resolver link, observed 2026-08-01T15:14:10.781795Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation b5b3f273-b238-4eeb-992c-20db2b954d25 · outbound

This paper cites In2024 IEEE LLM Aided Design Workshop (LAD).

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs In2024 IEEE LLM Aided Design Workshop (LAD)

Reference 23

Resolution: unresolved; no resolver link, observed 2026-08-01T15:14:10.552996Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 3d7ee864-ebd9-487f-987d-96fdb7070ac2 · outbound

This paper cites Paradigm-Based Automatic HDL Code Generation Using LLMs.

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs Paradigm-Based Automatic HDL Code Generation Using LLMs

Reference 24

Resolution: unresolved; no resolver link, observed 2026-08-01T15:14:11.153759Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 174ff88f-b81f-44d3-ae42-5af09ba88d10 · outbound

This paper cites VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning.

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning

Reference 25

Resolution: unresolved; no resolver link, observed 2026-08-01T15:14:11.345252Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation c068915c-c93e-48e1-8d8b-14ec626531ee · outbound

This paper cites an unresolved cited work.

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs Unresolved cited work

Reference 26

Resolution: unresolved; no resolver link, observed 2026-08-01T15:14:10.939545Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation ab754f08-a62c-47d1-9883-98313771a904 · outbound

This paper cites Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedback.

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedback

Reference 27

Resolution: unresolved; no resolver link, observed 2026-08-01T15:14:11.555202Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation f619fb03-c0d3-4384-a6ff-b73966b20a55 · outbound

This paper cites VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation.

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation

Reference 28

Resolution: unresolved; no resolver link, observed 2026-08-01T15:14:11.677747Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation f501840f-07c2-4848-b241-f4c142912544 · outbound

This paper cites an unresolved cited work.

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs Unresolved cited work

Reference 29

Resolution: unresolved; no resolver link, observed 2026-08-01T15:14:11.426132Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 821d6856-3da0-4bbb-8afa-ca7adaa9273c · outbound

This paper cites an unresolved cited work.

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs Unresolved cited work

Reference 30

Resolution: unresolved; no resolver link, observed 2026-08-01T15:14:12.123644Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 10f88c34-b255-494e-8d8a-91a449f5a91b · outbound

This paper cites an unresolved cited work.

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs Unresolved cited work

Reference 31

Resolution: unresolved; no resolver link, observed 2026-08-01T15:14:12.323793Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 665383ad-5687-468b-aa3a-a2dd11246492 · outbound

This paper cites an unresolved cited work.

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs Unresolved cited work

Reference 32

Resolution: unresolved; no resolver link, observed 2026-08-01T15:14:11.825930Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation ddb73a30-d6d8-4a67-a867-95aec15842d8 · outbound

This paper cites an unresolved cited work.

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs Unresolved cited work

Reference 33

Resolution: unresolved; no resolver link, observed 2026-08-01T15:14:12.743580Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 1b3d6c88-3283-4d21-90c3-26ae5e207261 · outbound

This paper cites an unresolved cited work.

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs Unresolved cited work

Reference 34

Resolution: unresolved; no resolver link, observed 2026-08-01T15:14:12.820102Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation a4a11ad8-d484-460b-9788-ba95e63ad752 · outbound

This paper cites an unresolved cited work.

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs Unresolved cited work

Reference 35

Resolution: unresolved; no resolver link, observed 2026-08-01T15:14:12.553415Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation c6458aa0-cb15-4751-8e19-3a403b9895b4 · outbound

This paper cites Abstraction-of-Thought Makes Language Models Better Reasoners.

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs Abstraction-of-Thought Makes Language Models Better Reasoners

Reference 2024

Resolution: unresolved; no resolver link, observed 2026-08-01T15:14:09.511601Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 33850d85-f626-446a-932c-b76da9938d46 · outbound

This paper cites ScaleRTL: Scaling LLMs with Reasoning Data and Test-Time Compute for Accurate RTL Code Generation.

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs ScaleRTL: Scaling LLMs with Reasoning Data and Test-Time Compute for Accurate RTL Code Generation

Reference 2025

Resolution: unresolved; no resolver link, observed 2026-08-01T15:14:08.913455Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Pith citing papers

No inbound Pith citation observations are available.