Typed states for the displayed outbound observations.
Source: paper_references, paper_reference_links
Paper Citation Record · LEDGER
RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model
As of 9 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 9 inbound Pith citation observations for arXiv:2308.05345.
A citation records a reference. It does not transfer a finding from one paper to another.
Coverage vector
One-hop event checks from named stored sources.
Source: scholarly_work_events, retraction_status_cache, observed 2026-08-09T06:31:02.800959+00:00
Pith citing papers itemized under the disclosed page cap.
Source: paper_references, paper_reference_links, observed 2026-08-07T05:27:36.116201Z
A source-named dated measurement, never combined with another source.
Source: arxiv_reference, observed 2026-07-03T19:08:49.829179Z
Reference resolution
0 of 0 outbound references displayed
- verified exact0
- verified fuzzy0
- unresolved0
- parse uncertain0
- malformed identifier0
- metadata mismatch0
External citation measurements
No source-named external measurement is stored.
Outbound references
No outbound reference observations are available for this paper version.
Pith citing papers
Observation c76af563-6072-4a2a-80f2-724bee73e467 · inbound
From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification cites this paper.
From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model
Reference 44
- Resolution
- verified exact
- arxiv_id, observed 2026-05-22T18:01:54.470242Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.
Observation e00af0db-2ebd-456b-967f-954bb8a5dc2b · inbound
ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols cites this paper.
ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model
Reference 25
- Resolution
- unresolved
- no resolver link, observed 2026-08-07T05:27:36.116201Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation ae9f620a-8bc0-44ee-8e46-5e8db082ebdb · inbound
Spec2RTL-Agent: Automated Hardware Code Generation from Complex Specifications Using LLM Agent Systems cites this paper.
Spec2RTL-Agent: Automated Hardware Code Generation from Complex Specifications Using LLM Agent Systems RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model
Reference 6
- Resolution
- unresolved
- no resolver link, observed 2026-08-07T00:31:00.464408Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 0ec66da2-188b-4aa0-ad9e-db7e4d35ed1e · inbound
HYPERHEURIST: A Simulated Annealing-Based Control Framework for LLM-Driven Code Generation in Optimized Hardware Design cites this paper.
HYPERHEURIST: A Simulated Annealing-Based Control Framework for LLM-Driven Code Generation in Optimized Hardware Design RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model
Reference 13
- Resolution
- verified exact
- arxiv_id, observed 2026-05-10T09:18:31.652957Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.
Observation 3d5d9d3e-8043-428a-ba6d-849ead6e5f83 · inbound
UVMarvel: an Automated LLM-aided UVM Machine for Subsystem-level RTL Verification cites this paper.
UVMarvel: an Automated LLM-aided UVM Machine for Subsystem-level RTL Verification RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model
Reference 28
- Resolution
- verified exact
- arxiv_id, observed 2026-05-11T18:31:13.607006Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.
Observation e0a1726e-097f-4a4a-9c96-d81362237d81 · inbound
Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generation cites this paper.
Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generation RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model
Reference 11
- Resolution
- verified exact
- arxiv_id, observed 2026-06-29T18:53:51.248419Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.
Observation b59d7472-3626-4883-9d00-00644f5b25b8 · inbound
Alpha-RTL: Test-Time Training for RTL Hardware Optimization cites this paper.
Alpha-RTL: Test-Time Training for RTL Hardware Optimization RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model
Reference 28
- Resolution
- verified exact
- arxiv_id, observed 2026-07-02T07:06:44.149727Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.
Observation 463f3ad8-a58f-4bf7-8ddd-6ad287335458 · inbound
PDAGENT-BENCH: Characterizing, Grounding, and Architecting LLM Agents for VLSI Physical Design cites this paper.
PDAGENT-BENCH: Characterizing, Grounding, and Architecting LLM Agents for VLSI Physical Design RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model
Reference 20
- Resolution
- verified exact
- arxiv_id, observed 2026-07-03T19:08:49.830893Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.
Observation 89c1c522-7ddf-44bb-acb3-3c138501172b · inbound
Agentic Hardware Design as Repository-Level Code Evolution cites this paper.
Agentic Hardware Design as Repository-Level Code Evolution RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model
Reference 8
- Resolution
- metadata mismatch
- arxiv_id, observed 2026-07-01T18:45:58.333957Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.