arxiv: 2605.04704 · v2 · submitted 2026-05-06 · 💻 cs.AR · cs.SE

Recognition: unknown

UVMarvel: an Automated LLM-aided UVM Machine for Subsystem-level RTL Verification

Junhao Ye , Dingrong Pan , Hanyuan Liu , Yuchen Hu , Jie Zhou , Ke Xu , Xinwei Fang , Xi Wang

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Nan Guan Zhe Jiang

Authors on Pith no claims yet

Pith reviewed 2026-05-08 15:31 UTC · model grok-4.3

classification 💻 cs.AR cs.SE

keywords UVM testbench generationLLM-aided verificationRTL subsystem verificationautomated stimulus refinementbus protocol handlingcode coverage improvementintermediate representationverification time reduction

0 comments

The pith

UVMarvel uses LLMs with an intermediate representation and protocol libraries to automatically build subsystem UVM testbenches that reach 95.65 percent coverage.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper presents UVMarvel as an automated framework that leverages large language models to construct Universal Verification Methodology testbenches for subsystem-level register-transfer level designs. It translates heterogeneous specifications into protocol-correct environments through an intermediate representation paired with a bus protocol library, then refines stimuli using a signal tracker and verilog patching library. This targets the fact that verification consumes nearly 70 percent of integrated circuit development effort, replacing several days of manual work with a 4.5-hour automated process while delivering high code coverage across mainstream bus protocols.

Core claim

UVMarvel is the first framework capable of automatically constructing subsystem-level UVM testbenches across mainstream bus protocols. It achieves an average code coverage of 95.65 percent by introducing an Intermediate Representation and a Bus Protocol Library to translate heterogeneous specifications into protocol-correct testbenches, and employs a Signal Tracker and a Verilog Patching Library to guide LLM-based stimuli refinement, reducing verification time from several human working days to a 4.5-hour automated execution.

What carries the argument

The central mechanism is the combination of an Intermediate Representation for translating specifications, a Bus Protocol Library for ensuring correctness across protocols, a Signal Tracker for monitoring, and a Verilog Patching Library for directing LLM refinements to produce complete high-coverage UVM testbenches.

If this is right

Subsystem-level RTL verification environments become generatable automatically for different bus protocols without repeated manual coding.
Verification time for such subsystems drops from multiple human working days to a single automated run of 4.5 hours.
Average code coverage of 95.65 percent is attainable through LLM-guided stimulus refinement without deep micro-architectural expertise per design.
Heterogeneous specifications can be uniformly handled to produce reusable UVM structures across mainstream protocols.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

If the libraries generalize, the approach could shorten overall chip design cycles by allowing faster verification iterations.
Similar guidance structures might apply to other verification flows such as coverage-driven closure or property generation.
Integration into existing EDA tools could shift verification roles toward higher-level oversight rather than low-level coding.

Load-bearing premise

The assumption that these libraries and trackers together will guide LLMs to generate protocol-correct and high-coverage testbenches without needing substantial manual corrections or expert oversight for each new design.

What would settle it

Running the framework on a new complex subsystem using a mainstream bus protocol and finding that the output testbench requires extensive manual fixes or delivers code coverage below 80 percent would falsify the central claim.

Figures

Figures reproduced from arXiv: 2605.04704 by Dingrong Pan, Hanyuan Liu, Jie Zhou, Junhao Ye, Ke Xu, Nan Guan, Xinwei Fang, Xi Wang, Yuchen Hu, Zhe Jiang.

**Figure 1.** Figure 1: Verification dominates IC front-end development. While modulelevel complexity scales linearly, subsystem-level verification grows exponentially due to inter-IP dependencies. (Verif.: Verification, TB: testbench, Refi.: Refinement, Constr.:Construction, I/F: Interface, Complx.: Complexity) automate error detection and repair in Verilog code, ensuring comprehensive verification; AssertLLM[44] utilises thr… view at source ↗

**Figure 2.** Figure 2: UVMarvel Framework. (a) Testbench Construction: the IR translated from design specifications, together with the Bus Protocol Library, guiding the LLMs to construct UVM testbench; and (b) Stimuli Refinement: uncovered coverage data are interpreted by the Coverage Analyser, filtered DUT is identified through Signal tracker and Verilog Patcher, and the LLMs generate new stimuli or waiving points to improve co… view at source ↗

**Figure 4.** Figure 4: Generation of UVM bus components using the Bus Protocol Library, illustrated with AHB_Driver. It selects a protocol-specific UVM skeleton, then the LLM specialises it into DUT-specific code that is integrated as a key bus component.(Struct.: Structural, Synth.: Synthetic) 3.3 Coverage Analyser After the UVM testbench has been constructed with the assistance of IR and the Bus Protocol Library, the verificat… view at source ↗

**Figure 5.** Figure 5: Verilog Patching Process. The library reconstructs incomplete code fragments into valid blocks based on their syntax types. In the example, it appends missing endcase and default keywords to terminated case statements and wraps isolated logic fragments within always blocks containing appropriate sensitivity lists. The workflow is as follows. We take the key statements reported by the Signal Tracker, and th… view at source ↗

**Figure 6.** Figure 6: End-to-end verification time: UVMarvel vs. experts (across all benchmarks). We exclude the test planning/IR authoring phase (0-𝑡0) from time evaluation to ensure precision—although this slightly lowers the acceleration ratio- to aligns UVMarvel’s automated verification objectives with manually defined coverage goals, guaranteeing fair and objective experimental results. UVMarvel achieves 90% coverage ne… view at source ↗

**Figure 7.** Figure 7: Code coverage of MEIC [42], UVM2 [46], and UVMarvel across six benchmark tests, evaluated using five coverage components. Watchdog Pwrctrl Cordic LPctrl Idlecontrol Busremap Average Spec IR +29.70% Coverage(%) 0 20 40 60 80 100 view at source ↗

**Figure 8.** Figure 8: Code coverage comparison between IR and SPEC inputs across six benchmark tests, showing higher coverage achieved by IR inputs. APB AHB P_Channel Q_Channel AXI Average 100 80 60 40 20 0 SRG(%) LLM(no lib) LLM(with bus lib) +65.78% view at source ↗

**Figure 10.** Figure 10: Coverage improvement achieved by the three methods across six benchmark tests, with the filtered DUT getting the highest performance view at source ↗

read the original abstract

Verification presents a major bottleneck in Integrated Circuit (IC) development, consuming nearly 70% of total effort. While the Universal Verification Methodology (UVM) improves reuse through structured verification environments, constructing subsystem-level UVM testbenches and generating high-quality stimuli still require extensive manual coding, repeated EDA tool runs, and deep protocol and micro-architectural expertise. We present UVMarvel, an automated verification framework that leverages Large Language Models (LLMs) to build UVM testbenches for subsystem-level RTL. UVMarvel introduces an Intermediate Representation (IR) and a Bus Protocol Library to translate heterogeneous specifications into protocol-correct subsystem-level UVM testbenches, and employs a Signal Tracker and a Verilog Patching Library to guide LLM-based stimuli refinement. UVMarvel is the first framework capable of automatically constructing subsystem-level UVM testbenches across mainstream bus protocols, and it achieves an average code coverage of 95.65%, while reducing verification time from several human working days to a 4.5-hour automated execution.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Desk Editor's Note private letter to a colleague

UVMarvel gives a working LLM pipeline with IR and protocol libraries that turns specs into subsystem UVM testbenches and hits 95% coverage in hours on the cases shown.

read the letter

The core contribution is a practical scaffolding system that feeds an Intermediate Representation and Bus Protocol Library into an LLM, then uses a Signal Tracker plus Verilog Patching Library to clean up the output. The authors walk through the translation steps for AXI, APB, and AXI-Lite and report end-to-end runs that reach 95.65% average code coverage in 4.5 hours instead of several manual days. That combination of components is what lets the LLM stay protocol-correct without constant human rewriting, and the paper supplies enough concrete examples to show the flow actually works on those protocols.

Referee Report

2 major / 1 minor

Summary. The paper presents UVMarvel, an automated LLM-based framework for generating subsystem-level UVM testbenches from RTL designs. It introduces an Intermediate Representation (IR) and Bus Protocol Library to translate specifications for mainstream protocols (AXI, APB, AXI-Lite), plus a Signal Tracker and Verilog Patching Library to refine LLM-generated stimuli. The central claim is that this is the first such end-to-end automated system, delivering 95.65% average code coverage while reducing verification effort from multiple human days to a 4.5-hour run.

Significance. If the reported coverage and runtime results prove reproducible across a broader set of designs, the work could meaningfully address the verification bottleneck (cited as ~70% of IC effort) by reducing manual UVM coding and protocol expertise requirements. The engineering integration of IR, protocol libraries, and patching mechanisms offers a concrete, extensible template for LLM-assisted hardware verification that could accelerate subsystem-level sign-off in practice.

major comments (2)

[Abstract and evaluation section] The abstract and evaluation section report 95.65% average code coverage and a 4.5-hour automated runtime but supply no details on the number or identity of evaluated RTL subsystems, the specific LLMs and prompting strategies used, baseline comparisons against manual UVM flows or prior tools, or any quantification of LLM failure modes and required manual corrections. These omissions make the performance claims impossible to assess for generalizability or robustness.
[Section 3] Section 3 (pipeline description) presents the combination of IR, Bus Protocol Library, Signal Tracker, and Verilog Patching Library as sufficient to steer LLMs toward protocol-correct, high-coverage testbenches, yet provides no quantitative data on how often the LLM still produces incorrect protocol behavior or requires substantial human intervention for new designs outside the demonstrated AXI/APB/AXI-Lite cases.

minor comments (1)

[Evaluation section] The manuscript would benefit from a dedicated table listing the exact designs, protocols, and coverage metrics per case to support the reported average.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive feedback on our manuscript. We address each major comment below and will revise the paper to enhance the clarity and completeness of the reported results and methodology.

read point-by-point responses

Referee: [Abstract and evaluation section] The abstract and evaluation section report 95.65% average code coverage and a 4.5-hour automated runtime but supply no details on the number or identity of evaluated RTL subsystems, the specific LLMs and prompting strategies used, baseline comparisons against manual UVM flows or prior tools, or any quantification of LLM failure modes and required manual corrections. These omissions make the performance claims impossible to assess for generalizability or robustness.

Authors: We agree that the abstract and evaluation section would benefit from greater specificity to support assessment of generalizability. In the revised manuscript, we will expand these sections to detail the number and identities of the evaluated RTL subsystems (including their protocol configurations and complexity), the specific LLMs and versions employed, the prompting strategies used, and quantitative baseline comparisons to manual UVM development in terms of time and coverage achieved. We will also add a table or subsection quantifying LLM failure modes, such as protocol violations or incomplete stimuli, along with the frequency and nature of required manual corrections based on our experimental records. revision: yes
Referee: [Section 3] Section 3 (pipeline description) presents the combination of IR, Bus Protocol Library, Signal Tracker, and Verilog Patching Library as sufficient to steer LLMs toward protocol-correct, high-coverage testbenches, yet provides no quantitative data on how often the LLM still produces incorrect protocol behavior or requires substantial human intervention for new designs outside the demonstrated AXI/APB/AXI-Lite cases.

Authors: We acknowledge that Section 3 would be strengthened by quantitative evidence on robustness. We will revise the section to include data from our experiments on the frequency of incorrect protocol behavior generated by the LLM despite the IR, libraries, and trackers. This will encompass metrics on intervention rates for the demonstrated protocols. For new designs beyond AXI/APB/AXI-Lite, we will report additional case studies or extensions to quantify human intervention needs, highlighting both the framework's extensibility and any observed limitations. revision: yes

Circularity Check

0 steps flagged

No significant circularity

full rationale

The paper presents an engineering framework for LLM-assisted UVM testbench generation rather than a mathematical derivation chain. No equations, fitted parameters, or predictions that reduce to inputs by construction appear in the described pipeline (IR translation, Bus Protocol Library, Signal Tracker, Verilog Patching Library). Claims rest on empirical coverage results and runtime measurements from concrete AXI/APB/AXI-Lite examples; the components are introduced as design inputs, not derived outputs. No self-citation load-bearing steps or ansatz smuggling are present.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 4 invented entities

The central claim rests on the assumption that LLMs can be reliably steered by the introduced scaffolding components. No numerical free parameters are fitted. The main invented entities are the four new software modules that constitute the framework.

axioms (1)

domain assumption LLMs can generate syntactically and semantically correct UVM and Verilog code when provided with structured protocol information.
Invoked implicitly when the framework translates specifications into testbenches.

invented entities (4)

Intermediate Representation (IR) no independent evidence
purpose: Translate heterogeneous specifications into protocol-correct UVM testbenches
New translation layer introduced by the paper.
Bus Protocol Library no independent evidence
purpose: Provide protocol knowledge to ensure generated testbenches are correct
New library component described in the framework.
Signal Tracker no independent evidence
purpose: Guide LLM-based stimuli refinement by monitoring signals
New component for feedback to the LLM.
Verilog Patching Library no independent evidence
purpose: Automatically patch Verilog files during stimuli refinement
New patching mechanism introduced.

pith-pipeline@v0.9.0 · 5503 in / 1526 out tokens · 62655 ms · 2026-05-08T15:31:22.670963+00:00 · methodology

discussion (0)

Reference graph

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