TCM finds provably optimal DNN accelerator mappings by pruning the search space up to 32 orders of magnitude with a new dataplacement concept, delivering 1.2-6.5x better energy-delay-product in 17 seconds instead of hours.
12.3 A 48GHz BW 225mW/ch Linear Driver IC with Stacked Current-Reuse Architecture in 65nm CMOS for Beyond-400Gb/s Coherent Optical Transmitters
9 Pith papers cite this work. Polarity classification is still indexing.
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An event-camera system with active gaze control and contrast-maximization spin estimation achieves real-time performance in table tennis with 8.8% magnitude error, 6.4° axis error, 3 ms latency, and 750 Hz throughput.
CBM-Dual is the first silicon-proven 65-nm digital processor for a 1024-neuron chaotic Boltzmann machine that supports dual-mode simulated annealing and reservoir computing with 99% fewer operations and 59% less area via a custom scheduler and multiply splitting.
FFM finds optimal fused mappings for tensor accelerators over 10,000 times faster than prior mappers while cutting energy-delay product by up to 1.8x versus hand-tuned designs.
Multi-stage silicon retina on SCAMP-5 achieves 13% lower saliency prediction loss and 47% fewer events than standard DVS using a ~100k-parameter network.
DISCA achieves 3.59 TOPS/W per bit energy efficiency for matrix multiplication at 500 MHz in 180 nm CMOS using a compressed Bent-Pyramid stochastic format.
Experimental demonstration of self-coherent 32 Gbaud QAM reception over fiber distances using ROSS photonic accelerator and direct detection, with reported power savings potential.
Digital twin ecosystem for BLE PHY allows validation of crystal-free motes, achieving commercial BLE communication and -82 dBm receiver sensitivity.
Review of CMOS compatibility advantages and challenges for semiconductor spin qubits aimed at enabling large-scale fault-tolerant quantum computing.
citing papers explorer
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The Turbo-Charged Mapper: Fast and Optimal Mapping for Energy-efficient and Low-latency Accelerator Design
TCM finds provably optimal DNN accelerator mappings by pruning the search space up to 32 orders of magnitude with a new dataplacement concept, delivering 1.2-6.5x better energy-delay-product in 17 seconds instead of hours.
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Event-based Gaze Control System for Accurate Real-time Spin Estimation in Professional Ball Games
An event-camera system with active gaze control and contrast-maximization spin estimation achieves real-time performance in table tennis with 8.8% magnitude error, 6.4° axis error, 3 ms latency, and 750 Hz throughput.
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CBM-Dual: A 65-nm Fully Connected Chaotic Boltzmann Machine Processor for Dual Function Simulated Annealing and Reservoir Computing
CBM-Dual is the first silicon-proven 65-nm digital processor for a 1024-neuron chaotic Boltzmann machine that supports dual-mode simulated annealing and reservoir computing with 99% fewer operations and 59% less area via a custom scheduler and multiply splitting.
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Fast and Fusiest: An Optimal Fusion-Aware Mapper for Accelerator Design
FFM finds optimal fused mappings for tensor accelerators over 10,000 times faster than prior mappers while cutting energy-delay product by up to 1.8x versus hand-tuned designs.
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Programmable Silicon Retina on Pixel Processor Array
Multi-stage silicon retina on SCAMP-5 achieves 13% lower saliency prediction loss and 47% fewer events than standard DVS using a ~100k-parameter network.
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DISCA: A Digital In-memory Stochastic Computing Architecture Using A Compressed Bent-Pyramid Format
DISCA achieves 3.59 TOPS/W per bit energy efficiency for matrix multiplication at 500 MHz in 180 nm CMOS using a compressed Bent-Pyramid stochastic format.
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Experimental Analysis of a Self-Coherent M-QAM Receiver by Means of Recurrent Optical Spectrum Slicing and Direct Detection
Experimental demonstration of self-coherent 32 Gbaud QAM reception over fiber distances using ROSS photonic accelerator and direct detection, with reported power savings potential.
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A Digital Twin Platform Enabling Monolithic Crystal-Free Bluetooth Low Energy Single-Chip Sensor Motes
Digital twin ecosystem for BLE PHY allows validation of crystal-free motes, achieving commercial BLE communication and -82 dBm receiver sensitivity.
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CMOS compatibility of semiconductor spin qubits
Review of CMOS compatibility advantages and challenges for semiconductor spin qubits aimed at enabling large-scale fault-tolerant quantum computing.