Design and Implementation a 8 bits Pipeline Analog to Digital Converter in the Technology 0.6 \mu m CMOS Process

Dominique Ginhac; Eri Prasetyo; Michel Paindavoine

arxiv: 0808.0387 · v1 · pith:5CB57HX5 · submitted 2008-08-04 · cs.RO · cs.CV

Design and Implementation a 8 bits Pipeline Analog to Digital Converter in the Technology 0.6 μ m CMOS Process

Eri Prasetyo , Dominique Ginhac , Michel Paindavoine This is my paper

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classification cs.RO cs.CV

keywords pipelinebitscapacitorclockcmosconverterdesignmanagement

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This paper describes a 8 bits, 20 Msamples/s pipeline analog-to-digital converter implemented in 0.6 \mu m CMOS technology with a total power dissipation of 75.47 mW. Circuit techniques used include a precise comparator, operational amplifier and clock management. A switched capacitor is used to sample and multiplying at each stage. Simulation a worst case DNL and INL of 0.75 LSB. The design operate at 5 V dc. The ADC achieves a SNDR of 44.86 dB. keywords : pipeline, switched capacitor, clock management

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Design and Implementation a 8 bits Pipeline Analog to Digital Converter in the Technology 0.6 μ m CMOS Process

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