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arxiv 2301.12252 v1 pith:PW4CRYBQ submitted 2023-01-28 cs.AR cs.AIcs.LG

Machine Learning Accelerators in 2.5D Chiplet Platforms with Silicon Photonics

classification cs.AR cs.AIcs.LG
keywords acceleratorschipletplatformscomputationdesignhardwarelearningmachine
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved
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Domain-specific machine learning (ML) accelerators such as Google's TPU and Apple's Neural Engine now dominate CPUs and GPUs for energy-efficient ML processing. However, the evolution of electronic accelerators is facing fundamental limits due to the limited computation density of monolithic processing chips and the reliance on slow metallic interconnects. In this paper, we present a vision of how optical computation and communication can be integrated into 2.5D chiplet platforms to drive an entirely new class of sustainable and scalable ML hardware accelerators. We describe how cross-layer design and fabrication of optical devices, circuits, and architectures, and hardware/software codesign can help design efficient photonics-based 2.5D chiplet platforms to accelerate emerging ML workloads.

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