Not yet reviewed by Pith; the record is open.

Due to low power consumption and high-speed performance, superconductor circuit technology has emerged as an attractive and compelling post-CMOS technology candidate. However, the design of dense memory circuits presents a significant challenge, especially for tasks that demand substantial memory resources. While superconductor memory cells offer impressive speed, their limited density is the primary yet-to-be-solved challenge. This study tackles this challenge head-on by introducing a novel design for a Non-Destructive Readout (NDRO) memory unit with single or multi-fluxon storage capabilities within the same circuit architecture. Notably, single storage demonstrates a critical margin exceeding 20\%, and multi-fluxon storage demonstrates 64\%, ensuring reliable and robust operation even in the face of process variations. These memory units exhibit high clock frequencies of 10GHz. The proposed circuits offer compelling characteristics, including rapid data propagation and minimal data refreshment requirements, while effectively addressing the density concerns associated with superconductor memory, doubling the memory capacity while maintaining the high throughput speed.