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arxiv: 2507.23011 · v2 · submitted 2025-07-30 · 🪐 quant-ph

Placing and routing quantum LDPC codes in multilayer superconducting hardware

Melvin Mathews , Lukas Pahl , David Pahl , Vaishnavi L. Addala , Catherine Tang , William D. Oliver , Jeffrey A. Grover This is my paper

Pith reviewed 2026-05-19 02:06 UTC · model grok-4.3

classification 🪐 quant-ph
keywords quantum LDPC codeshardware layoutsuperconducting qubitsplacement and routingbivariate bicycle codesopen boundary codesfault tolerant quantum computing
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The pith

A hardware-aware algorithm produces explicit layouts for quantum LDPC codes, showing open boundaries reduce complexity with little efficiency loss.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper introduces HAL, a heuristic for placing and routing quantum low-density parity-check codes on multilayer superconducting hardware that supports long-range connections. It applies this to generate layouts for about 150 instances of codes including bivariate bicycle and tile codes. Removing periodic boundaries is shown to cut hardware demands substantially while only modestly affecting logical performance. This work indicates that advanced error-correcting codes with lower overheads can be implemented on upcoming quantum devices.

Core claim

Leveraging multilayer routing and long-range coupling in superconducting qubit hardware, the Hardware-Aware Layout (HAL) algorithm automates placement and routing for arbitrary quantum LDPC codes. For codes with topological structure such as bivariate bicycle codes and open-boundary tile codes, explicit layouts demonstrate that dropping periodic boundaries lowers hardware complexity with only a moderate reduction in logical efficiency. Similar competitive tradeoffs are achieved for highly nonlocal families like quantum radial and Tanner codes.

What carries the argument

HAL (Hardware-Aware Layout), a robust runtime-efficient heuristic algorithm that automates and optimizes the placement and routing of arbitrary quantum LDPC codes by utilizing multilayer routing and long-range coupling capabilities.

Load-bearing premise

The model assumes multilayer routing and long-range couplings can be realized without adding significant noise or hitting major fabrication limits.

What would settle it

Measuring the actual error rates in a fabricated superconducting device using one of the HAL-generated layouts and checking if they match predictions without extra noise from the routing layers.

Figures

Figures reproduced from arXiv: 2507.23011 by Catherine Tang, David Pahl, Jeffrey A. Grover, Lukas Pahl, Melvin Mathews, Vaishnavi L. Addala, William D. Oliver.

Figure 1
Figure 1. Figure 1: FIG. 1 [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: FIG. 2 [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: FIG. 3 [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: FIG. 4 [PITH_FULL_IMAGE:figures/full_fig_p007_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: FIG. 5 [PITH_FULL_IMAGE:figures/full_fig_p012_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: FIG. 6 [PITH_FULL_IMAGE:figures/full_fig_p014_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: FIG. 7. Hardware complexity of square grid and spring lay [PITH_FULL_IMAGE:figures/full_fig_p015_7.png] view at source ↗
read the original abstract

Quantum error-correcting codes with asymptotically lower overheads than the surface code require nonlocal connectivity. Leveraging multilayer routing and long-range coupling capabilities in superconducting qubit hardware, we develop Hardware-Aware Layout, HAL: a robust, runtime-efficient heuristic algorithm that automates and optimizes the placement and routing of arbitrary codes. Using HAL, we generate around 150 explicit layouts of quantum low-density parity-check (qLDPC) codes with topological structure -- such as the bivariate bicycle codes and the open-boundary tile codes -- and find that removing the periodic boundaries significantly lowers the hardware complexity with only a moderate reduction of logical efficiency. We also lay out highly nonlocal qLDPC code families -- quantum radial and Tanner codes -- that achieve competitive tradeoffs between hardware complexity and logical efficiency. Based on our findings, we anticipate many novel qLDPC codes to be realizable on near-term superconducting qubit hardware and inform future directions for the co-design of quantum devices and fault-tolerant architectures.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The manuscript introduces HAL, a runtime-efficient heuristic algorithm for automated placement and routing of arbitrary quantum LDPC codes on multilayer superconducting hardware that supports long-range couplings. Using HAL, the authors generate around 150 explicit layouts for topologically structured qLDPC codes (including bivariate bicycle codes and open-boundary tile codes) and report that open-boundary versions achieve significantly lower hardware complexity at the cost of only a moderate reduction in logical efficiency. The work also presents layouts for highly nonlocal families such as quantum radial and Tanner codes and concludes that many such codes should be realizable on near-term hardware.

Significance. If the hardware model is realistic, the concrete layouts and the periodic-versus-open-boundary comparison could usefully inform co-design of superconducting devices and fault-tolerant architectures. The heuristic's ability to handle arbitrary codes and produce explicit, multilayer routings is a practical contribution. However, the significance is limited by the absence of quantitative error bars, formal optimality guarantees, or measured hardware performance, and by the heuristic nature of the results.

major comments (2)
  1. [Hardware assumptions and HAL cost function] Hardware assumptions and HAL cost function (abstract and introduction): the logical-efficiency metric used to compare periodic-boundary and open-boundary layouts counts layers, wire lengths, and coupler ranges but does not propagate any additional error rates or yield penalties from long-range couplers or multilayer vias. If realistic superconducting hardware assigns even modest extra noise to these elements, the reported 'moderate reduction' in logical efficiency could become large enough to erase the claimed advantage of open-boundary layouts.
  2. [Results on layout generation] Results section on layout generation: the claim that removing periodic boundaries 'significantly lowers the hardware complexity with only a moderate reduction of logical efficiency' is supported only by heuristic outputs without quantitative error bars, sensitivity analysis to the cost-function weights, or comparison against an independent baseline optimizer.
minor comments (2)
  1. The manuscript should clarify whether the reported efficiency numbers are averaged over the 150 layouts or selected from best-case runs, and should include at least a brief discussion of runtime scaling with code size.
  2. Figure captions and text should explicitly state the precise definition of 'logical efficiency' and 'hardware complexity' used in the comparisons.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the detailed and constructive feedback on our manuscript. We appreciate the opportunity to clarify the hardware assumptions underlying our logical-efficiency metric and to strengthen the presentation of our heuristic results. Below we address each major comment point by point.

read point-by-point responses

  1. Referee: Hardware assumptions and HAL cost function (abstract and introduction): the logical-efficiency metric used to compare periodic-boundary and open-boundary layouts counts layers, wire lengths, and coupler ranges but does not propagate any additional error rates or yield penalties from long-range couplers or multilayer vias. If realistic superconducting hardware assigns even modest extra noise to these elements, the reported 'moderate reduction' in logical efficiency could become large enough to erase the claimed advantage of open-boundary layouts.

    Authors: We agree that incorporating explicit error rates or yield penalties from long-range couplers and multilayer vias would provide a more comprehensive assessment. Our logical-efficiency metric is designed as a hardware-complexity proxy based on the number of layers, total wire length, and maximum coupler range, which directly impact the feasibility of implementation on current and near-term superconducting platforms. The 'moderate reduction' refers to this complexity measure. To address this, we will revise the manuscript to include a dedicated discussion on how additional noise from these elements might affect the comparison, and note that detailed error modeling would require device-specific parameters not available in the current hardware-agnostic model. This addition will clarify the scope of our claims. revision: yes

  2. Referee: Results section on layout generation: the claim that removing periodic boundaries 'significantly lowers the hardware complexity with only a moderate reduction of logical efficiency' is supported only by heuristic outputs without quantitative error bars, sensitivity analysis to the cost-function weights, or comparison against an independent baseline optimizer.

    Authors: The results are indeed generated using the HAL heuristic, which is the core contribution for producing explicit layouts. We acknowledge the absence of error bars from multiple runs and sensitivity analysis in the current version. In the revision, we will add error bars by reporting statistics over multiple independent runs of HAL for representative codes, and include a sensitivity analysis varying the weights in the cost function to show robustness of the periodic vs. open-boundary comparison. Regarding comparison to an independent baseline optimizer, we note that the primary goal is to demonstrate that HAL can generate high-quality layouts for a variety of codes, rather than to prove optimality; however, we will add a brief comparison to a simple greedy placement baseline to provide additional context. revision: yes

Circularity Check

0 steps flagged

No circularity: results are direct algorithmic outputs under explicit assumptions

full rationale

The paper defines the HAL heuristic algorithm for placement and routing, then executes it to produce ~150 explicit layouts for qLDPC codes (bivariate bicycle, open-boundary tile, radial, Tanner). The reported comparisons of hardware complexity and logical efficiency between periodic and open-boundary versions are computational results from this execution inside a stated hardware model that counts layers, wire lengths, and coupler ranges. No equations or definitions reduce a claimed quantity to itself by construction, no parameters are fitted to a subset and then relabeled as predictions, and no load-bearing step relies on a self-citation whose content is unverified or imported as a uniqueness theorem. The central claims remain independent of the authors' prior work and rest on the algorithm's outputs plus the enumerated hardware assumptions.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The work rests on a hardware model that assumes multilayer routing and long-range couplers are feasible without major new noise sources. No free parameters or invented entities are described in the abstract.

axioms (1)
  • domain assumption Multilayer superconducting hardware supports long-range coupling with acceptable noise levels
    Invoked to justify the feasibility of the generated layouts (abstract).

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Forward citations

Cited by 5 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score.

  1. Mitigating Classical Resource Costs in Quantum Error Correction via Generalized qLDPC Predecoding

    quant-ph 2026-05 unverdicted novelty 7.0

    An automated predecoder generator for arbitrary qLDPC codes cuts decoder utilization by up to 3963x and supports hardware scaling to tens or hundreds of thousands of logical qubits within power limits.

  2. Breaking the scalability barrier via a vertical tunable coupler in 3D integrated transmon system

    quant-ph 2026-05 unverdicted novelty 6.0

    A 3D integrated transmon system achieves 99.87% single-qubit and 97.5% CZ gate fidelities with interchip entanglement, showing vertical tunable couplers enable scalable superconducting quantum processors.

  3. Distributed Quantum Error Correction with Bivariate Bicycle Codes in a Modular Architecture

    quant-ph 2026-05 unverdicted novelty 6.0

    The [[144,12,12]] bivariate bicycle code is distributed across 4 to 12 processors in a star network, with simulations showing logical error rates under varying nonlocal noise scaling.

  4. Efficient Routing of Quantum LDPC Codes on Programmable 2D Toric Architectures

    quant-ph 2026-04 unverdicted novelty 6.0

    A programmable 2D toric oscillator network enables efficient routing for bivariate bicycle LDPC codes, reducing long-range couplers to O(sqrt(n)) and achieving 3.06% logical error rate per cycle in simulations for the...

  5. Geometry-induced correlated noise in qLDPC syndrome extraction

    quant-ph 2026-04 conditional novelty 6.0

    Geometry choices in bivariate-bicycle qLDPC syndrome extraction determine leading correlated error structure via weighted exposure, which correlates strongly with logical error rates and is reduced by biplanar layouts.

Reference graph

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