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arxiv: 2605.29942 · v1 · pith:2WSMQR6Znew · submitted 2026-05-28 · ⚛️ physics.app-ph · eess.IV

Reconfigurable Multistate MRAM Synapses with Vortex STNO based Neurons for Scalable In-Memory Convolutional Neural Networks

Ravish Kumar Raj , Simon N. Richter , Saeed Baghaee Ivriq , Oliver Fridorf , Dar\'io Fern\'andez-Khatiboun , Yasser Rezaeiyan , Luana Benetti , Tim Boehnert
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Ricardo Ferreira Hooman Farkhani Sonal Shreya Farshad Moradi
This is my paper

Pith reviewed 2026-06-28 23:49 UTC · model grok-4.3

classification ⚛️ physics.app-ph eess.IV
keywords MRAMSTNOneuromorphic computingin-memory computingconvolutional neural networksspin torque nano-oscillatormagnetic tunnel junction
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The pith

A unified MRAM-STNO architecture places multistate synapses and vortex neurons on one chip for in-memory CNNs.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper establishes that 1x8 multistate MRAM arrays can serve as programmable synapses when paired with vortex-based STNO neurons, allowing fieldline-driven tuning of multiple resistance states for positive and negative weights. This setup supports kernel and pooling operations directly in hardware for convolutional neural networks. Simulations on five standard datasets produce the listed accuracies, with the full system projected to fit in roughly 6171 square microns and use 200 pJ per cycle for MNIST based on fabricated device sizes. A sympathetic reader would care because the approach merges non-volatile memory and computation in a CMOS-compatible platform, which could cut the power and latency costs of moving data between separate memory and processor units in edge AI hardware.

Core claim

The authors claim that the multistate MRAM-STNO architecture can be configured for quantized synaptic weights and neuron operation in CNNs, demonstrated through simulations achieving 99.76% accuracy on MNIST, 87.93% on SVHN, 78.14% on CIFAR-10, 87.96% on Google Speech Commands, and 56.46% on RadioML, with an area of approximately 6171.2 μm² and average energy of 200.08 pJ per cycle for MNIST.

What carries the argument

1x8 multistate MRAM arrays as programmable synapses coupled with a vortex-based STNO neuron, tuned by internal and external magnetic fields plus bias currents to produce configurable resistance states via fieldline-driven write channels.

Load-bearing premise

The device models used in simulation accurately capture the collective behavior, variability, and programming reliability of the full multistate MRAM-STNO array when scaled to a complete CNN accelerator.

What would settle it

Fabricate and measure a physical prototype of the complete architecture on the MNIST dataset to determine whether the simulated 99.76 percent accuracy and 200 pJ energy consumption are realized in actual hardware.

Figures

Figures reproduced from arXiv: 2605.29942 by Dar\'io Fern\'andez-Khatiboun, Farshad Moradi, Hooman Farkhani, Luana Benetti, Oliver Fridorf, Ravish Kumar Raj, Ricardo Ferreira, Saeed Baghaee Ivriq, Simon N. Richter, Sonal Shreya, Tim Boehnert, Yasser Rezaeiyan.

Figure 7
Figure 7. Figure 7: Normalized frequency and power responses of STNO as a function of normalized bias line current (a) Demonstrating the capability of the STNO frequency to emulate ReLU neuron activation function (b) Power maps to sigmoid, and softmax neuron activation function. (a) (b) (a) (b) [PITH_FULL_IMAGE:figures/full_fig_p013_7.png] view at source ↗
read the original abstract

Magnetic tunnel junction (MTJ)-based magnetic random-access memory (MRAM) is a promising platform for neuromorphic and in-memory computing owing to its non-volatility, high endurance, fast switching dynamics and CMOS compatibility. However, conventional spin-transfer torque and spin-orbit torque MRAM implementations for neural networks often suffer from high critical switching currents, large latency, thermal instability and significant read-write overheads. Here, we demonstrate a unified multistate MRAM-spin-torque nano-oscillator (STNO) architecture that integrates synapses and neurons on a single chip for convolutional neural network (CNN) applications. The system employs 1x8 multistate MRAM arrays as programmable synapses coupled with a vortex-based STNO neuron, enabling both individual and collective programming through fieldline-driven write channels. Multiple configurable resistance states are achieved by tuning internal and external magnetic fields together with bias currents, allowing quantized positive and negative synaptic weights for configurable kernel and pooling operations. The proposed architecture is evaluated through simulation on MNIST, SVHN, CIFAR-10, Google Speech Commands (GSC) and RadioML datasets, achieving accuracy of 99.76%, 87.93%, 78.14%, 87.96% and 56.46% respectively. Based on fabricated device dimensions, the complete architecture occupies ~6171.2 {\mu}m2 with an average energy consumption of 200.08 pJ per training and inference cycle for MNIST, highlighting its potential for scalable low-power neuromorphic computing

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The manuscript proposes a unified multistate MRAM-STNO architecture that integrates 1x8 multistate MRAM arrays as programmable synapses with vortex-based STNO neurons on a single chip for CNN applications. Multiple resistance states are achieved via fieldline-driven programming and magnetic field tuning to realize quantized positive/negative weights for kernels and pooling. The architecture is evaluated entirely through simulation on MNIST, SVHN, CIFAR-10, GSC, and RadioML, reporting accuracies of 99.76%, 87.93%, 78.14%, 87.96%, and 56.46%, respectively, together with an area of ~6171.2 μm² and average energy of 200.08 pJ per training/inference cycle for MNIST, using dimensions from fabricated devices.

Significance. If the compact models prove accurate, the work offers a concrete route to non-volatile, CMOS-compatible in-memory CNN accelerators with low energy per operation. The grounding of area/energy projections in fabricated device dimensions is a positive feature that strengthens the quantitative claims relative to purely hypothetical scaling studies.

major comments (2)
  1. [Abstract] Abstract: All reported accuracies and the 200.08 pJ energy figure rest on simulation outputs from compact models of the 1x8 MRAM-STNO array; no measured data from a fabricated multistate array embedded in a CNN datapath are supplied to confirm switching thresholds, state retention, or inter-device variability, directly undermining the headline performance numbers.
  2. [Abstract] Abstract: The assertion of a 'scalable' architecture is supported only by the 1x8 array simulations; the manuscript does not quantify how thermal stability, fieldline crosstalk, or programming reliability would degrade when the same models are instantiated at the scale required for the CIFAR-10 or RadioML networks.
minor comments (1)
  1. The abstract would be clearer if it named the simulation platform and the source of the compact models (e.g., whether they are calibrated to the authors' own fabricated devices or taken from literature).

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive comments on our manuscript. We address each major comment point by point below.

read point-by-point responses

  1. Referee: [Abstract] Abstract: All reported accuracies and the 200.08 pJ energy figure rest on simulation outputs from compact models of the 1x8 MRAM-STNO array; no measured data from a fabricated multistate array embedded in a CNN datapath are supplied to confirm switching thresholds, state retention, or inter-device variability, directly undermining the headline performance numbers.

    Authors: We acknowledge that all quantitative results, including accuracies and energy figures, are obtained from simulations using compact models calibrated to parameters extracted from fabricated MRAM and STNO devices. The manuscript does not present new experimental measurements from a complete integrated multistate array within a CNN datapath, as the contribution centers on the architectural proposal and its simulation-based evaluation. We have revised the abstract to explicitly qualify the results as simulation outputs to prevent misinterpretation. revision: yes

  2. Referee: [Abstract] Abstract: The assertion of a 'scalable' architecture is supported only by the 1x8 array simulations; the manuscript does not quantify how thermal stability, fieldline crosstalk, or programming reliability would degrade when the same models are instantiated at the scale required for the CIFAR-10 or RadioML networks.

    Authors: The 1x8 array serves as the repeatable synaptic building block, and the larger networks (including CIFAR-10 and RadioML) are simulated by composing multiple instances of this unit under the same compact models. The manuscript does not provide a quantitative scaling study of effects such as fieldline crosstalk or thermal stability degradation at full network scale. We have added a brief discussion section addressing these considerations and the design choices intended to support scalability. revision: partial

Circularity Check

0 steps flagged

No circularity: simulation outputs reported directly from device models without fitted predictions or self-referential derivations

full rationale

The paper presents a hardware architecture for MRAM-STNO based CNN synapses and neurons, then reports simulation accuracies (99.76% MNIST etc.) and area/energy figures obtained from those simulations. No equations, parameter-fitting steps, uniqueness theorems, or ansatzes are described that reduce a claimed prediction back to the input data or to a self-citation. The central results are therefore simulation outputs whose validity rests on external model fidelity rather than on any internal definitional loop.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

Abstract-only review supplies no equations, fitted parameters, or postulated entities; the central claim rests on the unstated assumption that simulation models match fabricated-device behavior at system scale.

pith-pipeline@v0.9.1-grok · 5875 in / 1127 out tokens · 26336 ms · 2026-06-28T23:49:05.446855+00:00 · methodology

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