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arxiv: 2606.07159 · v1 · pith:WXTNUJJBnew · submitted 2026-06-05 · 💻 cs.ET · cs.AR

Distributed Persistence Domain for Persistent Memory Pooling

Khan Shaikhul Hadi , Andres David Delgado , Naveed Ul Mustafa , Mark Heinrich , Hao Zheng , Yan Solihin This is my paper

Pith reviewed 2026-06-27 20:06 UTC · model grok-4.3

classification 💻 cs.ET cs.AR
keywords CXLpersistent memorymemory poolingpersistence domaincrash consistencydisaggregated memoryCXL switch
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0 comments X

The pith

Distributed persistence domains let CXL switches support pooled persistent memory with lower latency while preserving crash consistency.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

CXL memory pooling promises better resource use for persistent memory but creates high persist latency because operations must cross switches, links, and protocol layers. The paper introduces the Distributed Persistence Domain abstraction to formalize the correctness hazards that appear when persistence moves out of a single centralized point into the network fabric. From that analysis the authors extract design requirements and build a Persistent CXL Switch that shortens persist paths, forwards reads, and coalesces writes. Cycle-accurate simulations on SPLASH-4 and YCSB workloads show an average 33 percent speedup over baseline volatile switches and up to 36 percent when read forwarding is active.

Core claim

The Distributed Persistence Domain abstraction formalizes the hazards of distributed persistence in CXL fabrics and supplies the minimal requirements that let a Persistent CXL Switch reduce persist latency, enable read forwarding, and coalesce writes while still guaranteeing crash consistency.

What carries the argument

The Distributed Persistence Domain (DPD) abstraction, which identifies stale-read and stale-write hazards and derives the coordination rules needed when persistence logic is placed inside CXL switches.

If this is right

  • Persist operations no longer traverse the full CXL fabric, directly lowering latency.
  • Read forwarding at the switch becomes safe under the stated coordination rules.
  • Writes can be coalesced at the switch without violating persistence ordering.
  • Average performance improves 33 percent over volatile CXL switches across the evaluated workloads.
  • Crash consistency holds even though persistence logic is no longer centralized.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same hazard-analysis approach could be applied to other disaggregated interconnects that want to move persistence closer to memory.
  • Real silicon would still need to confirm that no protocol-level corner cases exist beyond those captured in the simulation model.
  • The design opens the possibility of larger-scale persistent memory pools whose size is no longer limited by centralized persistence-domain latency.

Load-bearing premise

The design requirements derived from the DPD analysis are sufficient to guarantee correctness and crash consistency when persistence support is moved into distributed CXL switches, without introducing unmodeled hazards or overheads in real hardware deployments.

What would settle it

A workload run or crash-recovery test that produces a stale read or write in the Persistent CXL Switch would show that the derived requirements do not fully preserve consistency.

Figures

Figures reproduced from arXiv: 2606.07159 by Andres David Delgado, Hao Zheng, Khan Shaikhul Hadi, Mark Heinrich, Naveed Ul Mustafa, Yan Solihin.

Figure 1
Figure 1. Figure 1: (a) Persistent memory pooling using volatile CXL [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: (a) Persistent write and read in volatile CXL persis [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Normalized execu [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Data correctness concern for persistent memory [PITH_FULL_IMAGE:figures/full_fig_p004_4.png] view at source ↗
Figure 3
Figure 3. Figure 3: This holds significant promise for scaling performance in [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figure 5
Figure 5. Figure 5: CXL-based disaggregated persistent memory. System has multiple persist structures and multiple hosts that inject [PITH_FULL_IMAGE:figures/full_fig_p005_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Hardware component of persist buffer design. PBC Selector (c) resides in the main control logic, while Persist Buffer [PITH_FULL_IMAGE:figures/full_fig_p005_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: When migrating a process to a new compute node, [PITH_FULL_IMAGE:figures/full_fig_p007_7.png] view at source ↗
Figure 9
Figure 9. Figure 9: Commit stall breakdown for SPLASH-4 and YCSB [PITH_FULL_IMAGE:figures/full_fig_p009_9.png] view at source ↗
Figure 12
Figure 12. Figure 12: Percentage of write coalesce at PCS. BARNESCHOLESKY FFT LU_CONT LU_NON RAYTRACEVOLREND VOLREND_NPL A B C D F 0 20 40 60 80 Drain Threshold (%) DPD_Lazy Adaptive_CP [PITH_FULL_IMAGE:figures/full_fig_p010_12.png] view at source ↗
Figure 13
Figure 13. Figure 13: Average drain threshold across different scheme. [PITH_FULL_IMAGE:figures/full_fig_p010_13.png] view at source ↗
Figure 14
Figure 14. Figure 14: Speedup for Splash-4 benchmarks in DPD for dif [PITH_FULL_IMAGE:figures/full_fig_p011_14.png] view at source ↗
read the original abstract

Compute Express Link (CXL) enables memory pooling over disaggregated memory, offering the potential to improve resource utilization in persistent memory systems. However, integrating persistence semantics into CXL-based memory pooling introduces substantial latency, which limits system scalability. This overhead arises because persist operations must traverse the entire CXL fabric, including switches, links, and protocol layers, before reaching remote persistent memory. To this end, we argue that extending CXL switches with persistence support is a promising direction for improving the scalability of persistent memory pooling. However, moving persistence support into the network breaks the traditional correctness assumptions of centralized persistence domains. In particular, enabling persistence within distributed structures, such as CXL switches, can introduce stale reads and writes if not carefully coordinated. In this paper, we propose Distributed Persistence Domain (DPD), a new abstraction for persistent memory pooling that enables persistence support at the CXL switch level. We first formalize the concept of a distributed persistence domain and use DPD as a framework to identify the correctness hazards that arise when persistence structures are distributed across the CXL fabric. Based on this analysis, we derive the design requirements needed to guarantee correctness. Building on these insights, we present Persistent CXL Switch, a CXL switch architecture that incorporates persistence support to significantly reduce persist latency, enable read forwarding, and coalesce writes, while preserving correctness and crash consistency. We evaluated our system design using both SPLASH-4 and YCSB benchmarks. Simulation results show an average speedup of 33% over volatile CXL switches, and up to 36% speedup with read forwarding optimization across all workloads.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

1 major / 1 minor

Summary. The paper introduces the Distributed Persistence Domain (DPD) abstraction for CXL-based persistent memory pooling. It formalizes DPD to identify correctness hazards such as stale reads and writes when persistence is distributed across CXL switches, derives design requirements from this analysis, and proposes the Persistent CXL Switch architecture that incorporates persistence support to reduce persist latency, enable read forwarding, and coalesce writes while maintaining crash consistency. Evaluation using SPLASH-4 and YCSB benchmarks in simulation shows an average 33% speedup over volatile CXL switches, with up to 36% with read forwarding.

Significance. If the DPD framework accurately captures all distributed persistence hazards and the Persistent CXL Switch design satisfies the derived requirements without unmodeled issues, this work could significantly improve the scalability and performance of persistent memory systems over CXL fabrics by moving persistence logic closer to the network. The simulation results provide initial evidence of performance benefits, though the absence of correctness validation in the reported experiments limits the strength of the claims.

major comments (1)
  1. [Abstract and Evaluation] Abstract and Evaluation: The simulation results report only performance speedups (average 33%, up to 36% with read forwarding) but contain no description of experiments that exercise or validate crash consistency against the stale read/write hazards identified by the DPD analysis. Because the central claim is that the Persistent CXL Switch preserves correctness while delivering these gains, the lack of any reported failure-mode testing or hazard-mitigation verification is a load-bearing gap.
minor comments (1)
  1. [Abstract] Abstract: Workload coverage, number of runs, and presence/absence of error bars or variance measures are not stated, making it difficult to assess the robustness of the reported speedups.

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for the constructive feedback. The observation regarding the lack of explicit crash-consistency validation is valid and we address it directly below.

read point-by-point responses

  1. Referee: [Abstract and Evaluation] Abstract and Evaluation: The simulation results report only performance speedups (average 33%, up to 36% with read forwarding) but contain no description of experiments that exercise or validate crash consistency against the stale read/write hazards identified by the DPD analysis. Because the central claim is that the Persistent CXL Switch preserves correctness while delivering these gains, the lack of any reported failure-mode testing or hazard-mitigation verification is a load-bearing gap.

    Authors: We agree that the current evaluation section reports only performance results and does not describe dedicated experiments that inject the stale-read and stale-write hazards identified by the DPD analysis. The manuscript argues correctness by construction: the DPD formalization enumerates the hazards, derives the minimal requirements (atomic persistence ordering, forwarding coherence, and write coalescing under crash), and the Persistent CXL Switch is shown to satisfy each requirement through its protocol extensions. Nevertheless, we acknowledge that an explicit verification campaign would strengthen the central claim. In the revised manuscript we will add a new subsection (Evaluation: Correctness Validation) that describes targeted simulation experiments: (1) controlled injection of link delays and switch failures to trigger potential stale reads, (2) concurrent persist and read workloads that could produce stale writes, and (3) post-crash recovery checks confirming that no hazard manifests when the design invariants hold. These experiments will be run on the same SPLASH-4 and YCSB workloads plus micro-benchmarks crafted to stress the identified corner cases. We will also clarify in the abstract and introduction that correctness is established both analytically via DPD and empirically via the new validation suite. revision: yes

Circularity Check

0 steps flagged

No circularity; design derives from independent hazard analysis without reduction to inputs or self-citations.

full rationale

The paper formalizes DPD to identify hazards (stale reads/writes) when distributing persistence, derives requirements for correctness/crash consistency, and proposes Persistent CXL Switch to satisfy them, with simulation results for performance. No equations, fitted parameters, or self-citations appear in the provided text; the chain is a standard analysis-to-requirements-to-design flow that does not reduce by construction to its own inputs. The correctness claim rests on the sufficiency of derived requirements rather than any enumerated circular pattern.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 2 invented entities

The central claim rests on the newly introduced DPD abstraction and switch architecture; no free parameters or external axioms are detailed in the abstract, but the work postulates that distributed persistence can be made correct via derived requirements.

invented entities (2)
  • Distributed Persistence Domain (DPD) no independent evidence
    purpose: New abstraction to formalize correctness hazards when persistence support is distributed across CXL fabric
    Introduced to identify hazards like stale reads/writes and derive design requirements
  • Persistent CXL Switch no independent evidence
    purpose: CXL switch architecture incorporating persistence support, read forwarding, and write coalescing
    Presented as the concrete implementation that reduces latency while preserving correctness

pith-pipeline@v0.9.1-grok · 5832 in / 1284 out tokens · 21301 ms · 2026-06-27T20:06:32.924099+00:00 · methodology

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