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Detecting silent data corruptions in the wild

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arxiv 2203.08989 v1 pith:BV72WATV submitted 2022-03-16 cs.AR cs.DCcs.SE

classification cs.ARcs.DCcs.SE
keywords silentdataerrorstestingcorruptionsdefectacrosscausing
verification ladder T0 review T1 audit T2 compute T3 formal

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Silent Errors within hardware devices occur when an internal defect manifests in a part of the circuit which does not have check logic to detect the incorrect circuit operation. The results of such a defect can range from flipping a single bit in a single data value, up to causing the software to execute the wrong instructions. Silent data corruptions (SDC) in hardware impact computational integrity for large-scale applications. Manifestations of silent errors are accelerated by datapath variations, temperature variance, and age, among other silicon factors. These errors do not leave any record or trace in system logs. As a result, silent errors stay undetected within workloads, and their effects can propagate across several services, causing problems to appear in systems far removed from the original defect. In this paper, we describe testing strategies to detect silent data corruptions within a large scale infrastructure. Given the challenging nature of the problem, we experimented with different methods for detection and mitigation. We compare and contrast two such approaches - 1. Fleetscanner (out-of-production testing) and 2. Ripple (in-production testing).We evaluate the infrastructure tradeoffs associated with the silicon testing funnel across 3+ years of production experience.

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Cited by 2 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. Ralts: Robust Aggregation for Enhancing Graph Neural Network Resilience on Bit-flip Errors

    cs.LG 2025-07 conditional novelty 6.0 of 10

    The authors introduce distribution-based, dynamic-weight, and cosine-similarity aggregation to make message-passing GNNs resilient to bit-flip errors, reporting accuracy improvements of 10 to 44 percent over existing ...

  2. Algorithmic Strategies for Sustainable Reuse of Neural Network Accelerators with Permanent Faults

    cs.LG 2024-12 conditional novelty 6.0 of 10

    Fault-aware scaling, tile reordering, and fine-tuning restore near-original accuracy for many single stuck-at-bit faults in systolic-array neural network accelerators, in simulation.

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