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CXLMemSim: A pure software simulated CXL.mem for performance characterization

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arxiv 2303.06153 v2 pith:C3WNMQXF submitted 2023-03-10 cs.PF cs.ARcs.OS

classification cs.PFcs.ARcs.OS
keywords memorycxlmemsimhardwareperformancelatencybandwidthcharacterizationdisaggregation
verification ladder T0 review T1 audit T2 compute T3 formal
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CXLMemSim is a fast, lightweight simulation framework that enables performance characterization of memory systems based on Compute Express Link (CXL) .mem technology. CXL.mem allows disaggregation and pooling of memory to mitigate memory stranding (underutilized memory trapped on fully loaded servers) in cloud and datacenter environments. However, CXL-attached memory introduces additional latency and bandwidth constraints compared to local DRAM, and real CXL .mem hardware is not yet widely available for empirical evaluation. CXLMemSim addresses this gap by attaching to unmodified applications and simulating CXL-based memory pools in software. It operates by tracing memory allocations and accesses using efficient kernel probes and hardware performance counters, dividing execution into epochs, and injecting timing delays to emulate various CXL .mem latency/bandwidth characteristics. This approach incurs modest runtime overhead while preserving realistic load/store memory access patterns. We implement CXLMemSim on commodity hardware without special devices, and our evaluation shows that it runs orders of magnitude faster than cycle-accurate simulators (e.g., Gem5) for real-world workloads, while accurately modeling the performance impact of CXL .mem. We demonstrate use cases where CXLMemSim enables experimentation with memory pooling configurations, scheduling policies, data migration strategies, and caching techniques that were previously infeasible to evaluate at scale. Key findings include the viability of software-based CXL .mem emulation with low overhead, insights into latency and congestion effects in memory pools, and guidance for system designers to optimize memory disaggregation. Overall, CXLMemSim provides a practical and extensible platform for researchers and practitioners to explore CXL.mem innovations before real hardware becomes commonplace.

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Cited by 3 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. DMG: A Scalable and Efficient Memory-Disaggregated Graph Processing System

    cs.DB 2026-07 conditional novelty 7.0 of 10

    DMG makes graph processing on disaggregated memory practical by combining a DM-friendly graph store, adaptive update propagation, and fast two-stage load balancing, scaling to multiple compute/memory nodes with small caches.

  2. CXL-Interference: Analysis and Characterization in Modern Computer Systems

    cs.AR 2024-11 conditional novelty 6.0 of 10

    CXL memory traffic, especially non-temporal stores, can degrade concurrent DRAM and SSD bandwidth by up to 93.2%, and CPU quota or MBA regulation can restore about 99% of DRAM bandwidth.

  3. A Novel Extensible Simulation Framework for CXL-Enabled Systems

    cs.AR 2024-11 conditional novelty 6.0 of 10

    ESF is a new open-source CXL simulator that models CXL 3.1 features and is validated against a real CXL 2.0 memory expander.

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