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LoAS: Fully Temporal-Parallel Dataflow for Dual-Sparse Spiking Neural Networks

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arxiv 2407.14073 v3 pith:NNK567Z3 submitted 2024-07-19 cs.AR cs.AIcs.NE

classification cs.ARcs.AIcs.NE
keywords dual-sparsesnnsdataflowacceleratorsefficiencyloasnetworksneural
verification ladder T0 review T1 audit T2 compute T3 formal

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abstract

Spiking Neural Networks (SNNs) have gained significant research attention in the last decade due to their potential to drive resource-constrained edge devices. Though existing SNN accelerators offer high efficiency in processing sparse spikes with dense weights, opportunities are less explored in SNNs with sparse weights, i.e., dual-sparsity. In this work, we study the acceleration of dual-sparse SNNs, focusing on their core operation, sparse-matrix-sparse-matrix multiplication (spMspM). We observe that naively running a dual-sparse SNN on existing spMspM accelerators designed for dual-sparse Artificial Neural Networks (ANNs) exhibits sub-optimal efficiency. The main challenge is that processing timesteps, a natural property of SNNs, introduces an extra loop to ANN spMspM, leading to longer latency and more memory traffic. To address the problem, we propose a fully temporal-parallel (FTP) dataflow, which minimizes both data movement across timesteps and the end-to-end latency of dual-sparse SNNs. To maximize the efficiency of FTP dataflow, we propose an FTP-friendly spike compression mechanism that efficiently compresses single-bit spikes and ensures contiguous memory access. We further propose an FTP-friendly inner-join circuit that can lower the cost of the expensive prefix-sum circuits with almost no throughput penalty. All the above techniques for FTP dataflow are encapsulated in LoAS, a Low-latency inference Accelerator for dual-sparse SNNs. With FTP dataflow, compression, and inner-join, running dual-sparse SNN workloads on LoAS demonstrates significant speedup (up to $8.51\times$) and energy reduction (up to $3.68\times$) compared to running it on prior dual-sparse accelerators.

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Cited by 1 Pith paper

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  1. Towards 3D Acceleration for low-power Mixture-of-Experts and Multi-Head Attention Spiking Transformers

    cs.NE 2024-12 conditional novelty 5.0 of 10

    A 3D-stacked accelerator for spiking mixture-of-experts transformers reduces chip area by 39-41% and power by up to 14.4% versus a comparable 2D design.

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