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Integrated probabilistic computer using voltage-controlled magnetic tunnel junctions as its entropy source

T0 review · 3 major / 5 minor · reviewed 2026-08-11 · deepseek-v4-flash

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Pith's one-line read An ASIC with 1,143 probabilistic bits, fed by voltage-controlled magnetic tunnel junctions, solves integer factorization and projects to millions of p-bits.

desk verdict Real fabricated probabilistic ASIC driven by V-MTJ entropy, but the raw-bit bias gap keeps the result conditional. read the letter →

arxiv 2412.08017 v1 pith:EWAJRIBP submitted 2024-12-11 physics.app-ph cond-mat.dis-nn

Christian Duffee , Jordan Athas , Yixin Shao , Noraica Davila Melendez , Eleonora Raimondo , Jordan A. Katine , Kerem Y. Camsari , Giovanni Finocchio
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Pedram Khalili Amiri
This is my paper · ORCID
classification physics.app-phcond-mat.dis-nn
keywords probabilisticIsingmachinep-bitsvoltage-controlledmagneticanisotropytunneljunctiontruerandomnumbergeneratorintegerfactorizationinvertiblelogicCMOSASIC
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper demonstrates a fabricated 130 nm ASIC that implements a probabilistic Ising machine for integer factorization using 1,143 probabilistic bits, with random bits supplied by a voltage-controlled magnetic tunnel junction (V-MTJ) rather than a software or CMOS random number generator. The V-MTJ is thermally stable at rest and produces a random bit on demand when a 10 ns voltage pulse temporarily collapses its energy barrier. The authors show that the combined system solves 6-bit factorization problems, with the two correct factor pairs appearing in 67.5% of trials, and they argue that co-designing CMOS with V-MTJ entropy sources overcomes a key scaling bottleneck. If the approach scales as projected, it offers a path to single-chip probabilistic computers with millions of p-bits for hard combinatorial optimization.

What carries the argument

The load-bearing mechanism has three parts: the p-bit update rule $m_i(t+1)=\mathrm{sgn}[\tanh(I_i/T)+r]$ with $I_i = h_i + \sum_j J_{ij} m_j$, implemented digitally by a probabilistic logic unit (PLU) that maps 16 random bits to a sample from a scaled hyperbolic-arctangent distribution; the V-MTJ entropy source, where the voltage-controlled magnetic anisotropy effect lowers the energy barrier so the free layer relaxes in-plane and then re-enters one of two perpendicular states at random when the 10 ns pulse ends; and invertible logic gates built from AND, half-adder, and full-adder p-bit networks, whose ground states are the valid truth-table entries and which run equally well forward (multiplication), backward (factorization), or in division mode.

What would settle it

Feed the same 6-bit factorization trials with the V-MTJ's raw bit stream and with its XOR4-processed stream, and compare the solution distributions: if the raw-stream success rate drops below the paper's measured 67.5% or the energy minima no longer match the correct factors, the raw entropy quality is insufficient.

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Extended reading notes

Core claim

The central discovery is a working hybrid probabilistic computer in which a custom CMOS ASIC and a spintronic entropy source are co-designed: the ASIC implements 1,143 p-bits whose update rule samples the distribution of an Ising Hamiltonian, and a single voltage-controlled MTJ, driven by 10 ns pulses, provides the stochastic bits that make the p-bits random. Because the V-MTJ is engineered with a high standby energy barrier and switches randomly only while the voltage pulse is applied, it can generate random bits on demand at high speed without the fine-tuned low-barrier devices required by stochastic-MTJ approaches. The authors validate the system on 6-bit integer factorization, report simulated 20-bit factorization, and estimate that porting the design to 45 nm and 7 nm nodes yields dense factorizers whose area scales toward millions of integrated p-bits.

Load-bearing premise

The raw, un-XORed V-MTJ bit stream, which fails most NIST randomness tests, still provides random bits of sufficient quality for the p-bit update rule to sample the correct distribution.

Editorial extensions

If this is right

  • If the approach scales as projected, a single CMOS+V-MTJ chip could host millions of probabilistic bits, making Ising-machine solvers dense enough for practical combinatorial optimization problems.
  • Using several V-MTJs in parallel would move the throughput bottleneck from the entropy source to the CMOS logic, since p-bits can be updated in parallel with only modest area overhead.
  • The same invertible-logic architecture can perform multiplication and division as well as factorization, since the J matrix and h vector are fixed for a given bit width and only the clamped variables change.
  • V-MTJ entropy sources remove the need for the small, finely tuned energy barriers of stochastic MTJs, which should improve device-to-device uniformity and manufacturability in large arrays.
  • The synchronous ASIC approach consumes far less energy per random bit than FPGA or microcontroller implementations, per the comparison table.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • A direct experimental check would feed the same ASIC with XOR4-processed bits and compare success rates; the paper's argument depends on raw bits being adequate even though only the XORed stream passes NIST tests.
  • The single demonstrated 6-bit problem (35 = 5 × 7) is one instance; a broader sample of semiprimes would separate architecture capability from instance-specific luck.
  • The area projections ignore PLU and random-number-generator area in serial designs; the authors acknowledge this, but for parallel-update designs the added area is nontrivial (12–18% in their estimates), so the 'millions of p-bits' figure is an upper bound for serial operation.
  • The V-MTJ is currently external and wire-bonded; until monolithic integration is shown, the claimed path to millions of p-bits rests on fabrication assumptions rather than measured results.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. The manuscript reports a 130 nm CMOS ASIC implementing 1143 probabilistic bits for integer factorization, driven by a voltage-controlled MTJ (V-MTJ) entropy source that generates random bits on demand via the voltage-controlled magnetic anisotropy effect. The authors show that the experimental system factors the number 35 in 8192 iterations, with 67.5% of final states being the two valid factor pairs, and present NIST randomness results for the V-MTJ bit stream, which passes all 11 tests only after two XOR4 stages. They also simulate a 20-bit factorization using a modified design not implemented on the current chip, and they use synthesized 45 nm and 7 nm designs plus assumed V-MTJ cell areas to project scalability toward millions of p-bits.

Significance. If the entropy-quality gap is closed, this is a meaningful integration step: it is, to my knowledge, the first fabricated ASIC-level probabilistic Ising machine co-designed with an MTJ entropy source, and the paper includes concrete engineering details such as a synchronous p-bit architecture, a 30 nm V-MTJ, a comparison table with prior CMOS+MTJ platforms, and a measured 6-bit factorization. The authors are candid about the I/O bottleneck and about the distinction between measured and projected performance. However, the experimental support for the central claim is narrow: one V-MTJ, one factorization instance, and no repeated trials, while the entropy source as used during the factorization did not pass NIST randomness tests. The scaling projections are clearly labeled as projections but rest on assumed cell sizes and synthetic PDK densities.

major comments (3)
  1. [Methods, Table E1; §V, Fig. 6d] The ASIC received raw V-MTJ bits, not the XOR4-processed stream, yet only the XOR4 stream passes NIST STS (11/11 vs. 2/11 for raw). Because Eq. (1) draws r from a uniform distribution on (-1,1), a biased or correlated raw stream changes the effective update distribution implemented by the PLU. The single 67.5%-plurality histogram for the factorization of 35 therefore does not establish that the V-MTJ supplied entropy of adequate quality. Please report the bias, autocorrelation, and drift of the bit sequence actually delivered to the ASIC during factorization runs, compare results with and without XOR post-processing, and show either that the raw-stream statistics are adequate or that the update rule is robust to the measured deviations.
  2. [§V, Fig. 6d; Table 1] The experimental evidence is one V-MTJ device, one problem instance (35), and one 8192-iteration annealing run. The reported 67.5% valid-state rate is a plurality without error bars or a statistical significance test, and it does not distinguish a correctly sampling Ising machine from a weakly stochastic or biased annealer. Please add repeated independent trials, multiple devices, and a statistical comparison (e.g., bootstrap or chi-square) of the experimental state distribution against the simulated distribution for the same J and h.
  3. [Sec. IV; Eq. (1)] The text states that the PLU circuit 'sampled from the energy distribution of the Ising Hamiltonian defined by the J matrix and h vector' (Sec. IV). This is a distributional claim, but only the ground-state histogram of one factorization problem is shown. At fixed temperature the p-bit state distribution should be compared with the Boltzmann distribution of the implemented J/h for a small instance; without that check, the experimental data support only the weaker claim that the network reaches the low-energy states.
minor comments (5)
  1. [Abstract; Sec. I] There are typographical spacing errors ('large number s' in the abstract, 's of' in Sec. I); please proofread the manuscript.
  2. [Fig. 6] Figures 6b–6d would be more useful if the captions gave the total number of trials and the exact percentage for each reported plurality or majority.
  3. [Methods, Table E1] The description of the XOR post-processing is ambiguous: please state the stream length after each stage and clarify whether XOR4 consumes four original bits or two XOR2 outputs.
  4. [Data availability] The data availability statement should be more specific; raw V-MTJ bitstreams and per-trial factorization outcomes are needed to assess the statistical claims.
  5. [References] Reference [39] does not appear to be cited in the body text; please check the citation numbering.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the factorization demonstration and scaling projections are measured or explicitly assumed, not derived from their own conclusions.

full rationale

The paper's central demonstration is an experimental measurement: a fabricated 130 nm ASIC implementing 1143 p-bits, driven by random bits from a measured V-MTJ, solves a 6-bit factorization of 35 with 67.5% valid final states. The mapping from factorization to the Ising J/h matrices uses standard invertible-logic constructions, and the update rule in Eq. 1 is the standard p-bit update implemented by a LUT-based PLU. The entropy source is characterized against the external NIST STS benchmark, and the paper transparently reports that raw bits passed only 2/11 tests while XOR4-processed bits passed all 11, and that the ASIC received raw un-XORed bits. This is a validation gap, not a circular derivation: nothing in the experimental success is defined in terms of the success itself, and no parameter is fitted to force the factorization result. The J and h matrices are constructed so that ground states correspond to valid factor pairs, but the observed convergence of the physical system to those states is a nontrivial dynamical result, not a tautology. The scaling projections to 45 nm and 7 nm are explicitly based on synthesized cell densities and an assumed 50 F2 V-MTJ cell area, with no data fitted to produce a predetermined 'millions of p-bits' number. Self-citations to prior group work attribute device-stack choices and invertible-logic methodology, but the present work independently measures its V-MTJ, fabricates the ASIC, and reports raw measurement statistics; these citations are not load-bearing. The paper is therefore self-contained against external benchmarks and exhibits no circular step that reduces a prediction to its input by construction.

Assumptions & free parameters 4 free parameters · 4 assumptions · 0 invented entities

The central demonstration leans on established p-bit and VCMA physics, plus two untested extrapolation assumptions (raw bit adequacy and manufacturable advanced-node scaling). The tuning parameters are the annealing schedule and the applied field, both selected to make the system perform. No new physical entities are introduced.

free parameters (4)
  • Annealing start and end temperatures (6-bit experiment) = 1.375 (start), 0.8 (end)
    Chosen via a simulated parameter sweep over 6-bit factorization instances (Fig. 6a); the same values are used for the experimental trials. This is a tuned operating point, not a derived constant.
  • Annealing start and end temperatures (20-bit simulated) = 20 (start), 4 (end)
    Set for the modified 20-bit factorizer simulation to demonstrate convergence; no stated derivation. It affects the reported plurality of correct solutions.
  • V-MTJ cell area assumption = 50 F^2 plus support circuitry
    Scaling projections to millions of bits assume a 50 F^2 per-cell footprint for V-MTJ modules (Methods, based on cited MRAM cell references). This is a literature-derived assumption, not measured in this work, and it directly determines the projected p-bit density.
  • Applied bias field angle and magnitude for V-MTJ = ~37 degrees from normal, in-plane component of -62 Oe
    Adjusted via permanent magnet positioner to produce 50/50 switching probability; it compensates stray field and provides the precession reference. This is an experimental tuning parameter that affects bit balance, and the residual bias remains.
assumptions (4)
  • domain assumption The p-bit update rule in Eq. 1 (m_i(t+1) = sgn[tanh(I_i/T) + r(-1,1)]) samples the intended Ising-Boltzmann distribution.
    Adopted from prior p-bits literature (Camsari et al., Aadit et al.); the paper does not re-derive it. The hardware PLU approximates this rule with a 16-bit LUT.
  • domain assumption Invertible logic gate ground states encode valid truth tables, so fixing a multiplier output and annealing yields correct factors.
    Assumed from prior work on p-bits and invertible logic (Refs. 30, 49); used to construct the factorizer from AND, half-adder, and full-adder blocks. Derivations are said to be in Supplementary Note 2, which is not included.
  • domain assumption The VCMA pulse protocol yields statistically independent, near-50/50 random bits from a thermally stable MTJ.
    The mechanism is described and a sample bitstream is shown, but the raw bit stream fails most NIST tests. The paper relies on this assumption when feeding un-XORed bits to the ASIC.
  • ad hoc to paper Synthesized gate densities and 50 F^2 V-MTJ cell areas extrapolate to real advanced-node manufacturability.
    Used for the 45 nm and 7 nm projections and the 'millions of bits' statement; these are not manufacturing demonstrations. The GPDK and ASAP7 libraries are predictive, not foundry-qualified.

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Cite this review

Pith. "Pith review of Integrated probabilistic computer using voltage-controlled magnetic tunnel junctions as its entropy source." pith.science (2026). https://pith.science/paper/EWAJRIBP

@misc{pith2026241208017,
  author       = {Pith},
  title        = {Pith review of: Integrated probabilistic computer using voltage-controlled magnetic tunnel junctions as its entropy source},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/EWAJRIBP}},
  note         = {Machine review of arXiv:2412.08017}
}
read the original abstract

Probabilistic Ising machines (PIMs) provide a path to solving many computationally hard problems more efficiently than deterministic algorithms on von Neumann computers. Stochastic magnetic tunnel junctions (S-MTJs), which are engineered to be thermally unstable, show promise as entropy sources in PIMs. However, scaling up S-MTJ-PIMs is challenging, as it requires fine control of a small magnetic energy barrier across large numbers of devices. In addition, non-spintronic components of S-MTJ-PIMs to date have been primarily realized using general-purpose processors or field-programmable gate arrays. Reaching the ultimate performance of spintronic PIMs, however, requires co-designed application-specific integrated circuits (ASICs), combining CMOS with spintronic entropy sources. Here we demonstrate an ASIC in 130 nm foundry CMOS, which implements integer factorization as a representative hard optimization problem, using PIM-based invertible logic gates realized with 1143 probabilistic bits. The ASIC uses stochastic bit sequences read from an adjacent voltage-controlled (V-) MTJ chip. The V-MTJs are designed to be thermally stable in the absence of voltage, and generate random bits on-demand in response to 10 ns pulses using the voltage-controlled magnetic anisotropy effect. We experimentally demonstrate the chip's functionality and provide projections for designs in advanced nodes, illustrating a path to millions of probabilistic bits on a single CMOS+V-MTJ chip.

Figures

Figures reproduced from arXiv: 2412.08017 by the authors.

Figure 1
Figure 1. V-MTJ characteristics. a Schematic illustration of the 30 nm V-MTJ pillar used in this work. Voltage is applied between the top and bottom electrodes. b Relation between applied voltage and coercivity of the device due to VCMA. A linear interpolation is accurate over the voltage range explored in this work. c Relation between the read voltage and the parallel and antiparallel resistance levels of the V-MTJ. It is wo… view at source ↗
Figure 2
Figure 2. VCMA-based random bit generation. a Energy landscape illustration of MTJ undergoing VCMA-induced random switching. When a voltage pulse is applied to the MTJ, the energy barrier between the parallel (P) and antiparallel (AP) states disappears, causing the system to relax to an in-plane intermediate state within a few nanoseconds. When the voltage pulse is removed, the energy barrier re￾emerges, and the system finds … view at source ↗
Figure 3
Figure 3. Experimental configuration. a Setup showing the connections between the ASIC, the ASIC’s control board, the VCMA-TRNG PCB, the V-MTJ, and the pulse generator. b Microscope photograph of the connections to a V-MTJ device. c The Graphic Design System (GDSII) format rendering of the ASIC design, excluding metal layer 1 for visibility. The design area, center top, is connected to the ASIC control board and the RISC-V CP… view at source ↗
Figures from the paper (3 more)
Figure 4
Figure 4. Figure 4: Data flow block diagram. a The PLU which converts a uniformly distributed random number to one pulled from the hyperbolic arc-tangent distribution, scaled by a mathematical temperature. This implements part of the probabilistic update equation, with the corresponding p…
Figure 5
Figure 5. Figure 5: Factorization circuit. a Invertible logic gate factorization circuit made of invertible adders and gates. This design can be scaled to implement any symmetric binary factorization problem. b J matrix (above) and h vector (below) for an invertible AND gate, half adder, …
Figure 6
Figure 6. Figure 6: PIM performance results. a Simulated mean trials-to-solution for 6-bit factorization problem instances with different starting and finishing temperatures used in simulated annealing. Each trial consisted of 8192 iterations, after which the p-bit states were recorded. A…

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Pith tools

Reviewed August 11, 2026 · model on record in the stance chip above.