Pith. sign in

REVIEW 5 major objections 6 minor 38 references

NSFlow: An End-to-End FPGA Framework with Scalable Dataflow Architecture for Neuro-Symbolic AI

T0 review · 5 major / 6 minor · reviewed 2026-08-16 · deepseek-v4-flash

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗ Review JSON

Pith's one-line read Neuro-symbolic AI can be accelerated end-to-end on FPGAs, with a 31x speedup over a Jetson TX2 reported.

desk verdict NSFlow is a well-engineered and plausibly useful framework for FPGA-based neuro-symbolic acceleration, but the headline speedup numbers are not yet backed by a measurement methodology that separates the analytical model from actual board execution. read the letter →

arxiv 2504.19323 v2 pith:7SRYFU6F submitted 2025-04-27 cs.AR cs.AIcs.LGcs.PF

Hanchen Yang , Zishen Wan , Ritik Raj , Joongun Park , Ziwei Li , Ananda Samajdar , Arijit Raychowdhury , Tushar Krishna This is my paper · ORCID
classification cs.ARcs.AIcs.LGcs.PF
keywords neuro-symbolicAIFPGAaccelerationsystolicarrayvector-symbolicarchitecturecircularconvolutiondesignspaceexplorationmixedprecisiondataflow
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

NSFlow is an end-to-end FPGA design flow that targets neuro-symbolic AI workloads, which mix neural-network perception with vector-symbolic reasoning. The paper argues that this workload class is poorly served by CPUs, GPUs, TPUs, and existing FPGA deep-learning accelerators because its symbolic kernels are memory-bound, irregular, and sit on the critical path. NSFlow's generator builds a dataflow graph from the workload, searches over hardware configurations and kernel mappings, and produces a tailored FPGA design with a foldable systolic array, flexible on-chip memory, and mixed-precision arithmetic. On three neuro-symbolic models and six reasoning benchmarks, the paper reports 31x speedup over the Jetson TX2, over 2x over an RTX 2080 GPU, up to 8x over a TPU-like systolic array, and over 3x over the Xilinx DPU. The deeper claim is that the first automated, general-purpose FPGA acceleration path for neuro-symbolic inference is possible, making real-time cognitive reasoning on edge devices attainable.

What carries the argument

The load-bearing object is the NS-adaptive systolic array (AdArray): a grid of MAC processing elements, each augmented with a 'passing register' that delays one input stream by one cycle, enabling blockwise circular convolution—the core symbolic binding/unbinding operation of vector-symbolic architectures—to be executed on the same hardware as ordinary GEMM. By partitioning the array into sub-arrays that can be dynamically combined or split, a single design runs neural layers and symbolic vector ops in parallel on separate tiles. The frontend's dataflow graph and two-phase design-space exploration select the array dimensions, number of sub-arrays, memory sizes, and per-layer partition counts, using analytical runtime models for NN layers and for spatial/temporal mappings of VSA ops. The memory system (partitionable double-buffered BRAM blocks plus URAM cache) and SIMD unit are sized from the same graph so that data movement is overlapped with compute.

What would settle it

Run the NSFlow-generated bitstreams for NVSA, MIMONet, and LVRF on the AMD U250 board with cycle-accurate performance counters, and compare measured per-kernel latency to the predictions of Eqs. (1)-(5); if measured NN or VSA runtimes deviate by more than a few percent from the model, the chosen configurations may be suboptimal and the reported speedups against TX2, GPU, TPU, and DPU baselines would need to be re-measured under identical conditions.

Watch

Extended reading notes

Core claim

The central claim is that a single parameterized FPGA architecture, together with an automated design-space exploration frontend, can accelerate general neuro-symbolic AI workloads by an order of magnitude or more compared with existing edge and datacenter accelerators. The paper's key move is to treat the two sides of neuro-symbolic computation—neural network layers and symbolic vector operations such as blockwise circular convolution—as coexisting kernels that can be mapped onto one reconfigurable systolic array. A 'passing register' in each processing element introduces a one-cycle skew that lets the same MAC hardware stream circular convolution efficiently, while the array can fold into sub-arrays so that some columns run neural ops and others run symbolic ops simultaneously. The frontend generator extracts an execution trace, identifies critical paths and inter-loop dependencies, and uses a two-phase search over array height, width, and partition counts to choose the configuration. The paper reports that the resulting designs beat the compared baselines on all six reasoning tasks, and that mixed INT8/INT4 precision preserves reasoning accuracy while cutting memory footprint roughly 5.8x.

Load-bearing premise

The load-bearing premise is that the analytical runtime models the design-space search optimizes against accurately predict actual execution on the FPGA; if they are optimistic, the chosen configurations and reported speedups would not hold on real hardware.

Editorial extensions

If this is right

  • If the reported numbers are representative, a single FPGA board can run neuro-symbolic reasoning tasks in real time that take minutes on a desktop GPU, directly enabling cognitive workloads on edge devices.
  • The AdArray passing-register trick gives any vector-symbolic architecture a natural systolic mapping, so the speedups should transfer to other VSA-based models beyond NVSA, MIMONet, and LVRF.
  • Because the frontend is automated and end-to-end, users need only supply the workload program; the framework's ability to produce a tailored bitstream could lower the barrier to FPGA deployment for non-hardware experts.
  • Mixed INT8/INT4 precision keeps reasoning accuracy close to FP32 while cutting memory footprint by roughly 5.8x, which matters for on-chip capacity and bandwidth.
  • The scaling result—only about 4x runtime increase when symbolic workload size grows 150x—suggests the architecture does not bottleneck on symbolic memory traffic the way GPUs and TPUs do.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • One implicit consequence is that the same co-design recipe—extract trace, build dataflow graph, co-explore array shape and mapping—should apply to other heterogeneous inference workloads that mix dense and irregular kernels, such as graph neural networks or retrieval-augmented generation, even though the paper only evaluates VSA-based neuro-symbolic models.
  • Because the speedups are computed against analytical runtime models rather than board measurements, a natural test is to run the generated bitstreams on the AMD U250 and compare wall-clock time; if model errors are systematic, the two-phase DSE may be selecting the wrong array shape for extreme workload mixes.
  • The passing-register mechanism effectively turns circular convolution into a dataflow pattern with the same regularity as matrix multiplication; this suggests that other convolution-like symbolic operations, such as blockwise circular correlation, could be folded into the same array with no additional hardware.
  • The reported 4x runtime scaling over 150x symbolic workload growth hints that memory-aware partitioning and double-buffering are doing the heavy lifting; a direct ablation that varies only memory reorganization without array folding would isolate which component drives scalability.
Share X Bluesky LinkedIn Reddit HN

Signed reviews

No signed human review yet.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

5 major / 6 minor

Summary. The paper proposes NSFlow, an end-to-end FPGA acceleration framework for neuro-symbolic AI (NSAI) workloads. The frontend extracts an execution trace, builds a dataflow graph, and runs a two-phase design space exploration (DSE) to choose the systolic-array geometry, memory partition, and kernel-to-subarray mapping. The backend implements an adaptive systolic array with sub-array folding, reconfigurable on-chip memory, mixed-precision compute, and a SIMD unit. The evaluation reports large speedups over Jetson TX2, RTX 2080, a TPU-like systolic array, and Xilinx DPU, plus a scalability result. The paper claims to be the first automated end-to-end framework for accelerating generic NSAI workloads on FPGAs.

Significance. If the reported speedups are real, NSFlow would be a meaningful contribution: it addresses a genuine gap in accelerating heterogeneous neuro-symbolic pipelines, and the proposed architecture—an adaptive systolic array with sub-array folding and reconfigurable memory—is a plausible way to handle both CNN and vector-symbolic kernels. The paper also provides a concrete end-to-end tool flow and an ablation study that isolates the effect of the two-phase DSE. However, the central performance claims are not yet supported by a measurement methodology independent of the analytical runtime models used by the DSE. Without board-level or RTL-simulated timing, the 31x/8x/3x speedups remain projections rather than demonstrated properties. The framework's novelty is also somewhat incremental relative to the authors' prior CoGSys work [29], but the end-to-end automation and FPGA-specific implementation are still valuable.

major comments (5)
  1. [Sec. VI, Fig. 5] The central speedup claims (31x over TX2, 8x over TPU-like array, 3x over DPU) are presented without any measurement methodology. The text never states whether NSFlow runtimes come from on-board timing (e.g., XRT clock queries) or from the analytical runtime functions in Eqs. (1)-(5). If they come from the analytical functions, the evaluation is circular because Algorithm 1 optimizes against the same functions. The authors must provide either (a) board-level or RTL-simulated timing for NSFlow and all baselines, or (b) explicitly label Fig. 5 as model-based projections and validate Eqs. (1)-(5) against cycle-accurate simulation or on-board measurements.
  2. [Sec. V-C, Eqs. (3)-(5)] The runtime models assume that memory transfers are fully hidden behind compute. Equations (3) and (4) count only array compute cycles with T = 3H + dj - 1 and contain no term for DRAM bandwidth, memory stalls, or reconfiguration overhead. This contradicts the paper's own characterization in Sec. II-B that symbolic modules are memory-bound and Sec. I that NSAI memory footprints can be tens to hundreds of MB while on-chip memory is about 36 MB. Unless the authors demonstrate that double buffering and cache behavior hide all off-chip traffic, the model overestimates throughput and the DSE may select a configuration that is optimal in the model but not on the board.
  3. [Sec. V-B, Algorithm 1 line 8] The DSE evaluates parallel execution of NN and VSA kernels with tpara = max(tnn, tvsa), which assumes that NN and VSA operations overlap without resource conflict. However, both kernel classes share the memory bus, on-chip cache, and AXI interfaces; for memory-bound symbolic kernels, overlapping operations will contend for bandwidth. The model does not include a bandwidth or contention term, so the predicted parallel speedup is an upper bound. The authors should either extend the analytical model with a contention component or verify experimentally that the predicted overlap is achieved.
  4. [Abstract and Sec. VI-B, Fig. 6] The abstract claims 'only 4x runtime increase when symbolic workloads scale by 150x,' but the experiments in Fig. 6 vary the symbolic memory proportion from 5% to 80%, which is not a 150x workload scaling. The experiment that supports the 150x scaling claim is not described in the text. Please specify the experimental setup, define what 'scaling by 150x' means (e.g., vector dimension or number of rules), and report the actual absolute runtime values.
  5. [Sec. VI-A] The experimental setup does not explain how the baseline numbers (TX2, Xavier NX, Xeon CPU, RTX 2080, TPU-like systolic array, Xilinx DPU) were obtained. In particular, the TPU-like systolic array and DPU baselines are not described as measured implementations. If these baselines are simulated using the same analytical framework (e.g., Scale-sim [31]), then the speedups over them are model-to-model comparisons and do not demonstrate real-device superiority. The authors must specify the measurement or simulation setup for each baseline and report absolute runtimes alongside the normalized values in Fig. 5.
minor comments (6)
  1. [Sec. V-C, Tab. II] The design-space reduction factor is inconsistent: Tab. II says the search space is reduced by 100 magnitudes (10^300 to 10^3), while the text in Sec. V-C says the search space is 'shrunk by 10^100x.' Please reconcile these numbers.
  2. [Sec. V-C, Eq. (1)] The dimensions d1,i, d2,i, and d3,i are said to correspond to the NN layer dimensions m, n, and k, but the mapping (input channels, output channels, filter size) is not stated. Please define the correspondence explicitly.
  3. [Abstract] The phrase 'only 4x runtime increase' is ambiguous: it could mean a 4-fold increase or an increase of 4 percentage points. Please rephrase, e.g., 'runtime grows by 4x' or 'runtime increases 4-fold.'
  4. [Fig. 5] The y-axis label says 'Norm. Runtime ( )' with an empty unit. Please specify the normalization reference (e.g., normalized to NSFlow) and the unit of the original runtime.
  5. [Sec. IV-B, Fig. 3(b)] The roles of the Passing Register and Streaming Register in the circular-convolution dataflow are hard to follow from the figure alone. Consider adding explicit labels or a short timing diagram to clarify the 1-cycle pacing mismatch.
  6. [Sec. VII] The conclusion restates the claim of being 'the first framework to enable real-time generalizable NSAI algorithms acceleration' without qualification. Please temper this claim unless a systematic comparison with prior NSAI accelerators is included.

Circularity Check

2 steps flagged · score 5.0 of 10

The abstract's speedup numbers are not shown to be independently measured: the DSE optimizes the same analytical runtime model (Eqs. 1-5, from the authors' own CoGSys and Scale-sim lineage) that the evaluation section appears to report, and the TX2/NX/GPU baselines come from self-cited profiling.

  1. fitted input called prediction [Sec. V-C ('Analytical models', Algorithm 1) and Sec. VI-B (Fig. 5)]
    "Inspired by the analytical models from previous research [29], [31], we derive runtime functions specifically for NSFlow. ... tpara = max(tnn(H, W, Nl), tvsa(H, W, Nv))"

    Algorithm 1 selects H, W, N, Nl, Nv by minimizing the runtime functions in Eqs. (1)-(5). The only runtime results in the paper are the normalized values in Fig. 5 and the millisecond values in Fig. 6; no XRT timing, RTL simulation, absolute NSFlow latency, or measurement methodology is reported. If those figures are produced by the same Eqs. (1)-(5), then the DSE's objective function and the reported 'speedup' are the same quantity: the design is optimized against the model and then the model is used to declare that the design wins. This is a model-to-model prediction, not an independently verified hardware result. The TPU-like systolic array baseline is also from the same modeling lineage ([29], [31]), so the comparison can reduce to arithmetic over self-cited equations.

  2. self citation load bearing [Sec. II-B and Sec. VI-B (Fig. 5)]
    "recent work [29] profiles four representative models as elaborated in Tab. I on Coral edge TPU (4 W), Jetson TX2 (15 W), Xavier NX (20 W), and RTX 2080Ti (250 W), respectively. ... We can observe in Fig. 5 that NSFlow accelerator consistently outperforms other devices, offering 31×/18× speedup over TX2 and NX, more than 2× over GPU, up to 8× speedup over TPU-like systolic array, and more than 3× speedup over Xilinx DPU."

    The central speedup claims in the abstract are computed against baselines whose runtime characterization is taken from [29], the authors' own CoGSys paper, rather than re-measured or independently reported in this manuscript. The 'TPU-like systolic array' baseline is a modeled device, and the runtime model is itself inherited from [29] and [31], both with overlapping authors. Thus the headline comparative result is justified by a self-citation chain: the model comes from the authors' prior work, the baselines come from the authors' prior work, and the NSFlow runtime is not shown to be a distinct measured quantity. This is load-bearing because removing that self-cited provenance leaves no independent evidence for the 31x/2x/8x/3x numbers.

full rationale

NSFlow does contain substantial non-circular content: it reports actual FPGA implementation results on AMD U250 (DSP/LUT/FF/BRAM/URAM utilization and 272 MHz frequency), mixed-precision reasoning accuracy versus FP32, memory-footprint reductions, and a nontrivial graph-based DAG/DSE flow. None of those claims reduce to their inputs by definition. The circularity concern is confined to the performance/speedup headline. The runtime model (Eqs. 1-5) is adopted from the authors' own CoGSys work [29] and co-authored Scale-sim work [31]; Algorithm 1 optimizes hardware configurations directly against those equations; and the evaluation section gives no independent measurement path (no XRT timing, no RTL simulation, no absolute NSFlow times, no board timing methodology). As written, the speedups in the abstract and Fig. 5 are therefore not established as measured properties; they are at best the value of the optimized analytical model compared with baselines drawn from the same self-cited characterization. That is a partial circularity: the model could in principle be validated externally, and the paper's other contributions remain independent, but the central performance claim is not shown to be independent of the model that generated the design.

Assumptions & free parameters 0 free parameters · 5 assumptions · 0 invented entities

No numeric constants are fit to data in the scientific sense. The design variables H, W, N, Nl, Nv are searched by the DSE rather than fitted, and the only hand-set values are DSE hyperparameters which do not enter the scientific claims as free parameters. No new physical or conceptual entities are proposed; the adaptive systolic array and passing register are hardware design elements, not invented entities in the physics sense.

assumptions (5)
  • domain assumption The analytical runtime models of Eqs. (1)-(5), inherited from the authors' prior work [29] and Scale-sim [31], accurately predict actual FPGA execution time.
    The DSE selects architectures based on these models, and the speedup claims in Section VI are presented in terms of runtime. If the models deviate from real hardware, the optimized configurations and all reported speedups are overestimates.
  • domain assumption The dataflow graph extracted from the PyTorch execution trace captures all data dependencies and parallelism opportunities in the NSAI workloads.
    The DAG's critical path and loop-fusion decisions in Section V-B depend on the completeness of the trace; workloads with operations outside the recognized set would break the generator.
  • domain assumption The TPU-like systolic array and Xilinx DPU baselines are modeled faithfully and represent fair comparisons.
    The 8x speedup over TPU-like and 3x over DPU claims in Fig. 5 rely on the accuracy of these baselines, but the paper does not describe how they were instantiated or whether they were run on hardware.
  • domain assumption Mixed-precision quantization to INT8/INT4 preserves reasoning accuracy within acceptable bounds on the evaluated datasets.
    Table IV supports this empirically for three datasets, but the central real-time and comparable accuracy value proposition depends on quantization not degrading accuracy beyond the reported levels.
  • domain assumption The four representative workloads (NVSA, MIMONet, LVRF, PrAE) are representative of the broader NSAI algorithm space.
    The paper generalizes from these workloads to generic NSAI workloads in the abstract; the accelerator template and DAG are tuned to their characteristic kernels.

how reviews work

0 comments
Cite this review

Pith. "Pith review of NSFlow: An End-to-End FPGA Framework with Scalable Dataflow Architecture for Neuro-Symbolic AI." pith.science (2026). https://pith.science/paper/7SRYFU6F

@misc{pith2026250419323,
  author       = {Pith},
  title        = {Pith review of: NSFlow: An End-to-End FPGA Framework with Scalable Dataflow Architecture for Neuro-Symbolic AI},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/7SRYFU6F}},
  note         = {Machine review of arXiv:2504.19323}
}
read the original abstract

Neuro-Symbolic AI (NSAI) is an emerging paradigm that integrates neural networks with symbolic reasoning to enhance the transparency, reasoning capabilities, and data efficiency of AI systems. Recent NSAI systems have gained traction due to their exceptional performance in reasoning tasks and human-AI collaborative scenarios. Despite these algorithmic advancements, executing NSAI tasks on existing hardware (e.g., CPUs, GPUs, TPUs) remains challenging, due to their heterogeneous computing kernels, high memory intensity, and unique memory access patterns. Moreover, current NSAI algorithms exhibit significant variation in operation types and scales, making them incompatible with existing ML accelerators. These challenges highlight the need for a versatile and flexible acceleration framework tailored to NSAI workloads. In this paper, we propose NSFlow, an FPGA-based acceleration framework designed to achieve high efficiency, scalability, and versatility across NSAI systems. NSFlow features a design architecture generator that identifies workload data dependencies and creates optimized dataflow architectures, as well as a reconfigurable array with flexible compute units, re-organizable memory, and mixed-precision capabilities. Evaluating across NSAI workloads, NSFlow achieves 31x speedup over Jetson TX2, more than 2x over GPU, 8x speedup over TPU-like systolic array, and more than 3x over Xilinx DPU. NSFlow also demonstrates enhanced scalability, with only 4x runtime increase when symbolic workloads scale by 150x. To the best of our knowledge, NSFlow is the first framework to enable real-time generalizable NSAI algorithms acceleration, demonstrating a promising solution for next-generation cognitive systems.

Figures

Figures reproduced from arXiv: 2504.19323 by the authors.

Figure 1
Figure 1. End-to-end neuro-symbolic runtime and roofline characterization. (a) Benchmark neuro-symbolic models on CPU+GPU system, showing sym￾bolic may serve as system bottleneck. (b) Benchmark on Coral TPU, TX2, NX, and 2080Ti GPU, showing that real-time performance cannot be satisfied. (c) Roofline of RTX 2080Ti GPU, indicating symbolic memory-bounded. providing essential inputs for reasoning. 2 Symbolic system. These featu… view at source ↗
Figure 3
Figure 3. NSFlow Hardware Architecture. numerous 18KB BRAM blocks for maximum configurability, and on-chip cache is built with URAM considering its large capacity (288KB per block). Small registers and buffers in compute element use LUTRAMs for fast and dynamic access. D. Adaptive Compute for Mixed Precision To improve computing efficiency and save on-chip memory usage, NSFlow supports mixed precisions ranging from FP16/8 to … view at source ↗
Figure 4
Figure 4. Dataflow Architecture Generation (DAG) Flow. TABLE II NSFLOW DESIGN SPACE. Maximum #PEs = 2m. With exploration phasing and space pruning, search space is reduced by 100 magnitudes. HW config (H, W, N) Array partition and mapping Total design space, m = 10 Original m × (m + 1)/2 (N − 1)k for each N 10300 DAG Phase I: 1/4 ≤ H/W ≤ 16 Phase II: Iter × #layers 103 path for a single loop of the workload. 2 Inner-loop para… view at source ↗
Figures from the paper (2 more)
Figure 5
Figure 5. Figure 5: End-to-End Runtime Improvement. NSFlow consistently outper￾forms Xilinx DPU, TPU-like accelerator, Xeon CPU, RTX GPU, and edge SoCs (TX2, NX) in end-to-end runtime evaluated on NSAI reasoning tasks. NSFlow w/o Phase II DSE w/o Phase I (128x64) Runtime (ms) 0% 100 101 1…
Figure 6
Figure 6. Figure 6: Ablation Study. NSFlow exhibits superior scalability comparing to normal TPU design across workloads with various symbolic proportions. Performance improvement. We first benchmark our NSFlow accelerator against edge SoC (Jetson TX2, Xavier NX), Intel Xeon CPU, Nvidia R…

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

38 extracted references · 33 canonical work pages

  1. [29]

    Cogsys: Efficient and scalable neurosymbolic cognition system via algorithm-hardware co-design,

    Z. Wan, H. Yang, R. Raj, C.-K. Liu, A. Samajdar, A. Raychowd- hury, and T. Krishna, “Cogsys: Efficient and scalable neurosymbolic cognition system via algorithm-hardware co-design,” in 2025 IEEE International Symposium on High Performance Computer Architecture (HPCA), pp. 775–789, IEEE, 2025

    work page 2025

  2. [31]

    A systematic methodology for characterizing scalability of dnn accelerators using scale-sim,

    A. Samajdar, J. M. Joseph, Y . Zhu, P. Whatmough, M. Mattina, and T. Krishna, “A systematic methodology for characterizing scalability of dnn accelerators using scale-sim,” in 2020 IEEE International Sym- posium on Performance Analysis of Systems and Software (ISPASS) , pp. 58–68, IEEE, 2020

    work page 2020

  3. [1]

    The neuro- symbolic concept learner: Interpreting scenes, words, and sentences from natural supervision,

    J. Mao, C. Gan, P. Kohli, J. B. Tenenbaum, and J. Wu, “The neuro- symbolic concept learner: Interpreting scenes, words, and sentences from natural supervision,” International Conference on Learning Representa- tions (ICLR), 2019

    work page 2019

  4. [2]

    Visual concept- metaconcept learning,

    C. Han, J. Mao, C. Gan, J. Tenenbaum, and J. Wu, “Visual concept- metaconcept learning,” Advances in Neural Information Processing Systems (NeurIPS), vol. 32, 2019

    work page 2019

  5. [3]

    Falcon: fast visual concept learning by integrating images, linguistic descriptions, and conceptual relations,

    L. Mei, J. Mao, Z. Wang, C. Gan, and J. B. Tenenbaum, “Falcon: fast visual concept learning by integrating images, linguistic descriptions, and conceptual relations,” International Conference on Learning Repre- sentations (ICLR), 2022

    work page 2022

  6. [4]

    Clevrer: Collision events for video representation and reasoning,

    K. Yi, C. Gan, Y . Li, P. Kohli, J. Wu, A. Torralba, and J. B. Tenenbaum, “Clevrer: Collision events for video representation and reasoning,” in International Conference on Learning Representations (ICLR) , 2020

    work page 2020

  7. [5]

    Abstract spatial-temporal reasoning via probabilistic abduction and execution,

    C. Zhang, B. Jia, S.-C. Zhu, and Y . Zhu, “Abstract spatial-temporal reasoning via probabilistic abduction and execution,” in Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR), pp. 9736–9746, 2021

    work page 2021

  8. [6]

    Knowledge-based Analogical Reasoning in Neuro-symbolic Latent Spaces

    V . Shah, A. Sharma, G. Shroff, L. Vig, T. Dash, and A. Srini- vasan, “Knowledge-based analogical reasoning in neuro-symbolic latent spaces,” arXiv preprint arXiv:2209.08750 , 2022

    work page Pith review arXiv 2022

Show all 38 references
  1. [7]

    Solving olympiad geometry without human demonstrations,

    T. H. Trinh, Y . Wu, Q. V . Le, H. He, and T. Luong, “Solving olympiad geometry without human demonstrations,” Nature, vol. 625, no. 7995, pp. 476–482, 2024

    2024

  2. [8]

    Special session: Neuro-symbolic architecture meets large language models: A memory-centric perspective,

    M. Ibrahim, Z. Wan, H. Li, P. Panda, T. Krishna, P. Kanerva, Y . Chen, and A. Raychowdhury, “Special session: Neuro-symbolic architecture meets large language models: A memory-centric perspective,” in 2024 International Conference on Hardware/Software Codesign and System Synth...

    2024

  3. [9]

    Towards cognitive ai systems: Workload and characterization of neuro-symbolic ai,

    Z. Wan, C.-K. Liu, H. Yang, R. Raj, C. Li, H. You, Y . Fu, C. Wan, A. Samajdar, Y . C. Lin,et al., “Towards cognitive ai systems: Workload and characterization of neuro-symbolic ai,” in 2024 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) ...

    2024

  4. [10]

    Thinking fast and slow in ai,

    G. Booch, F. Fabiano, L. Horesh, K. Kate, J. Lenchner, N. Linck, A. Loreggia, K. Murgesan, N. Mattei, F. Rossi, et al. , “Thinking fast and slow in ai,” in Proceedings of the AAAI Conference on Artificial Intelligence, vol. 35, pp. 15042–15046, 2021

    2021

  5. [11]

    Towards learning abductive reasoning using vsa distributed representations,

    G. Camposampiero, M. Hersche, A. Terzi ´c, R. Wattenhofer, A. Se- bastian, and A. Rahimi, “Towards learning abductive reasoning using vsa distributed representations,” in International Conference on Neural- Symbolic Learning and Reasoning , pp. 370–385, Springer, 2024

    2024

  6. [12]

    Probabilistic abduction for visual abstract reasoning via learning rules in vector-symbolic architectures,

    M. Hersche, F. Di Stefano, T. Hofmann, A. Sebastian, and A. Rahimi, “Probabilistic abduction for visual abstract reasoning via learning rules in vector-symbolic architectures,” Advances in Neural Information Pro- cessing Systems (NeurIPS) , 2023

    2023

  7. [13]

    Neuro- symbolic approaches in artificial intelligence,

    P. Hitzler, A. Eberhart, M. Ebrahimi, M. K. Sarker, and L. Zhou, “Neuro- symbolic approaches in artificial intelligence,” National Science Review, vol. 9, no. 6, p. nwac035, 2022

    2022

  8. [14]

    Is neuro-symbolic ai meeting its promises in natural language processing? a structured review,

    K. Hamilton, A. Nayak, B. Bo ˇzi´c, and L. Longo, “Is neuro-symbolic ai meeting its promises in natural language processing? a structured review,” Semantic Web, vol. 15, no. 4, pp. 1265–1306, 2024

    2024

  9. [15]

    Towards efficient neuro-symbolic ai: From workload characterization to hardware architecture,

    Z. Wan, C.-K. Liu, H. Yang, R. Raj, C. Li, H. You, Y . Fu, C. Wan, S. Li, Y . Kim, et al. , “Towards efficient neuro-symbolic ai: From workload characterization to hardware architecture,” IEEE Transactions on Circuits and Systems for Artificial Intelligence , 2024

    2024

  10. [16]

    H3dfact: Heterogeneous 3d integrated cim for factorization with holographic perceptual representations,

    Z. Wan, C.-K. Liu, M. Ibrahim, H. Yang, S. Spetalnick, T. Krishna, and A. Raychowdhury, “H3dfact: Heterogeneous 3d integrated cim for factorization with holographic perceptual representations,” in 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE) , pp. 1–...

    2024

  11. [17]

    A neuro-vector-symbolic architecture for solving raven’s progressive matrices,

    M. Hersche, M. Zeqiri, L. Benini, A. Sebastian, and A. Rahimi, “A neuro-vector-symbolic architecture for solving raven’s progressive matrices,” Nature Machine Intelligence, vol. 5, no. 4, pp. 363–375, 2023

    2023

  12. [18]

    Towards cognitive ai systems: a survey and prospective on neuro-symbolic ai,

    Z. Wan, C.-K. Liu, H. Yang, C. Li, H. You, Y . Fu, C. Wan, T. Krishna, Y . Lin, and A. Raychowdhury, “Towards cognitive ai systems: a survey and prospective on neuro-symbolic ai,”arXiv preprint arXiv:2401.01040, 2024

    2024 arXiv

  13. [19]

    Autosa: A polyhedral compiler for high-performance systolic arrays on fpga,

    J. Wang, L. Guo, and J. Cong, “Autosa: A polyhedral compiler for high-performance systolic arrays on fpga,” in The 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays , pp. 93– 104, 2021

    2021

  14. [20]

    Automated systolic array architecture synthesis for high throughput cnn inference on fpgas,

    X. Wei, C. H. Yu, P. Zhang, Y . Chen, Y . Wang, H. Hu, Y . Liang, and J. Cong, “Automated systolic array architecture synthesis for high throughput cnn inference on fpgas,” in Proceedings of the 54th Annual Design Automation Conference 2017 , pp. 1–6, 2017

    2017

  15. [21]

    A survey of fpga design for ai era,

    Z. Li, Y . Zhang, J. Wang, and J. Lai, “A survey of fpga design for ai era,” Journal of Semiconductors , vol. 41, no. 2, p. 021402, 2020

    2020

  16. [22]

    Understanding the potential of fpga-based spatial acceleration for large language model inference,

    H. Chen, J. Zhang, Y . Du, S. Xiang, Z. Yue, N. Zhang, Y . Cai, and Z. Zhang, “Understanding the potential of fpga-based spatial acceleration for large language model inference,” ACM Transactions on Reconfig- urable Technology and Systems , 2024

    2024

  17. [23]

    A comprehensive evaluation of fpga-based spatial acceler- ation of llms,

    H. Chen, J. Zhang, Y . Du, S. Xiang, Z. Yue, N. Zhang, Y . Cai, and Z. Zhang, “A comprehensive evaluation of fpga-based spatial acceler- ation of llms,” in Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays , pp. 185–185, 2024

    2024

  18. [24]

    Flightllm: Efficient large language model inference with a complete mapping flow on fpgas,

    S. Zeng, J. Liu, G. Dai, X. Yang, T. Fu, H. Wang, W. Ma, H. Sun, S. Li, Z. Huang, et al. , “Flightllm: Efficient large language model inference with a complete mapping flow on fpgas,” in Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Array...

    2024

  19. [25]

    Fpga- based high-throughput cnn hardware accelerator with high computing resource utilization ratio,

    W. Huang, H. Wu, Q. Chen, C. Luo, S. Zeng, T. Li, and Y . Huang, “Fpga- based high-throughput cnn hardware accelerator with high computing resource utilization ratio,” IEEE Transactions on Neural Networks and Learning Systems, vol. 33, no. 8, pp. 4069–4083, 2021

    2021

  20. [26]

    A high throughput acceleration for hybrid neural networks with efficient resource management on fpga,

    S. Yin, S. Tang, X. Lin, P. Ouyang, F. Tu, L. Liu, and S. Wei, “A high throughput acceleration for hybrid neural networks with efficient resource management on fpga,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , vol. 38, no. 4, pp. 678–691, 2018

    2018

  21. [27]

    Llamaf: An efficient llama2 architecture accelerator on embedded fpgas,

    H. Xu, Y . Li, and S. Ji, “Llamaf: An efficient llama2 architecture accelerator on embedded fpgas,” arXiv preprint arXiv:2409.11424, 2024

    2024 arXiv

  22. [28]

    Mimonets: Multiple-input-multiple-output neural networks exploiting computation in superposition,

    N. Menet, M. Hersche, G. Karunaratne, L. Benini, A. Sebastian, and A. Rahimi, “Mimonets: Multiple-input-multiple-output neural networks exploiting computation in superposition,” Advances in Neural Informa- tion Processing Systems (NeurIPS) , vol. 36, 2023

    2023

  23. [30]

    High density 8-bit multiplier systolic arrays for fpga,

    M. Langhammer, S. Gribok, and G. Baeckler, “High density 8-bit multiplier systolic arrays for fpga,” in 2020 IEEE 28th Annual Interna- tional Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 84–92, IEEE, 2020

    2020

  24. [32]

    Raven: A dataset for relational and analogical visual reasoning,

    C. Zhang, F. Gao, B. Jia, Y . Zhu, and S.-C. Zhu, “Raven: A dataset for relational and analogical visual reasoning,” in Proceedings of the IEEE/CVF conference on computer vision and pattern recognition (CVPR), pp. 5317–5327, 2019

    2019

  25. [33]

    Stratified rule-aware network for abstract visual reasoning,

    S. Hu, Y . Ma, X. Liu, Y . Wei, and S. Bai, “Stratified rule-aware network for abstract visual reasoning,” in Proceedings of the AAAI Conference on Artificial Intelligence , vol. 35, pp. 1567–1574, 2021

    2021

  26. [34]

    Measuring abstract reasoning in neural networks,

    D. Barrett, F. Hill, A. Santoro, A. Morcos, and T. Lillicrap, “Measuring abstract reasoning in neural networks,” in International conference on machine learning (ICML) , pp. 511–520, PMLR, 2018

    2018

  27. [35]

    Gamma: Automating the hw mapping of dnn models on accelerators via genetic algorithm,

    S.-C. Kao and T. Krishna, “Gamma: Automating the hw mapping of dnn models on accelerators via genetic algorithm,” in Proceedings of the 39th International Conference on Computer-Aided Design , pp. 1–9, 2020

    2020

  28. [36]

    Maestro: A data-centric approach to understand reuse, performance, and hardware cost of dnn mappings,

    H. Kwon, P. Chatarasi, V . Sarkar, T. Krishna, M. Pellauer, and A. Parashar, “Maestro: A data-centric approach to understand reuse, performance, and hardware cost of dnn mappings,” IEEE micro, vol. 40, no. 3, pp. 20–29, 2020

    2020

  29. [37]

    A benchmark for compositional visual reasoning,

    A. Zerroug, M. Vaishnav, J. Colin, S. Musslick, and T. Serre, “A benchmark for compositional visual reasoning,” Advances in Neural Information Processing Systems (NeurIPS) , vol. 35, pp. 29776–29788, 2022

    2022

  30. [38]

    Comparing machines and humans on a visual categorization test,

    F. Fleuret, T. Li, C. Dubout, E. K. Wampler, S. Yantis, and D. Geman, “Comparing machines and humans on a visual categorization test,” Proceedings of the National Academy of Sciences , vol. 108, no. 43, pp. 17621–17625, 2011

    2011

Pith tools

Reviewed August 16, 2026 · model on record in the stance chip above.