Bridging the Gap: Physical PCI Device Integration Into SystemC-TLM Virtual Platforms

Jan Henrik Weinstock; Lukas J\"unger; Niko Zurstra{\ss}en; Nils Bosbach; Rainer Leupers; Rebecca Pelke

REVIEW 4 major objections 4 minor 34 references

Bridging the Gap: Physical PCI Device Integration Into SystemC-TLM Virtual Platforms

T0 review · 4 major / 4 minor · reviewed 2026-08-07 · deepseek-v4-flash

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Pith's one-line read A generic vPCI model lets a real PCIe device, such as Google Coral's Edge TPU, run inside a SystemC-TLM virtual platform, replacing virtual device models and speeding AI workloads by up to 480x.

desk verdict A real and well-engineered VFIO-to-SystemC integration, but the 'timed and deterministic' claims are unsubstantiated because the paper never shows how virtual time advances while the physical TPU runs. read the letter →

arxiv 2505.15590 v1 pith:DTRWCES7 submitted 2025-05-21 cs.SE cs.ARcs.PF

Nils Bosbach , Rebecca Pelke , Niko Zurstra{ss}en , Jan Henrik Weinstock , Lukas Jünger , Rainer Leupers This is my paper · ORCID

classification cs.SEcs.ARcs.PF

keywords SystemCTLM-2.0VFIOPCIevirtualplatformhybridsimulationEdgeTPUIOMMU

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper argues that a physical PCI or PCIe device plugged into a host computer can be operated inside a SystemC-TLM virtual platform as if it were a virtual model, with no device-specific virtual model needed. The approach uses Linux's VFIO driver to expose the real card, maps the virtual platform's RAM into the host's IOMMU so the card's DMA lands in the simulated memory, and forwards interrupts back into the simulation. In a case study, a Google Coral Edge TPU is attached to an ARMv8 virtual platform; offloading neural-network inference to the real TPU speeds the simulated workloads by up to 480x compared to CPU-only execution in the VP. The authors claim this enables fast AI execution, driver development, regression testing across architectures, and device communication analysis.

What carries the argument

The load-bearing object is the vPCI device model, a generic TLM-2.0 target socket that stands in for a real PCI(e) card inside the virtual platform. It performs three functions: memory access, where configuration reads and writes go through VFIO syscalls while MMIO and I/O regions are mapped directly into the VP's address space; DMA, where the model asks the PCI host bridge for a Direct Memory Interface (DMI) pointer to the VP's RAM and hands that host virtual address plus the VP physical range to VFIO, which programs the host IOMMU so the real card's DMA writes land in the simulated RAM; and interrupt handling, where legacy IRQ pin numbers are read from configuration space and re-emitted on the PCI backward path, while MSI(-X) writes are translated into TLM transactions toward a virtual GICv2m interrupt controller. This generic forwarding is what makes the physical device usable as a drop-in replacement for a virtual model.

What would settle it

Run the same Edge TPU benchmark in the virtual platform while a second host process continuously allocates and touches memory to force swapping or page migration, then compare the simulated RAM contents to a run with no memory pressure; if the DMA mapping is not pinned, the two runs will diverge. Alternatively, attempt the setup on a host with the IOMMU disabled, where VFIO binding should fail and the integration cannot operate.

Watch

Extended reading notes

Core claim

A physical PCI(e) device can be integrated into a SystemC-TLM-2.0-based virtual platform through a generic vPCI model that uses VFIO for configuration and MMIO/I/O access, a host IOMMU configured with a DMI pointer to the VP's RAM for DMA, and forwarding of both legacy interrupts and MSI(-X) into the virtual interrupt controller. The model is device-independent: the target software on the vCPU talks to the card through the virtual PCI host bridge using VCML's PCI TLM protocol, so the same driver stack runs against real hardware. The case study shows that this setup works with a real Edge TPU and that the dominant cost—neural-network inference—moves onto physical hardware, yielding speedups of roughly 10x to 480x over VP-only CPU execution. The authors therefore claim that hybrid simulation can replace complex virtual device models with real devices while keeping SystemC's standardized interfaces, virtual-time kernel, and tracing capabilities.

Load-bearing premise

The approach assumes that the host's memory-mapping hardware can be configured once to send the device's direct memory accesses into the virtual platform's memory, and that those host memory pages never move; if they are swapped or relocated, the physical device could write to the wrong memory and corrupt the simulation.

Editorial extensions

If this is right

Real AI accelerators, Ethernet NICs, GPUs, and other PCIe cards can replace virtual models in SystemC virtual platforms, removing modeling effort and increasing simulation speed.
Driver software for different CPU architectures can be developed and regression-tested against the same physical card on one host, with multiple virtual platforms sharing the device.
vCPU-to-device traffic and interrupt counts remain observable through standard TLM sockets, supporting debugging and profiling without extra hardware probes.
AI workloads in virtual platforms can run at speeds close to native hardware, with observed speedups between roughly 10x and 480x for Edge TPU inference.
Because the integration uses standard VFIO and SystemC/TLM interfaces, the vPCI model is portable to virtual platforms beyond the specific ARMv8 platform used in the case study.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

The DMA path implicitly assumes the host kernel keeps the virtual platform's RAM pages at the same physical locations for the whole simulation; real deployments would need memory pinning or IOMMU invalidation handling, which the paper does not discuss.
Because DMA traffic bypasses the VP's memory model, the tracing shown in the paper captures only vCPU-to-device communication and interrupts, not the bulk of the data movement; a future extension could instrument the IOMMU or the RAM model to trace DMA as well.
The claimed determinism of SystemC-based simulation may not fully extend to wall-clock timing once a real device is in the loop, since the physical card introduces host-dependent latencies; repeated runs with timing instrumentation would quantify this effect.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

I read the vPCI paper. Here is my take: the core contribution is real and the integration is well engineered; however, the authors' claim that their approach is 'timed' and 'deterministic' is not backed by the text, and that matters because it is the stated reason for preferring SystemC over QEMU.

What is new: this is the first time a physical PCIe device is passed through to a SystemC-TLM virtual platform via VFIO. The design has three pieces: MMIO access via direct mapping into the VP address space, DMA through a DMI pointer into the RAM model with the host IOMMU set up to translate VP addresses, and interrupt forwarding over the TLM PCI protocol. These are standard VFIO operations, but applying them to a TLM socket and getting the case study to run is a legitimate engineering contribution. The Edge TPU experiment is a reasonable stress test. I also find the reader's page-pinning concern to be a non-issue: VFIO MAP_DMA pins the pages, so there is no relocation hazard.

The soft spots are larger. The paper never explains how virtual time advances while the physical TPU is executing. A blocking wait on the VFIO eventfd freezes the SystemC kernel; polling would make timing depend on the host scheduler. Either way, 'timed' is a stretch. And determinism cannot survive the non-deterministic latency of a physical device. This is the paper's main weakness. Second, there is no validation that the TPU outputs are correct. The paper reports speedups but not whether the inference results match native execution. A referee should push on this. Minor: the measurements are medians of 100 runs without error bars, and there is no baseline against a virtual TPU model, so 'eliminating the need for a model' is an assertion, not a demonstrated benefit.

Who will benefit: anyone building SystemC-TLM VPs for AI workloads or wanting to bring real devices into hybrid simulation. It is a solid conference paper, but the timing/determinism claims need to be fixed or heavily qualified.

For peer review: send it out. A serious referee can get the authors to clarify the synchronization and add correctness checks. My verdict: conditionally solid.

Referee Report

4 major / 4 minor

Summary. The paper presents a VFIO-based virtual PCI (vPCI) model for SystemC-TLM-2.0 virtual platforms, allowing a physical PCIe device to be accessed by a simulated CPU through MMIO, configuration, DMA via the host IOMMU, and interrupt forwarding through VCML's PCI TLM protocol. The approach is demonstrated in a case study that integrates Google Coral's Edge TPU into an open-source ARMv8 virtual platform, comparing CPU-only execution against TPU offloading for 13 neural-network workloads. The reported speedups range from roughly 8x to 484x, based on median wall-clock times of 100 runs, and the paper also presents trace-based communication analysis of memory accesses and MSI-X interrupts. The authors position the work as having advantages over QEMU in modularity, timing, determinism, and tracing capability.

Significance. If the synchronization and correctness gaps are closed, this is a useful contribution to hybrid simulation in SystemC-TLM: it demonstrates a clean VFIO-based vPCI model, integrates a real Edge TPU into an open-source ARMv8 VP, and reports measured speedups with no fitted parameters in the speedup derivation. The tracing of vCPU-to-device transactions and MSI-X interrupts is a practical benefit for driver debugging, and the use of open-source VCML/AVP64 components supports reproducibility. The main significance is therefore as a proof of concept for accelerator-in-the-loop VP simulation, not as a fully validated timing model; the paper's Table 1 claims go beyond what the current measurements establish.

major comments (4)

[Section 3, Table 1, Section 4.3] The paper claims that, unlike QEMU, the proposed simulation is 'Timed' and 'Deterministic', but it never states how the SystemC kernel advances virtual time while the physical TPU is executing. If the vPCI device blocks on a VFIO eventfd while waiting for the completion interrupt, the SystemC kernel is stalled and virtual time does not advance during acceleration; if instead a delay model is used, neither its value nor its justification is given. The wall-clock times in Section 5.1 do not establish a timed simulation, and physical interrupt arrival depends on host scheduling, so run-to-run determinism of transaction ordering and virtual timestamps is not shown. Please specify the synchronization mechanism and provide an empirical determinism check (e.g., repeated runs with identical virtual-time traces).
[Section 4.2, Figure 4] The DMA path relies on passing the DMI pointer (a host virtual address into the RAM model) to VFIO for IOMMU mapping. VFIO's MAP_DMA operation pins the corresponding host pages, so the page-pinning concern is mitigated only if the DMI pointer is page-aligned and the RAM model's backing store is a contiguous, page-aligned region; the paper does not discuss this. Please state the alignment and contiguity conditions, or describe a fallback mapping procedure, so that DMA cannot silently target memory outside the VP's RAM model.
[Section 5.1, Figure 7] The speedup analysis reports medians of 100 runs and no dispersion measures, and it does not validate that the TPU offloading produces correct inference results. Without error bars or at least min/max ranges, a reader cannot tell whether the reported speedups are stable, and without a correctness check (e.g., comparing classification labels or detection outputs between CPU-only and TPU paths), a fast but incorrect execution would still satisfy the reported numbers. Please add variance information and a correctness validation of the accelerator results.
[Abstract, Section 6] The paper claims that the approach 'eliminates the need for complex virtual device models', but it provides no comparison with a virtual TPU model in terms of development effort, simulation speed, or accuracy. This overstates the contribution; either include a comparison with a functional or approximate TPU model or soften the claim to state that no such model was needed for this case study.

minor comments (4)

[Table 1] The table uses symbols or check marks to indicate capabilities, but no legend is provided; please define the notation or use explicit 'yes/no' entries.
[Section 5, first paragraph] The TensorFlow Lite framework is cited as '[?]', which appears to be a missing or incomplete reference.
[Section 5.2, Figure 8b] The term 'sc-host 0' is used without an explanation of how it maps to the TPU's 13 MSI-X vectors; please clarify this naming.
[Section 6, first paragraph] The phrase 'the superfluity of the creation of a virtual model' is awkward; consider replacing it with 'the elimination of the need to create a virtual model'.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: the reported speedup is a measured benchmark ratio, not a self-derived prediction.

full rationale

This paper contains no derivation chain in which a predicted quantity is constructed from its own inputs. The central result is an experimental comparison: speedup S = t_CPU / t_TPU, with both times measured as wall-clock times in Section 5.1 and Figure 7. No parameter is fitted to the data and then reported as a prediction. No uniqueness theorem or ansatz is imported from the authors' prior work. The cited prior artifacts (VCML [24], AVP64 [18,19], and the NISTT tracing tool [6]) are building blocks and tooling, not load-bearing justifications for the measured speedup or for the PCI/VFIO mechanism. The claims that SystemC is timed and deterministic are inherited from the SystemC standard and are not obtained by circular reduction. Whether the wall-clock TPU path preserves determinism is a correctness or validation concern, not a circularity. Likewise, the possible DMA/IOMMU mapping issue is a technical robustness concern. No circular step can be exhibited with a quotation and a specific reduction, so the appropriate finding is no significant circularity.

Assumptions & free parameters 0 free parameters · 5 assumptions · 0 invented entities

The work depends on standard Linux VFIO/IOMMU facilities and on the unmodified behavior of the physical PCIe device. No free parameters are fitted. The main unproven assumption is that the host memory mapping remains valid and that determinism is preserved with real hardware.

assumptions (5)

domain assumption VFIO provides raw PCI(e) access to user space and supports IOMMU mapping of user memory
The whole approach depends on VFIO's ability to map memory and forward interrupts as described in Section 2.2.
domain assumption The host system has an IOMMU and it is enabled
VFIO requires an activated IOMMU, as stated in Section 2.2.
domain assumption The VP's RAM model is a contiguous memory region that can be described by a DMI pointer for IOMMU mapping
Section 4.2 uses a DMI pointer to the virtual RAM; if the memory is scattered, the IOMMU mapping would be incomplete or fail.
domain assumption The physical PCI(e) device behaves as expected when driven by the unmodified guest OS driver
The case study relies on the TPU driver working correctly inside the simulated ARM environment (Section 5).
ad hoc to paper The integration preserves SystemC's determinism even with real hardware interrupts
Section 3 claims determinism, but the paper does not test or discuss non-determinism introduced by the physical device and its wall-clock timing.

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Cite this review

Pith. "Pith review of Bridging the Gap: Physical PCI Device Integration Into SystemC-TLM Virtual Platforms." pith.science (2026). https://pith.science/paper/DTRWCES7

@misc{pith2026250515590,
  author       = {Pith},
  title        = {Pith review of: Bridging the Gap: Physical PCI Device Integration Into SystemC-TLM Virtual Platforms},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/DTRWCES7}},
  note         = {Machine review of arXiv:2505.15590}
}

read the original abstract

In today's technology-driven world, early-stage software development and testing are crucial. Virtual Platforms (VPs) have become indispensable tools for this purpose as they serve as a platform to execute and debug the unmodified target software at an early design stage. With the increasing complexity of software, especially in areas like Artificial Intelligence (AI) applications, VPs need to provide high simulation speed to ensure the target software executes within a reasonable time. Hybrid simulation, which combines virtual models with real hardware, can improve the performance of VPs. This paper introduces a novel approach for integrating real Peripheral Component Interconnect (PCI) devices into SystemC-TLM-2.0-based VPs. The embedded PCI devices enable high performance, easy integration, and allow introspection for analysis and optimization. To illustrate the practical application of our approach, we present a case study where we integrate Google Coral's Edge Tensor Processing Unit (TPU) into an ARM-based VP. The integration allows efficient execution of AI workloads, accelerating simulation speeds by up to 480x while eliminating the need for complex virtual device models. Beyond accelerating AI-workload execution, our framework enables driver development, regression testing across architectures, and device communication analysis. Our findings demonstrate that embedding PCI devices into SystemC simulations significantly enhances

Figures

Figures reproduced from arXiv: 2505.15590 by the authors.

**Figure 2.** IOMMU working principle. The Memory-Mapped Input/Output (MMIO) regions of the PCI(e) device can directly be mapped into the address space of a process. To reroute DMA accesses of the device to a memory region of the user-space process, an Input-Output Memory Management Unit (IOMMU) of the host system is needed. The IOMMU translates addresses on DMA accesses as visualized in [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗

**Figure 3.** Memory access implementation. as reference. This can lead to non-deterministic behavior. SystemC, on the other hand, has a concept of a virtual time that is kept track of by the SystemC kernel. In addition, SystemC simulations are deterministic, meaning that multiple runs of the same simulation with the same inputs will produce exactly the same output. This is very important for the reproducibility of bugs when VPs … view at source ↗

Figures from the paper (5 more)

**Figure 4.** Figure 4: DMA access configuration. To process the request, the vPCI device needs to access the HW device. For this access, two possibilities exist. If the address belongs to the configuration space, Linux’s pread or pwrite syscalls need to be used. The file descriptor that need…

**Figure 5.** Figure 5: Interrupt forwarding implementation. During the VP setup, the vPCI device requests a Direct Memory Interface (DMI) pointer (host VA) to the specified region using the DMI TLM socket of the connected PCI host bridge i . The vPCI device configures the host’s IOMMU by pas…

**Figure 6.** Figure 6: VP setup with connected VFIO device. 5 Case Study To showcase the effectiveness and working principle of our vPCI model, we present the integration of Google Coral’s PCIe Edge TPU into the ARMv8 Virtual Platform (AVP64) [18,19]. We compare the runtime performance of an…

**Figure 7.** Figure 7: Inference results. 5.1 Speedup Analysis To analyze the impact of offloading workload to the TPU, all benchmarks are executed in two configurations. At first, they are compiled for CPU-only execution. Then, they are compiled using the Edge TPU compiler to offload compu…

**Figure 8.** Figure 8: TPU execution statistics. 5.2 Communication Analysis A benefit of using VPs for SW development compared to real HW is the simplicity of tracing data collection. Since the VP offers insights into the models and their communication, complex debuggers or probes typically…

Discussion (0). Continue with ORCID to comment.

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Pith tools

Reviewed August 7, 2026 · model on record in the stance chip above.

[1] [1]

AMD Inc.: AMD I/O Virtualization Technology (IOMMU) Specification, 48882 (Oct 2023)

work page 2023

[2] [2]

PC system architecture series, Addison-Wesley, Boston, Mass

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work page 1999

[3] [3]

ARM: Arm System Memory Management Unit Architecture Specification

work page

[4] [4]

In: USENIX an- nual technical conference, FREENIX Track

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