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REVIEW 2 major objections 7 minor 38 references

GenTT: Generate Vectorized Codes for General Tensor Permutation

T0 review · 2 major / 7 minor · reviewed 2026-08-07 · deepseek-v4-flash

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Pith's one-line read GenTT claims a single code generator can SIMD-vectorize any tensor permutation in one load-shuffle-store pass, at $O(N \log_2 w / w)$ worst-case cost.

desk verdict GenTT has a real tiling-and-butterfly idea and good correctness testing, but its worst-case complexity claim is falsified by a simple small-block counterexample, and the evaluation has loose ends (missing HPTT, inconsistent speedup numbers). read the letter →

arxiv 2506.03686 v1 pith:UFF5FTNW submitted 2025-06-04 cs.DS cs.DCcs.DM

Yaojian Chen , Tianyu Ma , An Yang , Lin Gan , Wenlai Zhao , Guangwen Yang This is my paper · ORCID
classification cs.DScs.DCcs.DM
keywords tensorpermutationSIMDcodegenerationvectorshuffletilingbutterflynetworkregisterrenamingcross-platformkernels
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Tensor permutation — reordering the indices of a multidimensional array — is a common step in AI data-layout changes, tensor-network contractions, and FFTs, and its cost depends heavily on shape and on which indices move. The paper's central claim is that this operation can be fully vectorized for arbitrary shapes, permutation maps, and SIMD instruction sets by a single code generator, with worst-case element work $O(N \log_2 w / w)$, where $w$ is the number of elements in a vector register. The method tiles the tensor into square blocks whose two sides are padded to power-of-two sizes fitting in $w$ lanes, performs the local permutation inside each block with a butterfly network of shuffle instructions, and handles misalignment with safe overlapping stores. If the claim holds, hand-written or pattern-specific transpose kernels are unnecessary: the same generated strategy works on x86, ARM, and Sunway, with reported speedups over standard tensor libraries reaching $38\times$ in special cases and about $5\times$ for general shapes.

What carries the argument

The load-bearing object is the padded square block. The generator picks a set of input trailing dimensions and a set of output trailing dimensions, pads each dimension up to the next power of two, and requires both padded products to be at most $w$, so one side of the block can be filled by contiguous vector loads and the other side by contiguous vector stores. Inside the block, the permutation is enacted by a butterfly network of vector shuffle instructions: in round $k$, register $i$ exchanges data with register $i \oplus 2^k$, so the corresponding index pair is swapped while elements inside each register are reordered; each common index between the two sides saves one round. Register renaming handles the final ordering of registers without extra data movement, and padded-shuffle cancellation drops instructions whose output registers contain no valid elements. The strategy is encoded in a hardware-independent IR parameterized by vector length $w$; backends lower the abstract load, store, and shuffle operations to the target ISA.

What would settle it

Run the generator on a sweep of small irregular shapes (e.g. dimensions from $\{3,5,7\}$ up to rank 6) with vector length $w=4$ and $w=8$; if any generated kernel falls back to scalar or multi-pass handling, or if its measured time grows faster than $O(N\log_2 w / w)$, the arbitrary-shape guarantee is false.

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Extended reading notes

Core claim

GenTT's central claim is that every tensor permutation can be decomposed into a high-level block permutation and a low-level in-block permutation, with both levels vectorized in a single load-shuffle-store pass: each element is loaded once, reordered inside registers, and stored once. A block is chosen from the trailing dimensions of the input and the trailing dimensions of the output, padded to powers of two so both products fit in $w$ lanes; the block's local permutation is realized by $\log_2 w$ rounds of pairwise register shuffles along a butterfly pattern, and register renaming absorbs the final column ordering. Common indices between the input-side and output-side block dimensions reduce the shuffle rounds, and a padded-shuffle step cancels operations whose output lanes contain no valid element. Unaligned loads and stores, together with a rotate-and-collect store for boundary registers, make the overlapping writes safe, so irregular shapes do not require a scalar residual loop. The result is a deterministic worst-case bound of $O(N \log_2 w / w)$ — a $w/\log_2 w$-fold reduction in element work over scalar $O(N)$ — claimed for arbitrary tensor shapes, permutation maps, and instruction sets.

Load-bearing premise

The framework assumes that for every tensor shape and permutation map, the trailing dimensions of the input and of the output can be padded (and where possible merged) so that both block products fit in one vector register; if no such block can be formed, the $O(N \log_2 w / w)$ bound and the arbitrary-shape guarantee break.

Editorial extensions

If this is right

  • Any tensor permutation — not just transposes or contraction layouts — gets a vectorized implementation with the same one-load-shuffle-store structure.
  • As SIMD width grows, the bound $\log_2 w / w$ decreases, so wider registers help instead of multiplying passes the way decomposition methods do.
  • Irregular shapes no longer force scalar residual processing: padding to powers of two is confined to registers and absorbed by self-shuffle and safe overlapping stores.
  • Only the backends need to change when moving to a new instruction set, so permutation kernels can be regenerated rather than rewritten for each architecture.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The paper does not prove that block selection succeeds for every shape; the fallback it spells out covers only the case where the last input dimension exceeds $w$, so a shape with several medium-sized dimensions and a small $w$ is the natural place to test the 'arbitrary shapes' claim.
  • Because permutations are memory-bound, the $O(N \log_2 w / w)$ bound is an instruction-count statement; on large tensors the measured speedup should approach the memory-bandwidth ratio, which the paper's own size-versus-speedup curve already suggests.
  • The butterfly local permutation is the same communication pattern used in all-to-all networks, so the scheme could plausibly be transplanted to GPU warp shuffles or other SIMT hardware that exposes pairwise exchange primitives; the authors do not discuss this direction.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

2 major / 7 minor

Summary. The paper proposes GenTT, a code generator that produces SIMD-vectorized tensor permutation kernels for a range of instruction sets, bit widths, tensor shapes, and permutation maps. The method tiles the tensor into small blocks whose trailing input and output dimensions are padded to powers of two, performs the local permutation with a butterfly-style multi-step shuffle, and handles misalignment with unaligned loads/stores and boundary reorganization. The paper claims a worst-case complexity of O(N log2 w / w), a deterministic ≥w/log2 w complexity reduction relative to scalar code, and speedups over NumPy, PyTorch, and HPTT. Experiments on x86, ARM, and Sunway platforms report correctness on over 1,000 randomized tests and speedups of up to 38-50× in special cases and roughly 4-5× for general shapes.

Significance. If the complexity and portability claims were fully supported, GenTT would be a useful contribution: a single generator covering multiple ISAs with a structural complexity analysis and an unusual amount of cross-platform validation. The randomized bitwise-equality testing and the instruction-reordering optimizations are strengths. However, the central complexity guarantee has a gap for shapes with several medium-sized dimensions, the claimed HPTT comparison is absent from the evaluation, and the reported speedup numbers are internally inconsistent. The work is potentially significant, but the claims need to be narrowed or repaired.

major comments (2)
  1. [§5.1, §4.2] The worst-case complexity O(N log2 w / w) and the 'arbitrary shapes' guarantee are not supported, because block selection can fail for shapes with several medium-sized dimensions. Consider shape (d2,d1,d0) = (M,3,3), w = 8, and permutation map (2,0,1) in the paper's notation, which swaps the last two axes. The trailing input dimension d0 = 3 pads to 4; including d1 = 3 gives padded product 4·4 = 16 > 8, so p = 0. Symmetrically, dσ0 = 3, so q = 0. The block is a 3×3 transpose padded to 4×4. Under the squared-shuffle scheme of §4.2, a 4×4 block requires 2 steps with 4 shuffles per step, i.e., 8 shuffle instructions per block, for 9 useful elements — about 0.89 shuffle instructions/element, versus the 0.375 shuffle/element implied by N log2(8)/8. Even counting padded elements, 8 shuffles per 16 slots is 0.5 > 0.375. The only exception stated in §5.1 (d0 > w or dσ0 > w) does not apply here. No fallback is described for shapes whose padded trailing products exceed w without any single dimension exceeding w; therefore the complexity guarantee and the deterministic ≥ w/log2 w reduction claim are not established for arbitrary tensors. The paper should also state precisely which instruction class the O(N log2 w / w) bound counts.
  2. [Abstract; §7.2.5; Figure 9] The introduction and conclusion claim speedups compared with HPTT, but Section 7 never reports an HPTT baseline; Figure 9 compares only against NumPy, PyTorch, and GCC auto-vectorization. In addition, the abstract reports 'up to 38× speedup for special cases' while §7.2.5 states 'an acceleration factor of up to 50× relative to NumPy'; these numbers conflict. The HPTT comparison should either be added to the experiments or removed from the claims, and the speedup figures should be reconciled, with the exact configurations for the maximum values identified.
minor comments (7)
  1. [Abstract, §1] The phrase 'general gases' appears in the abstract and the introduction; this should read 'general cases'.
  2. [§7] The formula for converting between the paper's permutation-map notation and the NumPy/PyTorch convention is garbled: '(n−1,...,n−1,n−1)−(σ_{n−1},...,σ_1,σ_0)' is not a valid expression. Please provide an explicit, correct conversion.
  3. [§7.2] The experiments do not list the exact software versions (GCC, NumPy, PyTorch) or compiler flags, which makes the performance results hard to reproduce.
  4. [Table 1] The abstract's phrase 'arbitrary instruction sets' is broader than the supported parameter space in Table 1, which lists only x86 AVX, ARM SVE, and Sunway SIMD; please qualify the claim.
  5. [Figure 5/6/9] Speedup ratios are reported without raw times or error bars beyond min/max in Figure 9; please report the mean and range or interquartile spread, and clarify what each panel of Figure 5 plots.
  6. [§7.1] The randomized correctness testing is described only qualitatively; providing the test-generation procedure, seed, and a shortlist of shapes would make the validation reproducible.
  7. [§7.2.1] The terms 'special cases' and 'general cases' are used for speedup claims but never defined precisely; please define them and identify which configurations produce the maximum speedup.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: GenTT's complexity bound and speedups are derived from the algorithm structure and measured against external baselines, not fitted to or defined by the claimed results.

full rationale

The paper's central claims are algorithmic and empirical rather than circular. The worst-case complexity O(N log2 w / w) is derived from the structural design: each w-lane block is permuted with at most log2 w shuffle steps per w elements, and all elements are loaded and stored once. This bound is not fitted to data and does not assume the conclusion. The shuffle-count derivation is self-contained, using the butterfly-network communication pattern with external references [2,15]. Performance claims are validated against external baselines (NumPy, PyTorch, GCC auto-vectorization, HPTT) on x86, ARM, and Sunway, and no fitted parameter is renamed as a prediction. The two self-citations ([5] and [6]) concern quantum simulation and tensor-network contraction contexts and are not load-bearing for the permutation framework's correctness or complexity. The paper's weaker points, such as the assumption that suitable p and q blocks always exist for arbitrary shapes after padding and merging, are potential correctness or generality limitations, not circular reasoning: they do not make the derivation equivalent to its inputs. Therefore the appropriate circularity score is 0.

Assumptions & free parameters 0 free parameters · 4 assumptions · 0 invented entities

The method rests on algorithmic building blocks from SIMD hardware and prior compiler research; no scalar parameters were fitted to experimental data. The main unexamined assumptions are the universal validity of block selection and the performance idealization of unaligned accesses.

assumptions (4)
  • standard math Reshaping a tensor into decomposed power-of-two sub-indices is an O(1) view and does not change memory layout.
    Section 5.1 invokes reshape to slice dimensions into binary sub-indices; this is a linear-index reinterpretation, valid because the underlying layout is unchanged.
  • domain assumption Unaligned load/store instructions (uload/ustore) incur no performance loss on x86 and ARM.
    Section 5.2 states this to justify not designing a general alignment strategy; on many x86 and ARM cores unaligned accesses are nearly as fast within a cache line, but performance can degrade at cache-line or page boundaries, so this is an idealization.
  • standard math Any permutation of a length-w register block can be realized by log2 w butterfly shuffle steps.
    Section 4.2 borrows the butterfly network result from references [2] and [15]; for tensor-index swapping this is exact, but it assumes shuffle instructions support arbitrary two-source element selection, which holds for the targeted ISAs.
  • ad hoc to paper Dimension composition (merging adjacent unchanged dims) always reduces padding waste and can be applied without changing the permutation's effect.
    Section 5.1 describes merging as a pre-reshape heuristic; it improves packing but is not guaranteed to find a valid block for every shape, and the paper does not prove a fallback.

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Cite this review

Pith. "Pith review of GenTT: Generate Vectorized Codes for General Tensor Permutation." pith.science (2026). https://pith.science/paper/UFF5FTNW

@misc{pith2026250603686,
  author       = {Pith},
  title        = {Pith review of: GenTT: Generate Vectorized Codes for General Tensor Permutation},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/UFF5FTNW}},
  note         = {Machine review of arXiv:2506.03686}
}
abstract

Tensor permutation is a fundamental operation widely applied in AI, tensor networks, and related fields. However, it is extremely complex, and different shapes and permutation maps can make a huge difference. SIMD permutation began to be studied in 2006, but the best method at that time was to split complex permutations into multiple simple permutations to do SIMD, which might increase the complexity for very complex permutations. Subsequently, as tensor contraction gained significant attention, researchers explored structured permutations associated with tensor contraction. Progress on general permutations has been limited, and with increasing SIMD bit widths, achieving efficient performance for these permutations has become increasingly challenging. We propose a SIMD permutation toolkit, \system, that generates optimized permutation code for arbitrary instruction sets, bit widths, tensor shapes, and permutation patterns, while maintaining low complexity. In our experiments, \system is able to achieve up to $38\times$ speedup for special cases and $5\times$ for general gases compared to Numpy.

Figures

Figures reproduced from arXiv: 2506.03686 by the authors.

Figure 1
Figure 1. Matrix transposition with tiling. The whole matrix [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Tiling framework of tensor permutation, targeting tensors with all dimensions of size 2. Vector length [PITH_FULL_IMAGE:figures/full_fig_p005_2.png] view at source ↗
Figure 3
Figure 3. Local permutation by multi-step shuffle. [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figures from the paper (5 more)
Figure 4
Figure 4. Figure 4: The unaligned storing avoiding unsafe overwriting. [PITH_FULL_IMAGE:figures/full_fig_p006_4.png]
Figure 5
Figure 5. Figure 5: Time results and speedup ratios of tensors with different shapes. Two shapes with three permutation maps are selected [PITH_FULL_IMAGE:figures/full_fig_p009_5.png]
Figure 7
Figure 7. Figure 7: The performance improvement of loop unrolling [PITH_FULL_IMAGE:figures/full_fig_p009_7.png]
Figure 8
Figure 8. Figure 8: Time consumed and speedup comparing with GCC [PITH_FULL_IMAGE:figures/full_fig_p010_8.png]
Figure 9
Figure 9. Figure 9: The performance results of cross-platform testing. [PITH_FULL_IMAGE:figures/full_fig_p010_9.png]

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Works this paper leans on

38 extracted references · 35 canonical work pages

  1. [1]

    Andrew Anderson, Avinash Malik, and David Gregg. 2015. Automatic vectoriza- tion of interleaved data revisited.ACM Transactions on Architecture and Code Optimization (TACO)12, 4 (2015), 1–25

    work page 2015

  2. [2]

    Aythan Avior, Tiziana Calamoneri, Shimon Even, Ami Litman, and Arnold L Rosenberg. 1996. A tight layout of the butterfly network. InProceedings of the eighth annual ACM symposium on Parallel Algorithms and Architectures. 170–175

    work page 1996

  3. [3]

    Sara S Baghsorkhi, Nalini Vasudevan, and Youfeng Wu. 2016. FlexVec: Auto- vectorization for irregular loops. InProceedings of the 37th ACM SIGPLAN Con- ference on Programming Language Design and Implementation. 697–710

    work page 2016

  4. [4]

    Bryan Catanzaro, Alexander Keller, and Michael Garland. 2014. A decomposition for in-place matrix transposition.ACM SIGPLAN Notices49, 8 (2014), 193–206

    work page 2014

  5. [5]

    Yaojian Chen, Yong Liu, Xinmin Shi, Jiawei Song, Xin Liu, Lin Gan, Chu Guo, Haohuan Fu, Jie Gao, Dexun Chen, et al. 2023. Lifetime-based optimization for simulating quantum circuits on a new sunway supercomputer. InProceedings of the 28th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming. 148–159

    work page 2023

  6. [6]

    Yaojian Chen, Zhaoqi Sun, Chengyu Qiu, Zegang Li, Yanfei Liu, Lin Gan, Xiaohui Duan, and Guangwen Yang. 2025. SW-TNC : Reaching the Most Complex Random Quantum Circuit via Tensor Network Contraction. arXiv:2504.09186 [cs.DC] https://arxiv.org/abs/2504.09186

    arXiv 2025

  7. [7]

    Kai-Jung Cheng and Che-Rung Lee. 2025. ITTPD: In-place Tensor Transposition with Permutation Decomposition on GPUs. InProceedings of the International Conference on High Performance Computing in Asia-Pacific Region. 90–98

    work page 2025

  8. [8]

    Alexandre E Eichenberger, Peng Wu, and Kevin O’brien. 2004. Vectorization for SIMD architectures with alignment constraints.Acm sigplan notices39, 6 (2004), 82–93. GenTT: Generate Vectorized Codes for General Tensor Permutation Conference’17, July 2017, Washington, DC, USA

    work page 2004

Show all 38 references
  1. [9]

    2002.Computational methods for fluid dynamics

    Joel H Ferziger and Milovan Perić. 2002.Computational methods for fluid dynamics. Springer

    2002

  2. [10]

    Franz Franchetti and Markus Puschel. 2007. SIMD vectorization of non-two- power sized FFTs. In2007 IEEE International Conference on Acoustics, Speech and Signal Processing-ICASSP’07, Vol. 2. IEEE, II–17

    2007

  3. [11]

    Franz Franchetti and Markus Püschel. 2008. Generating SIMD vectorized permu- tations. InInternational Conference on Compiler Construction. Springer, 116–131

    2008

  4. [12]

    Fred G Gustavson and David W Walker. 2019. Algorithms for in-place matrix transposition.Concurrency and Computation: Practice and Experience31, 13 (2019), e5071

    2019

  5. [13]

    Libo Huang, Li Shen, and Zhiying Wang. 2010. Permutation optimization for SIMD devices. InProceedings of 2010 IEEE International Symposium on Circuits and Systems. IEEE, 3849–3852

    2010

  6. [14]

    Antti-Pekka Hynninen and Dmitry I Lyakh. 2017. cutt: A high-performance tensor transpose library for cuda compatible gpus.arXiv preprint arXiv:1705.01598 (2017)

    2017 arXiv

  7. [15]

    Daniele Izzi and Annalisa Massini. 2023. Realizing Optimal All-to-All Personalized Communication Using Butterfly-Based Networks.IEEE Access11 (2023), 51064– 51083

    2023

  8. [16]

    Martin Kong, Richard Veras, Kevin Stock, Franz Franchetti, Louis-Noël Pouchet, and Ponnuswamy Sadayappan. 2013. When polyhedral transformations meet SIMD code generation. InProceedings of the 34th ACM SIGPLAN conference on Programming language design and implementation. 127–138

    2013

  9. [17]

    Fang Li, Xin Liu, Yong Liu, Pengpeng Zhao, Yuling Yang, Honghui Shang, Weizhe Sun, Zhen Wang, Enming Dong, and Dexun Chen. 2021. SW_Qsim: A minimize- memory quantum simulator with high-performance on a new sunway super- computer. InProceedings of the International Conference f...

    2021

  10. [18]

    Dmitry I Lyakh. 2015. An efficient tensor transpose algorithm for multicore CPU, Intel Xeon Phi, and NVidia Tesla GPU.Computer Physics Communications189 (2015), 84–91

    2015

  11. [19]

    2024.Vectron: A Dynamic Programming Auto- Vectorization Framework

    Sourena Naser Moghaddasi. 2024.Vectron: A Dynamic Programming Auto- Vectorization Framework. Ph. D. Dissertation. University of Victoria

    2024

  12. [20]

    Dorit Nuzman, Ira Rosen, and Ayal Zaks. 2006. Auto-vectorization of interleaved data for SIMD.ACM SIGPLAN Notices41, 6 (2006), 132–143

    2006

  13. [21]

    Gang Ren, Peng Wu, and David Padua. 2006. Optimizing data permutations for SIMD devices.ACM SIGPLAN Notices41, 6 (2006), 118–131

    2006

  14. [22]

    Christopher Rodrigues, Amarin Phaosawasdi, and Peng Wu. 2018. Simdization of small tensor multiplication kernels for wide SIMD vector processors. InProceed- ings of the 2018 4th Workshop on Programming Models for SIMD/Vector Processing. 1–8

    2018

  15. [23]

    Yang Shi, Uma Naresh Niranjan, Animashree Anandkumar, and Cris Cecka. 2016. Tensor contractions with extended BLAS kernels on CPU and GPU. In2016 IEEE 23rd International Conference on High Performance Computing (HiPC). IEEE, 193–202

    2016

  16. [24]

    Edgar Solomonik, Devin Matthews, Jeff Hammond, and James Demmel. 2013. Cyclops tensor framework: Reducing communication and eliminating load imbal- ance in massively parallel contractions. In2013 IEEE 27th International Symposium on Parallel and Distributed Processing. IEEE, 813–824

    2013

  17. [25]

    Paul Springer and Paolo Bientinesi. 2018. Design of a high-performance GEMM- like tensor–tensor multiplication.ACM Transactions on Mathematical Software (TOMS)44, 3 (2018), 1–29

    2018

  18. [26]

    Paul Springer, Jeff R Hammond, and Paolo Bientinesi. 2017. TTC: A high- performance compiler for tensor transpositions.ACM Transactions on Mathe- matical Software (TOMS)44, 2 (2017), 1–21

    2017

  19. [27]

    Paul Springer, Tong Su, and Paolo Bientinesi. 2017. HPTT: A high-performance tensor transposition C++ library. InProceedings of the 4th ACM SIGPLAN Interna- tional Workshop on Libraries, Languages, and Compilers for Array Programming. 56–62

    2017

  20. [28]

    Kevin Stock, Tom Henretty, Iyyappa Murugandi, P Sadayappan, and Robert Harrison. 2011. Model-driven simd code generation for a multi-resolution tensor kernel. In2011 IEEE International Parallel & Distributed Processing Symposium. IEEE, 1058–1067

    2011

  21. [29]

    I-Jui Sung, Juan Gómez-Luna, José María González-Linares, Nicolás Guil, and Wen-Mei W Hwu. 2014. In-place transposition of rectangular matrices on accel- erators.ACM SIGPLAN Notices49, 8 (2014), 207–218

    2014

  22. [30]

    Jubi Taneja, Avery Laird, Cong Yan, Madan Musuvathi, and Shuvendu K Lahiri

  23. [31]

    Konrad Trifunovic, Dorit Nuzman, Albert Cohen, Ayal Zaks, and Ira Rosen. 2009. Polyhedral-model guided loop-nest auto-vectorization. In2009 18th International Conference on Parallel Architectures and Compilation Techniques. IEEE, 327–337

    2009

  24. [32]

    Jyothi Vedurada, Arjun Suresh, Aravind Sukumaran Rajam, Jinsung Kim, Chang- wan Hong, Ajay Panyala, Sriram Krishnamoorthy, V Krishna Nandivada, Ro- hit Kumar Srivastava, and P Sadayappan. 2018. TTLG-an efficient tensor trans- position library for GPUs. In2018 IEEE Internationa...

    2018

  25. [33]

    Lai Wei and John Mellor-Crummey. 2014. Autotuning tensor transposition. In 2014 IEEE International Parallel & Distributed Processing Symposium Workshops. IEEE, 342–351

    2014

  26. [34]

    Chun-Yu Wu, Chih-Chieh Tu, Kai-Jung Cheng, and Che-Rung Lee. 2025. EI- THOT: Efficient In-place Transposition of High Order Tensors on GPUs.ACM Transactions on Parallel Computing12, 1 (2025), 1–22

    2025

  27. [35]

    Wang Xu, Zhang Yan, and Ding Shunying. 2011. A high performance FFT library with single instruction multiple data (SIMD) architecture. In2011 International Conference on Electronics, Communications and Control (ICECC). IEEE, 630–633

    2011

  28. [36]

    Lanmin Zheng and Tianqi Chen. 2018. Optimizing deep learning workloads on ARM GPU with TVM. InProceedings of the 1st on Reproducible Quality-Efficient Systems Tournament on Co-Designing Pareto-Efficient Deep Learning. 1

    2018

  29. [37]

    Zhongchun Zheng, Long Cheng, Lu Li, Rodrigo CO Rocha, Tianyi Liu, Wei Wei, Xianwei Zhang, and Yaoqing Gao. 2025. VecTrans: LLM Transformation Framework for Better Auto-vectorization on High-performance CPU.arXiv preprint arXiv:2503.19449(2025)

    2025 arXiv

  30. [2025]

    InProceedings of the 23rd ACM/IEEE International Symposium on Code Generation and Optimization

    Llm-vectorizer: Llm-based verified loop vectorizer. InProceedings of the 23rd ACM/IEEE International Symposium on Code Generation and Optimization. 137–149

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