pith. machine review for the scientific record.
sign in

arxiv: 2510.23519 · v3 · submitted 2025-10-27 · 🪐 quant-ph · cs.AR

Architecting Scalable Trapped Ion Quantum Computers using Surface Codes

Scott Jones , Prakash Murali (University of Cambridge) This is my paper

Pith reviewed 2026-05-18 04:13 UTC · model grok-4.3

classification 🪐 quant-ph cs.AR
keywords trapped ionssurface codesquantum error correctionQCCD architecturequantum compilationhardware optimizationscalability
0
0 comments X

The pith

Two-ion traps prove optimal for implementing surface codes on scalable trapped-ion quantum hardware.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper establishes that QCCD-based trapped-ion systems can implement surface codes most efficiently by using traps that hold only two ions each. A new compilation method that respects the physical topology of ion movement and connectivity achieves logical operation speeds 3.8 times higher than prior compilers. This finding contradicts the earlier expectation that larger traps holding 20 to 30 ions would scale better. If the result holds, designers can build future systems with simpler electrode layouts and lower hardware overhead while still reaching the error rates needed for useful computation. The work focuses on how trap size, connectivity, and wiring choices affect the speed of logical qubits built from many physical ions.

Core claim

By building a topology-aware compiler that maps surface-code stabilizer measurements onto QCCD shuttling constraints, the authors show that two-ion traps simultaneously maximize logical clock rate and minimize electrode wiring complexity. This configuration outperforms both larger ion chains and alternative connectivity patterns under realistic near-term error rates of 10^{-3} to 10^{-4}.

What carries the argument

A near-optimal topology-aware compiler that schedules surface-code operations while accounting for ion shuttling times and trap connectivity constraints.

If this is right

  • Future QCCD hardware can use simpler electrode wiring focused on two-ion units rather than complex multi-ion chains.
  • Logical qubits can reach target speeds without requiring large ion numbers per trap.
  • Connectivity graphs can be optimized around nearest-neighbor shuttling between two-ion modules.
  • Overall device scaling becomes feasible at lower fabrication cost and complexity.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same compiler-driven approach could be applied to other error-correcting codes to test whether two-ion optimality is surface-code specific.
  • Modular designs built from many independent two-ion traps may reduce crosstalk and heating effects that grow with trap size.

Load-bearing premise

The performance comparisons assume specific ion movement times and gate error rates that will be realized in future fabricated QCCD devices.

What would settle it

Fabricate and benchmark a small QCCD array containing both two-ion and twenty-ion traps, then measure whether the two-ion layout actually produces higher logical operation rates under the same gate and shuttling error rates.

Figures

Figures reproduced from arXiv: 2510.23519 by Prakash Murali (University of Cambridge), Scott Jones.

Figure 1
Figure 1. Figure 1: Quantum Charge-Coupled Device (QCCD) system. A detailed view of the QCCD hardware, where ions (grey circles) serve as qubits and are confined within an electromagnetic field known as a trap. (a) The trap is structured with different types of electrodes to position ions, including dynamic electrodes (green) for time-varying signals and shim electrodes (blue) for static potentials. Transport segments (black)… view at source ↗
Figure 2
Figure 2. Figure 2: Framework for evaluating the suitability of a can￾didate QCCD-based TI system for error correction. Taking a candidate architecture and a candidate QEC code as in￾put, the tool flow computes error correction metrics such as logical error rate, QEC round time and power dissipation requirements by using a QEC and device topology-aware compiler, QCCD simulator, and realistic models for perfor￾mance and resour… view at source ↗
Figure 3
Figure 3. Figure 3: The topology of the distance four surface code. The blue circles represent physical data qubits, and the red circles represent physical ancilla qubits. Data qubits form the vertices of the cells that make up the shaded surface, and there is exactly one ancilla qubit in the centre of every cell. The cells are shaded purple or green to disambiguate the two types of parity checks, with each type of circuit gi… view at source ↗
Figure 4
Figure 4. Figure 4: (a) Each electrode is connected to a dedicated DAC in the standard architecture, resulting in a direct but highly resource-intensive wiring scheme. (b) The WISE architecture integrates an ion trap with a switch-based demultiplexing network, significantly altering the scaling of control elec￾tronics. All dynamic electrodes (green) are controlled with ≈ 100 DACs irrespective of system size by using a switch … view at source ↗
Figure 5
Figure 5. Figure 5: QCCD compilation flow: from a distance 2 surface code (syndrome extraction) circuit (top-left) and QCCD device configuration (top-right) to a scheduled, executable QCCD program. Steps include translation to native gates, qubit-to-ion mapping, ion routing using the movement primitives from the QCCD toolbox (§2), and scheduling using the operation timings in [PITH_FULL_IMAGE:figures/full_fig_p005_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: This minimises ancilla movement between traps [PITH_FULL_IMAGE:figures/full_fig_p005_6.png] view at source ↗
Figure 6
Figure 6. Figure 6: Mapping qubits to ions. Given a distance 4 surface code (left) and a QCCD device with trap capacity 9, we first partition into 𝑐𝑒𝑖𝑙(𝑁𝑞𝑢𝑏𝑖𝑡𝑠/(𝑐𝑎𝑝𝑎𝑐𝑖𝑡𝑦 − 1)) = 𝑐𝑒𝑖𝑙(31/8) = 4 clusters of qubits by top-down regular partitioning of the code topology (recursively bisecting the code’s qubit layout). The surface code’s regular structure means neighbouring qubits that share entanglement operations are likely group… view at source ↗
Figure 7
Figure 7. Figure 7: Ion Routing. (1) Gates that are not blocked by other unscheduled gates and do not need routing are scheduled. (2) The destination traps for each ancilla qubit are determined based on their next operation. Routing paths are allocated sequentially to ancilla qubits, prioritising those needed ear￾lier in the input gate sequence. (3) Finds a path for ancilla A1, with each component along the path (except the s… view at source ↗
Figure 8
Figure 8. Figure 8: (a) compares QEC round time as a function of code distance for the linear, grid, and all-to-all switch communica￾tion topologies. We show the results for capacities of 2, 5 and 12, but the trends are similar for other capacities. We make three observations. First, the linear topology exhibits high [PITH_FULL_IMAGE:figures/full_fig_p010_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: QEC shot time (y-axis) as a function of trap capac￾ity (marked by the legend) and code distance (x-axis). The lower bound (grey dotted) corresponds to the minimal time required (2.5𝑚𝑠) for a single round of surface code parity￾check operations when there are no ion reconfigurations, and there is complete parallelism. The upper bound repre￾sents the elapsed time when all ions are in the same trap, causing c… view at source ↗
Figure 10
Figure 10. Figure 10: Projections of logical error rate versus code dis￾tance for the surface code on a QCCD grid topology at differ￾ent levels of gate improvement. The target logical error rate of 10−9 is used to assess practical feasibility, with the x-axis intercept indicating the code distance required to achieve this target. The three axes show projections for 1X, 5X and 10X gate improvements, respectively. code. We use t… view at source ↗
Figure 12
Figure 12. Figure 12: Hardware requirements for achieving a target log￾ical error rate under a 5x gate improvement scenario across different trap capacities (𝑐). The axis shows the required data rate between the QPU and the controller. A trap capacity of 𝑐 = 2 minimises both power dissipation and data rate demands at a logical error rate of 10−9 . However, even in this optimal case, achieving 10−9 necessitates an impractical 1… view at source ↗
Figure 11
Figure 11. Figure 11: Projected number of electrodes required to achieve a target logical error rate under a 5x gate improve￾ment scenario for different trap capacities. Impact on hardware footprint [PITH_FULL_IMAGE:figures/full_fig_p012_11.png] view at source ↗
Figure 13
Figure 13. Figure 13: (b) compares the elapsed time at different logical error rates. For the WISE architecture, the elapsed time scales in proportion to the desired logical error rate. For every 10X improvement desired in the logical error rate, the elapsed time increases by 1.17X. WISE suffers from limited transport flexibility, allowing only one transport operation at a time. Under an odd-even sort global reconfiguration sc… view at source ↗
read the original abstract

Trapped ion (TI) qubits are a leading quantum computing platform. Current TI systems have less than 60 qubits, but a modular architecture known as the Quantum Charge-Coupled Device (QCCD) is a promising path to scale up devices. There is a large gap between the error rates of near-term systems ($10^{-3}$ to $10^{-4}$) and the requirements of practical applications (below $10^{-9}$). To bridge this gap, we require Quantum Error Correction (QEC) to build logical qubits that are composed of multiple physical qubits. While logical qubits have been demonstrated on TI qubits, these demonstrations are restricted to small codes and systems. There is no clarity on how QCCD systems should be designed to implement practical-scale QEC. This paper studies how surface codes, a standard QEC scheme, can be implemented efficiently on QCCD-based systems. To examine how architectural parameters of a QCCD system can be tuned for surface codes, we develop a near-optimal topology-aware compilation method that outperforms existing QCCD compilers by an average of 3.8X in terms of logical clock speed. We use this compiler to examine how hardware trap capacity, connectivity and electrode wiring choices can be optimised for surface code implementation. In particular, we demonstrate that small traps of two ions are surprisingly ideal from both a performance-optimal and hardware-efficiency standpoint. This result runs counter to prior intuition that larger traps (20-30 ions) would be preferable, and has the potential to inform design choices for upcoming systems.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The paper presents a near-optimal topology-aware compiler for implementing surface codes on QCCD trapped-ion architectures, claiming an average 3.8X improvement in logical clock speed over prior QCCD compilers. Using this compiler, the authors systematically vary hardware parameters including trap capacity, connectivity, and electrode wiring, and conclude that two-ion traps are optimal from both performance and hardware-efficiency perspectives, contrary to prior intuition favoring 20-30 ion traps.

Significance. If the modeling assumptions hold and the compiler results are robust, the work could meaningfully inform design choices for scalable trapped-ion systems by suggesting simpler small-trap architectures that still support efficient surface-code QEC. The compiler improvement and the counter-intuitive trap-size finding are the primary contributions; the paper also provides a concrete study of architectural trade-offs for near-term error rates.

major comments (2)
  1. [Abstract] Abstract: the central claim that two-ion traps are both performance-optimal and hardware-efficient rests on specific modeled costs for ion shuttling times, gate error rates in the 10^{-3}–10^{-4} range, and QCCD connectivity constraints. No sensitivity analysis or calibration against existing QCCD prototypes is indicated, yet deviations in real shuttling latencies or wiring overheads could reverse the optimality conclusion and favor larger traps.
  2. [Results/Methods] The performance numbers and trap-size optimality conclusion are outputs of the authors' compiler simulations. Without detailed methods, validation data, or error-bar reporting, it remains unclear whether post-hoc tuning or unstated modeling choices affect the 3.8X speedup and the trap-capacity result; this is load-bearing for the main architectural recommendation.
minor comments (2)
  1. Clarify the precise definition and measurement of 'logical clock speed' early in the text, including how shuttling and gate operations are aggregated.
  2. The abstract states the compiler 'outperforms existing QCCD compilers by an average of 3.8X'; provide the baseline compilers and workload details in a dedicated comparison section or table.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for their constructive comments on our manuscript. We address each major comment point by point below, providing the strongest honest defense of our work while agreeing to revisions that improve clarity and robustness without misrepresenting the results.

read point-by-point responses

  1. Referee: [Abstract] Abstract: the central claim that two-ion traps are both performance-optimal and hardware-efficient rests on specific modeled costs for ion shuttling times, gate error rates in the 10^{-3}–10^{-4} range, and QCCD connectivity constraints. No sensitivity analysis or calibration against existing QCCD prototypes is indicated, yet deviations in real shuttling latencies or wiring overheads could reverse the optimality conclusion and favor larger traps.

    Authors: The modeled parameters are drawn directly from published QCCD experimental results on shuttling latencies and gate fidelities in the cited range. We agree that explicit sensitivity analysis would strengthen the claim. In revision we will add a dedicated subsection varying shuttling time and wiring overhead across plausible experimental ranges and confirm that the two-ion optimality conclusion is robust within those bounds. Full experimental calibration of the model against a specific prototype lies outside the scope of this simulation study, but we will expand the text to cite the exact experimental sources and note this limitation. revision: yes

  2. Referee: [Results/Methods] The performance numbers and trap-size optimality conclusion are outputs of the authors' compiler simulations. Without detailed methods, validation data, or error-bar reporting, it remains unclear whether post-hoc tuning or unstated modeling choices affect the 3.8X speedup and the trap-capacity result; this is load-bearing for the main architectural recommendation.

    Authors: Section 3 presents the topology-aware compiler algorithm, cost model, and scheduling procedure in detail, with the 3.8X figure obtained from head-to-head comparison against the strongest prior QCCD compiler on the same surface-code benchmarks. To increase transparency we will expand the Methods section with additional pseudocode, an explicit table of all parameter values, and verification on small hand-solved instances. Because the simulations are deterministic given fixed hardware parameters, statistical error bars are not applicable; we will instead report results across multiple code distances and trap configurations to demonstrate consistency of the trap-size finding. revision: yes

Circularity Check

0 steps flagged

No significant circularity; results are simulation outputs under explicit assumptions

full rationale

The paper develops an independent topology-aware compiler, measures its 3.8X logical-clock-speed improvement over prior compilers, and then applies the compiler to evaluate architectural parameters including trap size. The conclusion favoring 2-ion traps emerges from these simulations under stated modeling assumptions for shuttling times, gate errors, and connectivity; it is not equivalent to any input by definition or construction. No self-definitional steps, fitted inputs renamed as predictions, or load-bearing self-citation chains appear in the derivation. The work remains self-contained as a modeling study whose central claims retain independent content from the chosen parameters.

Axiom & Free-Parameter Ledger

1 free parameters · 1 axioms · 0 invented entities

The central claims rest on a hardware model of QCCD shuttling costs and surface-code gate schedules whose accuracy is not independently verified in the provided abstract; no new physical entities are postulated.

free parameters (1)
  • trap capacity parameter
    Trap sizes (including the favored 2-ion case) are varied as design choices rather than fitted constants, but the performance optimum depends on the assumed shuttling and gate timing model.
axioms (1)
  • domain assumption Surface-code logical operations can be scheduled using the QCCD ion shuttling primitives without additional unmodeled overheads
    Invoked when the compiler maps surface-code circuits onto the trap layout.

pith-pipeline@v0.9.0 · 5804 in / 1311 out tokens · 35692 ms · 2026-05-18T04:13:02.984888+00:00 · methodology

discussion (0)

Sign in with ORCID, Apple, or X to comment. Anyone can read and Pith papers without signing in.

Forward citations

Cited by 1 Pith paper

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score.

  1. High-Fidelity Raman Spin-Dependent Kicks in the Presence of Micromotion

    quant-ph 2025-11 unverdicted novelty 6.0

    A scheme using modulated Raman pulses achieves spin-dependent kick infidelities below 10^{-5} in trapped ions despite micromotion by optimizing RF parameters to cancel backward kicks.

Reference graph

Works this paper leans on

37 extracted references · 37 canonical work pages · cited by 1 Pith paper

  1. [1]

    Andersen, Markus Ansmann, Frank Arute, Kunal Arya, Abraham Asfaw, Juan Atalaya, Ryan Babbush, Dave Bacon, Joseph C

    Rajeev Acharya, Igor Aleiner, Richard Allen, Trond I. Andersen, Markus Ansmann, Frank Arute, Kunal Arya, Abraham Asfaw, Juan Atalaya, Ryan Babbush, Dave Bacon, Joseph C. Bardin, Joao Basso, Andreas Bengtsson, Sergio Boixo, Gina Bortoli, Alexandre Bourassa, Jenna Bovaird, Leon Brill, Michael Broughton, Bob B. Buckley, David A. Buell, Tim Burger, Brian Burk...

    work page 2023

  2. [2]

    Google Quantum AI. 2025. Google Quantum AI Roadmap.https: //quantumai.google/roadmap

    work page 2025

  3. [3]

    Konstantin Andreev and Harald Räcke. 2006. Balanced graph par- titioning.Theory of Computing Systems39, 6 (Nov. 2006), 929–939. doi:10.1007/s00224-006-1350-7Funding Information: This work was supported by the NSF under Grants CCR-0085982 and CCR-0122581∗

    work page doi:10.1007/s00224-006-1350-7funding 2006

  4. [4]

    Barnes, Tomasz Bialas, Okan Buğdaycı, Earl T

    Ben Barber, Kenton M. Barnes, Tomasz Bialas, Okan Buğdaycı, Earl T. Campbell, Neil I. Gillespie, Kauser Johar, Ram Rajan, Adam W. Richard- son, Luka Skoric, Canberk Topal, Mark L. Turner, and Abbas B. Ziad

    work page

  5. [5]

    2025), 84–91

    A real-time, scalable, fast and resource-efficient decoder for a quantum computer.Nature Electronics8, 1 (Jan. 2025), 84–91. doi:10.1038/s41928-024-01319-5

    work page doi:10.1038/s41928-024-01319-5 2025

  6. [6]

    Bowler, J

    R. Bowler, J. Gaebler, Y. Lin, T. R. Tan, D. Hanneke, J. D. Jost, J. P. Home, D. Leibfried, and D. J. Wineland. 2012. Coherent Diabatic Ion Transport and Separation in a Multizone Trap Array.Phys. Rev. Lett. 109 (Aug 2012), 080502. Issue 8. doi:10.1103/PhysRevLett.109.080502

    work page doi:10.1103/physrevlett.109.080502 2012

  7. [7]

    Hoffman, Abigail R

    William Cody Burton, Brian Estey, Ian M. Hoffman, Abigail R. Perry, Curtis Volin, and Gabriel Price. 2023. Transport of Multispecies Ion Crystals through a Junction in a Radio-Frequency Paul Trap.Physical Review Letters130, 17 (April 2023). doi:10.1103/physrevlett.130.173202

    work page doi:10.1103/physrevlett.130.173202 2023

  8. [8]

    Jwo-Sy Chen, Erik Nielsen, Matthew Ebert, Volkan Inlek, Kenneth Wright, Vandiver Chaplin, Andrii Maksymov, Eduardo Páez, Amrit Poudel, Peter Maunz, and John Gamble. 2024. Benchmarking a trapped- ion quantum computer with 30 qubits.Quantum8 (Nov. 2024), 1516. doi:10.22331/q-2024-11-07-1516

    work page doi:10.22331/q-2024-11-07-1516 2024

  9. [9]

    Caroline Figgatt. 2018. Building and Programming a Universal Ion Trap Quantum Computer. (2018)

    work page 2018

  10. [10]

    Figgatt, A

    C. Figgatt, A. Ostrander, N. M. Linke, K. A. Landsman, D. Zhu, D. Maslov, and C. Monroe. 2019. Parallel entangling operations on a universal ion-trap quantum computer.Nature572, 7769 (July 2019), 368–372. doi:10.1038/s41586-019-1427-5

    work page doi:10.1038/s41586-019-1427-5 2019

  11. [11]

    Fowler and Craig Gidney

    Austin G. Fowler and Craig Gidney. 2018. Low overhead quantum computation using lattice surgery.arXiv: Quantum Physics(2018). https://api.semanticscholar.org/CorpusID:119447706

    work page 2018

  12. [12]

    Garey and David S

    Michael R. Garey and David S. Johnson. 1979.Computers and In- tractability: A Guide to the Theory of NP-Completeness. W.H. Freeman and Co., San Francisco, CA

    work page 1979

  13. [13]

    Craig Gidney. 2021. Stim: a fast stabilizer circuit simulator.Quantum 5 (July 2021), 497. doi:10.22331/q-2021-07-06-497

    work page doi:10.22331/q-2021-07-06-497 2021

  14. [14]

    Gutiérrez, M

    M. Gutiérrez, M. Müller, and A. Bermúdez. 2019. Transversality and lattice surgery: Exploring realistic routes toward coupled logical qubits with trapped-ion quantum processors.Phys. Rev. A99 (Feb 2019), 022330. Issue 2. doi:10.1103/PhysRevA.99.022330

    work page doi:10.1103/physreva.99.022330 2019

  15. [15]

    IBM. 2025. IBM Quantum Roadmap.https://www.ibm.com/roadmaps/ quantum/

    work page 2025

  16. [16]

    Oxford Ionics. 2025. Oxford Ionics | High Performance Quantum Computing.https://www.oxionics.com/

    work page 2025

  17. [17]

    IonQ. 2025. IonQ | Trapped Ion Quantum Computing.https://ionq. com/

    work page 2025

  18. [18]

    Kielpinski, C

    D. Kielpinski, C. Monroe, and D. J. Wineland. 2002. Architecture for a large-scale ion-trap quantum computer.Nature417, 6890 (01 Jun 2002), 709–711. doi:10.1038/nature00784 14 Architecting Scalable Trapped Ion Quantum Computers using Surface Codes

    work page doi:10.1038/nature00784 2002

  19. [19]

    Harold W. Kuhn. 1955. The Hungarian Method for the Assignment Problem.Naval Research Logistics Quarterly2, 1–2 (March 1955), 83–97. doi:10.1002/nav.3800020109

    work page doi:10.1002/nav.3800020109 1955

  20. [20]

    Bennink, Justin G

    Tyler Leblond, Ryan S. Bennink, Justin G. Lietz, and Christopher M. Seck. 2023. TISCC: A Surface Code Compiler and Resource Estimator for Trapped-Ion Processors. InProceedings of the SC ’23 Workshops of the International Conference on High Performance Computing, Network, Storage, and Analysis (SC-W 2023). ACM, 1426–1435. doi:10.1145/ 3624062.3624214

    work page arXiv 2023

  21. [21]

    Fowler, Klaus Mølmer, Simon J

    Bjoern Lekitsch, Sebastian Weidt, Austin G. Fowler, Klaus Mølmer, Simon J. Devitt, Christof Wunderlich, and Winfried K. Hensinger. 2017. Blueprint for a microwave trapped ion quantum computer.Science Advances3, 2 (Feb. 2017). doi:10.1126/sciadv.1601540

    work page doi:10.1126/sciadv.1601540 2017

  22. [22]

    Pak Hong Leung and Kenneth R. Brown. 2018. Entangling an arbitrary pair of qubits in a long ion crystal.Phys. Rev. A98 (Sep 2018), 032318. Issue 3. doi:10.1103/PhysRevA.98.032318

    work page doi:10.1103/physreva.98.032318 2018

  23. [23]

    Malinowski, D.T.C

    M. Malinowski, D.T.C. Allcock, and C.J. Ballance. 2023. How to Wire a1000-Qubit Trapped-Ion Quantum Computer.PRX Quantum4 (Oct 2023), 040313. Issue 4. doi:10.1103/PRXQuantum.4.040313

    work page doi:10.1103/prxquantum.4.040313 2023

  24. [24]

    Monroe, R

    C. Monroe, R. Raussendorf, A. Ruthven, K. R. Brown, P. Maunz, L.- M. Duan, and J. Kim. 2014. Large-scale modular quantum-computer architecture with atomic memory and photonic interconnects.Phys. Rev. A89 (Feb 2014), 022317. Issue 2. doi:10.1103/PhysRevA.89.022317

    work page doi:10.1103/physreva.89.022317 2014

  25. [25]

    S. A. Moses, C. H. Baldwin, M. S. Allman, R. Ancona, L. Ascarrunz, C. Barnes, J. Bartolotta, B. Bjork, P. Blanchard, M. Bohn, J. G. Bohnet, N. C. Brown, N. Q. Burdick, W. C. Burton, S. L. Campbell, J. P. Campora, C. Carron, J. Chambers, J. W. Chan, Y. H. Chen, A. Chernoguzov, E. Chertkov, J. Colina, J. P. Curtis, R. Daniel, M. DeCross, D. Deen, C. Delaney...

    work page doi:10.1103/physrevx.13.041052 2023

  26. [26]

    S. A. Moses, C. H. Baldwin, M. S. Allman, R. Ancona, L. Ascarrunz, C. Barnes, J. Bartolotta, B. Bjork, P. Blanchard, M. Bohn, J. G. Bohnet, N. C. Brown, N. Q. Burdick, W. C. Burton, S. L. Campbell, J. P. Campora, C. Carron, J. Chambers, J. W. Chan, Y. H. Chen, A. Chernoguzov, E. Chertkov, J. Colina, J. P. Curtis, R. Daniel, M. DeCross, D. Deen, C. Delaney...

    work page 2023

  27. [27]

    Debroy, Kenneth R

    Prakash Murali, Dripto M. Debroy, Kenneth R. Brown, and Margaret Martonosi. 2020. Architecting Noisy Intermediate-Scale Trapped Ion Quantum Computers. arXiv:2004.04706 [quant-ph]https://arxiv.org/ abs/2004.04706

    work page arXiv 2020

  28. [28]

    Quantum Optics and Spectroscopy Institut für Experimentalphysik Universität Innsbruck. 2023. World list of QIP ion trapping groups.https://www.quantumoptics.at/images/miscellaneous/ IonTrappers.pdf

    work page 2023

  29. [29]

    J. M. Pino, J. M. Dreiling, C. Figgatt, J. P. Gaebler, S. A. Moses, M. S. Allman, C. H. Baldwin, M. Foss-Feig, D. Hayes, K. Mayer, C. Ryan- Anderson, and B. Neyenhuis. 2021. Demonstration of the trapped-ion quantum CCD computer architecture.Nature592, 7853 (April 2021), 209–213. doi:10.1038/s41586-021-03318-4

    work page doi:10.1038/s41586-021-03318-4 2021

  30. [30]

    Quantinuum. 2025. Quantinuum.https://www.quantinuum.com/

    work page 2025

  31. [31]

    Abdullah Ash Saki, Rasit Onur Topaloglu, and Swaroop Ghosh. 2022. Muzzle the Shuttle: Efficient Compilation for Multi-Trap Trapped-Ion Quantum Computers. In2022 Design, Automation & Test in Europe Conference & Exhibition (DATE). 322–327. doi:10.23919/DATE54114. 2022.9774619

    work page doi:10.23919/date54114 2022

  32. [32]

    Daniel Schoenberger, Stefan Hillmich, Matthias Brandl, and Robert Wille. 2024. Shuttling for Scalable Trapped-Ion Quantum Computers. arXiv:2402.14065 [quant-ph]https://arxiv.org/abs/2402.14065

    work page arXiv 2024

  33. [33]

    Seyon Sivarajah, Silas Dilkes, Alexander Cowtan, Will Simmons, Alec Edgington, and Ross Duncan. 2020. t|ket 〉: a retargetable compiler for NISQ devices.Quantum Science and Technology6, 1 (Nov. 2020), 014003. doi:10.1088/2058-9565/ab8e92

    work page doi:10.1088/2058-9565/ab8e92 2020

  34. [34]

    Marco Valentini, Martin W. van Mourik, Friederike Butt, Jakob Wahl, Matthias Dietl, Michael Pfeifer, Fabian Anmasser, Yves Colombe, Clemens Rössler, Philip Holz, Rainer Blatt, Markus Müller, Thomas Monz, and Philipp Schindler. 2024. Demonstration of two-dimensional connectivity for a scalable error-corrected ion-trap quantum processor architecture. arXiv:...

    work page arXiv 2024

  35. [35]

    Wim van Dam, Mariia Mykhailova, and Mathias Soeken. 2024. Using Azure Quantum Resource Estimator for Assessing Performance of Fault Tolerant Quantum Computation. arXiv:2311.05801 [quant-ph] https://arxiv.org/abs/2311.05801

    work page arXiv 2024

  36. [36]

    Walther, F

    A. Walther, F. Ziesel, T. Ruster, S. T. Dawkins, K. Ott, M. Hettrich, K. Singer, F. Schmidt-Kaler, and U. Poschinger. 2012. Controlling Fast Transport of Cold Trapped Ions.Phys. Rev. Lett.109 (Aug 2012), 080501. Issue 8. doi:10.1103/PhysRevLett.109.080501

    work page doi:10.1103/physrevlett.109.080501 2012

  37. [37]

    Anbang Wu, Gushu Li, Hezi Zhang, Gian Giacomo Guerreschi, Yufei Ding, and Yuan Xie. 2022. A synthesis framework for stitching surface code with superconducting quantum devices. InProceedings of the 49th Annual International Symposium on Computer Architecture(New York, New York)(ISCA ’22). Association for Computing Machinery, New York, NY, USA, 337–350. do...

    work page doi:10.1145/3470496.3527381 2022