arxiv: 2602.06523 · v2 · submitted 2026-02-06 · 💻 cs.CV · cs.HC

Recognition: 2 theorem links

· Lean Theorem

MicroBi-ConvLSTM: An Ultra-Lightweight Efficient Model for Human Activity Recognition on Resource Constrained Devices

Mridankan Mandal

Authors on Pith no claims yet

Pith reviewed 2026-05-16 07:14 UTC · model grok-4.3

classification 💻 cs.CV cs.HC

keywords Human Activity RecognitionLightweight Neural NetworksMicrocontroller DeploymentConvLSTMResource-Constrained DevicesOn-Device InferenceTinyML

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The pith

MicroBi-ConvLSTM deploys successfully on all eight HAR benchmarks across both Pico 2 and ESP32 microcontrollers with an average of 11.4K parameters.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper presents MicroBi-ConvLSTM as a convolutional recurrent architecture for human activity recognition that keeps the parameter count down to 11.4K on average. It does this by running two stages of convolution with 4x temporal pooling followed by one bidirectional LSTM layer. The design stays in linear time and delivers competitive accuracy on eight different benchmarks while fitting inside the memory limits of real microcontrollers after operating-system overhead. On-device tests show it is the only tested model that completes full coverage on both the Raspberry Pi Pico 2 and ESP32 platforms.

Core claim

MicroBi-ConvLSTM achieves full 8/8 dataset coverage on Raspberry Pi Pico 2 and ESP32 by reducing to 11.4K parameters on average through two-stage convolutional feature extraction with 4x temporal pooling and a single bidirectional LSTM layer, while preserving linear O(N) complexity and delivering 93.41 percent macro F1 on UCI-HAR, 94.46 percent on SKODA, and 88.98 percent on Daphnet together with 72.8 ms average latency on Pico 2 and 97.9 percent PyTorch parity on ESP32.

What carries the argument

two-stage convolutional feature extraction with 4x temporal pooling followed by a single bidirectional LSTM layer

If this is right

The architecture fits inside the SRAM budgets of common microcontrollers where TinierHAR and TinyHAR exceed limits after OS overhead.
Bidirectionality improves detection of episodic events such as gait freeze while adding little value on steady locomotion tasks.
Linear time complexity is retained while cutting parameters by roughly 2.9 times compared with TinierHAR.
The model provides the first architecture shown to reach complete coverage across the full set of eight benchmarks on both tested platforms.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

The same lightweight structure could support always-on activity tracking in low-cost wearables that never connect to the cloud.
If the eight benchmarks capture the main real-world patterns, the approach may transfer to other sensor streams such as environmental monitoring with only minor retraining.
Further tests on additional microcontroller variants would clarify whether the reported latency and parity numbers generalize beyond the two platforms examined.

Load-bearing premise

The reported parameter counts and accuracy figures continue to hold once operating-system overhead is added on the target microcontrollers and the eight chosen benchmarks are representative of real-world use without further tuning.

What would settle it

Running the model on the Raspberry Pi Pico 2 or ESP32 and finding either fewer than eight fully working datasets or average latency above the stated 72.8 ms on Pico 2 would disprove the full-deployment claim.

Figures

Figures reproduced from arXiv: 2602.06523 by Mridankan Mandal.

**Figure 1.** Figure 1: µBi-ConvLSTM architecture overview. Input sensor signals (C channels × T timesteps) pass through two convolutional blocks with batch normalization, ReLU activation, and 2× max pooling each, achieving 4× total temporal compression. A single bidirectional LSTM (hidden dimension 24) processes the compressed sequence, with the final timestep representation feeding the classification head. Parameter count varie… view at source ↗

**Figure 2.** Figure 2: Parameters, MACs, FLOPs, Model Size (in KB), F1-score per million MACs, and F1-score per thousand parameters distributions across architectures and datasets. Box plots show mean, and standard deviations across five random seeds. µBi-ConvLSTM (leftmost in each group) maintains competitive variance despite 2.9× fewer parameters than TinierHAR. TABLE VI: INT8 Quantization Impact on µBi-ConvLSTM Dataset FP32 F… view at source ↗

**Figure 5.** Figure 5: FP32 versus INT8 F1-scores for uBi-ConvLSTM across datasets. The near diagonal alignment demonstrates quantization robustness, with average degradation of only 0.21%. Temporal Compression Value: Removing max pooling (A1) increases MACs by 3.1× with inconsistent accuracy effects, validating the aggressive temporal compression strategy. The pooling layers provide regularization that benefits generalization … view at source ↗

**Figure 4.** Figure 4: Efficiency heatmap: F1-score per thousand parameters across datasets. Darker cells indicate higher parameter efficiency. µBi-ConvLSTM advantage is consistent across benchmarks rather than dataset-specific. minimum), whereas TinyHAR increases to 305 KB (411% increase) due to attention’s quadratic channel scaling. This characteristic makes µBi-ConvLSTM particularly suitable for multi-sensor wearable platform… view at source ↗

**Figure 6.** Figure 6: Ablation results across variants (A0–A4) and datasets. A0: Base configuration, A1: No pooling, A2: Unidirectional LSTM, A3: Single conv block, and A4: Mean pooling aggregation [PITH_FULL_IMAGE:figures/full_fig_p008_6.png] view at source ↗

**Figure 7.** Figure 7: F1-score differences from base configuration (A0) across ablation variants and datasets. The base configuration achieves best or near best performance on 5 of 8 datasets. B. Limitations Class Imbalance Sensitivity: On PAMAP2, µBiConvLSTM shows a 13.3% F1-score gap as compared to TinierHAR due to extreme class imbalance where rare activities (rope jumping, cycling) constitute <10% of samples, causing ultra… view at source ↗

read the original abstract

Human Activity Recognition (HAR) on resource constrained wearables requires models that balance accuracy against strict memory and computational budgets. State of the art lightweight architectures such as TinierHAR (34K parameters), and TinyHAR (55K parameters) achieve strong accuracy, but exceed memory budgets of microcontrollers with limited SRAM once operating system overhead is considered. We present MicroBi-ConvLSTM, an ultra-lightweight convolutional recurrent architecture achieving 11.4K parameters on average through two stage convolutional feature extraction with 4x temporal pooling, and a single bidirectional LSTM layer. This represents 2.9x parameter reduction versus TinierHAR, and 11.9x versus DeepConvLSTM while preserving linear O(N) complexity. Evaluation across eight diverse HAR benchmarks shows that MicroBi-ConvLSTM maintains competitive performance within the ultra-lightweight regime: 93.41% macro F1 on UCI-HAR, 94.46% on SKODA assembly gestures, and 88.98% on Daphnet gait freeze detection. Systematic ablation reveals task dependent component contributions where bidirectionality benefits episodic event detection, but provides marginal gains on periodic locomotion. On-device deployment on the Raspberry Pi Pico 2 and ESP32 validates hardware viability: MicroBi-ConvLSTM is the only architecture achieving full 8/8 dataset coverage on both platforms, with 72.8 ms average latency on Pico 2 and 97.9% PyTorch parity on ESP32, while all three baselines show partial or complete deployment failure.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Desk Editor's Note private letter to a colleague

MicroBi-ConvLSTM shows a workable 11k-param HAR design that deploys fully on both Pico 2 and ESP32 where the baselines do not, but the memory overhead and training details stay thin.

read the letter

The main point for you is that they've produced a model with just 11.4K parameters that deploys successfully across all eight HAR datasets on both the Raspberry Pi Pico 2 and ESP32, something the larger baselines like TinierHAR and TinyHAR don't manage. That's a practical win for anyone trying to run activity recognition on microcontrollers with tight memory. The new piece is the specific design: two stages of convolution with 4x temporal pooling before a single bidirectional LSTM layer. This gives a 2.9 times reduction in parameters over TinierHAR while keeping O(N) complexity. They show competitive macro F1 scores, like 93.41% on UCI-HAR, 94.46% on SKODA, and 88.98% on Daphnet. The ablation study on the bidirectional part is clear and points out that it helps more on episodic tasks than on steady locomotion. The on-device tests add real value with the 72.8 ms latency on Pico 2 and 97.9% parity to PyTorch on ESP32. Where it could be stronger is the lack of detail on how the model was trained and tuned. The abstract skips the hyperparameter search process and any statistical checks on whether the accuracy differences are significant. The deployment uniqueness claim also rests on the baselines failing, but without reported peak SRAM usage that factors in operating system overhead, it's possible the advantage comes partly from better optimization rather than just the parameter count. If the full paper has those measurements, it would tighten things up. This paper is aimed at engineers and researchers focused on ultra-lightweight models for wearables and edge devices. Someone looking for working examples of tiny HAR that actually run on hardware will get something out of the benchmarks and deployment numbers. It has enough empirical grounding to deserve a serious referee, even if revisions would likely ask for more on the training pipeline and memory analysis. I'd say go ahead and send it to peer review.

Referee Report

1 major / 2 minor

Summary. The manuscript presents MicroBi-ConvLSTM, an ultra-lightweight convolutional recurrent architecture with an average of 11.4K parameters that uses two-stage convolutional feature extraction with 4x temporal pooling and a single bidirectional LSTM layer. It claims competitive accuracy on eight HAR benchmarks (e.g., 93.41% macro F1 on UCI-HAR, 94.46% on SKODA, 88.98% on Daphnet) while achieving linear O(N) complexity, a 2.9x parameter reduction versus TinierHAR, and unique full 8/8 deployment success on both Raspberry Pi Pico 2 (72.8 ms average latency) and ESP32 (97.9% PyTorch parity), where the three baselines exhibit partial or complete failure.

Significance. If the deployment viability claims hold after accounting for system overhead, the work would be significant for enabling accurate HAR on severely memory-constrained microcontrollers. The extensive evaluation across eight diverse benchmarks, systematic ablations on bidirectionality, and direct hardware deployment measurements provide a strong empirical foundation that strengthens the case for ultra-lightweight models in real-world wearable applications.

major comments (1)

[Hardware deployment evaluation] Hardware deployment evaluation: The headline claim that MicroBi-ConvLSTM is the only architecture achieving full 8/8 dataset coverage on both Pico 2 and ESP32 is load-bearing for the superiority argument. However, the manuscript reports no peak SRAM figures that include operating-system overhead (stack, heap, DMA buffers, or runtime allocations) for any model. Without these measurements it remains unclear whether the 2.9x parameter reduction actually enables deployability or whether overhead is comparable across models.

minor comments (2)

[Abstract] Abstract: Limited detail is provided on the training procedure, exact hyperparameter search, and whether reported accuracy differences are statistically significant.
[Results tables] Results tables: Consider reporting standard deviations or confidence intervals alongside the macro F1 scores to allow readers to assess the reliability of the cross-model comparisons.

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for the constructive comments. We address the major comment below and will revise the manuscript to incorporate the requested measurements.

read point-by-point responses

Referee: Hardware deployment evaluation: The headline claim that MicroBi-ConvLSTM is the only architecture achieving full 8/8 dataset coverage on both Pico 2 and ESP32 is load-bearing for the superiority argument. However, the manuscript reports no peak SRAM figures that include operating-system overhead (stack, heap, DMA buffers, or runtime allocations) for any model. Without these measurements it remains unclear whether the 2.9x parameter reduction actually enables deployability or whether overhead is comparable across models.

Authors: We agree that reporting peak SRAM usage including OS overhead would provide stronger evidence for the deployability claims. The manuscript currently emphasizes successful full deployment outcomes and latency but omits these detailed breakdowns. In the revised manuscript we will add peak memory measurements (including stack, heap, DMA buffers, and runtime allocations) for all models on both platforms, obtained via platform-specific profilers such as Pico SDK memory statistics and ESP-IDF heap tracing. These additions will clarify the role of the 2.9x parameter reduction in enabling full deployment. revision: yes

Circularity Check

0 steps flagged

No circularity: architecture and results are self-contained empirical claims

full rationale

The paper defines MicroBi-ConvLSTM explicitly via two-stage conv feature extraction, 4x temporal pooling, and one bidirectional LSTM layer, then directly counts parameters as 11.4K from that definition. Accuracies, F1 scores, latency, and 8/8 deployment coverage are reported as measured outcomes on eight benchmarks and two MCUs, with no fitted parameters renamed as predictions, no self-citation chains justifying uniqueness theorems, and no ansatz smuggled in. The derivation chain consists of architectural choices followed by independent empirical validation; baseline failures are presented as comparative measurements rather than self-referential reductions. No step reduces by construction to its own inputs.

Axiom & Free-Parameter Ledger

2 free parameters · 1 axioms · 0 invented entities

The model relies on standard deep-learning assumptions about sensor data distributions and the validity of macro F1 as the primary metric; no new entities are postulated.

free parameters (2)

convolutional filter counts and kernel sizes
Typical CNN hyperparameters tuned during architecture search to reach the reported parameter budget.
LSTM hidden dimension
Chosen to keep total parameters at 11.4K while preserving accuracy.

axioms (1)

domain assumption Sensor time-series from the eight benchmarks are representative of real-world HAR tasks.
Invoked when claiming generalization from the reported macro F1 scores.

pith-pipeline@v0.9.0 · 5577 in / 1322 out tokens · 38407 ms · 2026-05-16T07:14:06.687629+00:00 · methodology

discussion (0)

Lean theorems connected to this paper

Citations machine-checked in the Pith Canon. Every link opens the source theorem in the public Lean library.

IndisputableMonolith/Cost/FunctionalEquation.lean washburn_uniqueness_aczel unclear

?

unclear
Relation between the paper passage and the cited Recognition theorem.

two-stage convolutional feature extraction with 4× temporal pooling and a single bidirectional LSTM layer... 11.4K parameters... O(N) complexity
IndisputableMonolith/Foundation/DimensionForcing.lean alexander_duality_circle_linking unclear

?

unclear
Relation between the paper passage and the cited Recognition theorem.

MicroBi-ConvLSTM is the only architecture achieving full 8/8 dataset coverage... 72.8 ms average latency

What do these tags mean?

matches: The paper's claim is directly supported by a theorem in the formal canon.
supports: The theorem supports part of the paper's argument, but the paper may add assumptions or extra steps.
extends: The paper goes beyond the formal theorem; the theorem is a base layer rather than the whole result.
uses: The paper appears to rely on the theorem as machinery.
contradicts: The paper's claim conflicts with a theorem or certificate in the canon.
unclear: Pith found a possible connection, but the passage is too broad, indirect, or ambiguous to say the theorem truly supports the claim.

Reference graph

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