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arxiv: 2602.09872 · v2 · pith:Q4ZVK537new · submitted 2026-02-10 · 💻 cs.CV · cs.HC

BabyMamba-HAR: Lightweight Selective State Space Models for Efficient Human Activity Recognition on Resource Constrained Devices

Mridankan Mandal This is my paper

Pith reviewed 2026-05-21 13:18 UTC · model grok-4.3

classification 💻 cs.CV cs.HC
keywords human activity recognitionselective state space modelstiny machine learningmicrocontroller deploymentbidirectional scanningsensor time seriesefficient inferencelightweight models
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The pith

Lightweight selective state space models achieve 86.5 percent average F1-score for human activity recognition using 27K parameters and 2.2M MACs.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

This paper establishes that selective state space models can be turned into two very small architectures for recognizing human activities from sensor data on severely limited hardware. One version processes channels independently to resist noise while the other fuses them early to keep complexity independent of channel count. Both add weight-tied bidirectional scanning to look at time both forward and backward and gated temporal attention pooling to emphasize important moments. These choices let the models reach accuracy levels similar to prior tiny models across eight different benchmarks yet with far lower computation and memory use. A sympathetic reader would care because the results show on-device activity sensing can run reliably on cheap microcontrollers without needing powerful processors or large batteries.

Core claim

BabyMamba-HAR presents CI-BabyMamba-HAR and Crossover-BiDir-BabyMamba-HAR as compact selective state space model variants for human activity recognition. The designs include a channel-independent stem or an early-fusion stem, weight-tied bidirectional scanning, and gated temporal attention pooling. Crossover-BiDir-BabyMamba-HAR reaches an average 86.52 percent F1-score with 27K parameters and 2.21M MACs across eight benchmarks, matching TinyHAR accuracy while using 11 times fewer MACs on high-channel datasets. On Raspberry Pi Pico 2 and ESP32 the models run via a mixed-precision C++ runtime with lifetime-aware memory management that cuts peak memory from O(B times dmodel times L times dstate

What carries the argument

Weight-tied bidirectional scanning together with gated temporal attention pooling inside selective state space model layers, which supplies efficient forward-and-backward temporal modeling and focused aggregation at low parameter and compute cost.

If this is right

  • The model matches prior accuracy on eight benchmarks while cutting MACs by a factor of eleven on high-channel sensor data.
  • Both architectures achieve complete coverage of all eight datasets with greater than 99.2 percent parity to the original PyTorch versions on two common microcontrollers.
  • Ablations demonstrate that bidirectional scanning and gated attention each raise F1-scores by as much as 8 to 9 percent.
  • The memory strategy reduces peak usage to scale with batch size, model dimension, and state size instead of sequence length.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same scanning and pooling choices could improve efficiency for other edge-device time-series tasks such as gesture detection or equipment monitoring.
  • The channel-streaming execution pattern may support continuous real-time inference from live sensor feeds without storing full sequences.
  • Further experiments on additional low-power chips would test whether the reported parity and latency hold beyond the two devices examined here.
  • These lightweight SSM patterns could serve as baselines when comparing new sequence models for resource-constrained classification problems.

Load-bearing premise

The specific optimizations of weight-tied bidirectional scanning, gated temporal attention pooling, and the mixed-precision runtime with lifetime-aware memory allocation keep accuracy intact while fitting the memory and timing constraints of the tested microcontrollers.

What would settle it

Testing the trained models on a ninth human activity recognition dataset that uses different sensors or activities and checking whether average F1-score stays above 80 percent and microcontroller parity remains above 95 percent.

Figures

Figures reproduced from arXiv: 2602.09872 by Mridankan Mandal.

Figure 1
Figure 1. Figure 1: CI-BabyMamba-HAR architecture. The channel independent stem processes each sensor channel through shared weight Conv1D, BatchNorm, and [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Crossover-BiDir-BabyMamba-HAR architecture. The early fusion stem projects all input channels to [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Weight tied Bidirectional Selective state space (SSM) block architecture. Input dependent projections control discretization step [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Performance comparison grid across all eight HAR benchmark datasets showing macro F1-scores for each model-dataset combination. [PITH_FULL_IMAGE:figures/full_fig_p005_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Combined ablation study results showing ∆F1 relative to baseline configurations. (C) Channel processing ablation across all 8 datasets comparing CI-BabyMamba vs. Crossover architectures with channel independent stem variants. (B) Hyperparameter sensitivity (d_state, d_model, expand factor) on 2 representative datasets. (A) Architecture ablation (bidirectionality A2, pooling A3, stem A4) on 4 datasets. (L) … view at source ↗
read the original abstract

Human activity recognition (HAR) on resource constrained devices requires high accuracy across diverse sensor setups. Selective state space models (SSMs) offer efficient linear time sequence processing, presenting a compelling alternative to attention mechanisms. However, their TinyML design space remains unexplored. This paper introduces BabyMamba-HAR, comprising two lightweight architectures: (1) CI-BabyMamba-HAR, utilizing a channel independent stem for noise robustness, and (2) Crossover-BiDir-BabyMamba-HAR, utilizing an early fusion stem for channel count independent complexity. Both integrate weight tied bidirectional scanning and gated temporal attention pooling. Across eight benchmarks, Crossover-BiDir-BabyMamba-HAR averages an 86.52% F1-score with 27K parameters and 2.21M MACs, matching TinyHAR (86.16%) while requiring 11x fewer MACs on high channel datasets. On-device deployment on the Raspberry Pi Pico 2 and ESP32 utilized a mixed precision C++ runtime (INT8 projections, float32 states). A fused computation strategy with lifetime aware memory management reduces peak memory footprint from O(B*dmodel*L*dstate) to O(B*dmodel*dstate), adapting to support weight-tied bidirectional and channel-streaming execution. Both architectures achieved full 8/8 dataset coverage with >99.2% PyTorch parity, whereas INT8 quantized TFLite baselines showed degraded coverage and parity (TinyHAR: 7/8 and 4/8 coverage at 60.4% and 88.6% parity, TinierHAR: 8/8 and 6/8 at 54.2% and 90.8%, DeepConvLSTM: 1/8 and 0/8 on Pico 2 and ESP32, respectively). Crossover-BiDir-BabyMamba-HAR averages 154.4 ms latency on ESP32 and 481.9 ms on Pico 2. Ablations confirm bidirectional scanning and gated attention improve F1-scores by up to 8.42% and 8.94%, respectively, establishing practical principles for TinyML SSM deployment.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The paper introduces BabyMamba-HAR, two lightweight selective state space model (SSM) architectures for human activity recognition (HAR) on resource-constrained devices: CI-BabyMamba-HAR with a channel-independent stem and Crossover-BiDir-BabyMamba-HAR with an early-fusion stem. Both incorporate weight-tied bidirectional scanning and gated temporal attention pooling. The central claim is that Crossover-BiDir-BabyMamba-HAR achieves an average 86.52% F1-score across eight benchmarks with 27K parameters and 2.21M MACs, matching TinyHAR (86.16%) while using 11x fewer MACs on high-channel datasets; on-device deployments on Raspberry Pi Pico 2 and ESP32 yield >99.2% PyTorch parity with full 8/8 coverage, 154.4 ms latency on ESP32, and ablation gains up to 8.94% from the proposed components.

Significance. If the empirical results hold under statistical scrutiny, the work is significant for filling the unexplored TinyML design space for SSMs in sensor-based HAR. It supplies concrete efficiency metrics (parameter counts, MACs, latency), hardware-validated parity, and a memory optimization reducing peak footprint from O(B·d_model·L·d_state) to O(B·d_model·d_state), along with practical principles such as weight-tied bidirectional scanning. These elements offer actionable guidance for deploying linear-time sequence models on microcontrollers beyond the specific eight benchmarks tested.

major comments (2)
  1. [Abstract and experimental results] Abstract and results presentation: the average F1-score of 86.52%, the parity with TinyHAR at 86.16%, and the ablation improvements (up to 8.42% from bidirectional scanning and 8.94% from gated temporal attention pooling) are reported as single-run point estimates with no error bars, standard deviations, multi-seed averages, or statistical significance tests. This directly affects the load-bearing central claim that the architectures match prior work while establishing reliable TinyML SSM principles, as the absence of variance measures leaves open whether the reported gains and parity are reproducible across training runs or data splits.
  2. [Deployment and hardware results] On-device evaluation: the claims of >99.2% PyTorch parity, full 8/8 dataset coverage, and superiority over INT8 TFLite baselines (e.g., TinyHAR at 60.4% parity) rest on the specific mixed-precision C++ runtime and lifetime-aware memory management, yet no quantitative before/after memory measurements or failure-case analysis for the eight benchmarks are provided to confirm that the optimizations preserve accuracy without hidden trade-offs.
minor comments (2)
  1. [Architecture] The description of the channel-independent stem versus early-fusion stem would benefit from an explicit comparison table of complexity scaling with channel count to clarify the 'channel count independent complexity' claim.
  2. [Experimental setup] Training hyperparameters, exact data splits for the eight benchmarks, and optimizer details are referenced only at a high level; adding these to a reproducibility section or appendix would strengthen the manuscript without altering the core claims.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive comments on our manuscript. We address each major point below and have revised the manuscript to incorporate additional statistical reporting and quantitative hardware measurements where feasible.

read point-by-point responses

  1. Referee: [Abstract and experimental results] Abstract and results presentation: the average F1-score of 86.52%, the parity with TinyHAR at 86.16%, and the ablation improvements (up to 8.42% from bidirectional scanning and 8.94% from gated temporal attention pooling) are reported as single-run point estimates with no error bars, standard deviations, multi-seed averages, or statistical significance tests. This directly affects the load-bearing central claim that the architectures match prior work while establishing reliable TinyML SSM principles, as the absence of variance measures leaves open whether the reported gains and parity are reproducible across training runs or data splits.

    Authors: We agree that reporting single-run point estimates without variance measures limits the strength of the central claims regarding reproducibility. While single-run results are common in resource-intensive TinyML evaluations, we will revise the manuscript to include averages and standard deviations over five random seeds for the main F1-scores, parity metrics, and ablations on the eight benchmarks. We will also add a brief discussion of observed run-to-run variability. revision: yes

  2. Referee: [Deployment and hardware results] On-device evaluation: the claims of >99.2% PyTorch parity, full 8/8 dataset coverage, and superiority over INT8 TFLite baselines (e.g., TinyHAR at 60.4% parity) rest on the specific mixed-precision C++ runtime and lifetime-aware memory management, yet no quantitative before/after memory measurements or failure-case analysis for the eight benchmarks are provided to confirm that the optimizations preserve accuracy without hidden trade-offs.

    Authors: We acknowledge the value of explicit quantitative memory data and failure analysis. The current manuscript describes the asymptotic reduction in peak memory but does not report concrete before/after RAM measurements or per-benchmark failure cases. In the revised version we will add a table with measured peak memory usage (in KB) on ESP32 and Raspberry Pi Pico 2 for each of the eight datasets, both before and after the lifetime-aware optimization, along with notes on any accuracy trade-offs or deployment failures encountered. revision: yes

Circularity Check

0 steps flagged

No circularity: purely empirical architecture proposal and benchmark evaluation

full rationale

The paper proposes two new lightweight SSM-based architectures (CI-BabyMamba-HAR and Crossover-BiDir-BabyMamba-HAR) with specific design choices such as weight-tied bidirectional scanning and gated temporal attention pooling. All central claims consist of direct empirical measurements: average F1-scores on eight public benchmarks, parameter/MAC counts, ablation deltas, on-device latency, and PyTorch parity after custom C++ implementation. No derivation chain, first-principles equations, fitted parameters renamed as predictions, or self-citation load-bearing steps exist. Comparisons are to external baselines (TinyHAR, etc.) on standard datasets; ablations simply report observed accuracy changes from adding components. The work is self-contained against external benchmarks with no reduction of outputs to inputs by construction.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The paper relies on standard machine learning assumptions about benchmark representativeness and generalization but introduces no new physical entities or heavily fitted parameters beyond typical neural network hyperparameters.

axioms (1)
  • domain assumption The eight HAR benchmarks used are representative of real-world sensor data distributions and noise characteristics.
    Performance claims rest on these benchmarks generalizing beyond the tested setups.

pith-pipeline@v0.9.0 · 5941 in / 1394 out tokens · 57397 ms · 2026-05-21T13:18:05.900082+00:00 · methodology

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Reference graph

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