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arxiv: 2604.04696 · v2 · submitted 2026-04-06 · 💻 cs.CR · cs.AR

Recognition: no theorem link

GPIR: Enabling Practical Private Information Retrieval with GPUs

G. Edward Suh, Hyesung Ji, Hyunah Yu, Jongmin Kim, Jung Ho Ahn, Wonseok Choi

Authors on Pith no claims yet

Pith reviewed 2026-05-10 19:54 UTC · model grok-4.3

classification 💻 cs.CR cs.AR
keywords private information retrievalGPU accelerationlattice-based cryptographykernel fusionmatrix multiplicationdata layout optimizationmulti-GPU systemsmemory traffic reduction
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The pith

GPIR makes private database queries practical on GPUs by redesigning kernels and data layouts to cut memory traffic and reach up to 297 times higher throughput than prior GPU systems.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

Private information retrieval lets clients query databases without revealing their interests, but the server-side work of expanding queries, selecting rows, and combining results creates heavy computation and memory movement that has kept it from widespread use. The paper demonstrates that GPUs become effective for this workload once the software accounts for how large batches of clients change the bottlenecks, specifically by keeping intermediate data in fast on-chip memory instead of spilling to slow DRAM. GPIR does this through a hybrid scheduler that sometimes runs each math step alone and sometimes fuses an entire stage into one kernel, plus a data rearrangement that aligns the row-selection multiplications with the rest of the pipeline. These changes let the system handle more clients and bigger databases while scaling across multiple GPUs with little extra communication. A reader would care because the result turns a privacy tool that was mostly theoretical into one that can run at usable speeds on existing hardware.

Core claim

GPIR is a GPU PIR implementation built around a stage-aware hybrid execution model that switches between separate kernels for each primitive and fused kernels that keep all operations of a stage on-chip, paired with a transposed data layout and fine-grained pipelining for the RowSel matrix multiplications. The same design extends to multi-GPU configurations with negligible communication cost. On the evaluated hardware these techniques produce up to 297.2 times the throughput of the previous best GPU PIR system.

What carries the argument

The stage-aware hybrid execution model that fuses all operations inside each PIR phase into single kernels for on-chip reuse, together with the transposed-layout pipelining that aligns RowSel GEMMs to the surrounding NTT-driven data layout.

If this is right

  • Multi-client PIR becomes feasible on both single and multi-GPU servers without the memory-traffic penalty that previously limited batch size.
  • Database capacity can be increased in proportion to the number of GPUs while communication overhead remains negligible.
  • The same kernel-fusion and layout techniques apply directly to any lattice-based protocol that alternates NTTs with large independent matrix multiplications.
  • Practical deployment of private queries becomes realistic for cloud services that already have GPU clusters.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Similar hybrid scheduling could improve other GPU-heavy cryptographic workloads that suffer from working-set explosion under batching.
  • The transposed-layout idea suggests that domain-specific data rearrangements may be a general lever for unlocking hardware acceleration in privacy protocols.
  • Testing the same design on newer GPU generations with larger on-chip caches would reveal whether the gains widen or shift to different bottlenecks.
  • Widespread adoption would lower the barrier to private queries in applications such as medical or financial record access.

Load-bearing premise

The hybrid execution model and transposed pipelining will actually remove the excess DRAM traffic caused by batching without introducing correctness errors or new performance limits that appear only at full implementation scale.

What would settle it

Measure DRAM bandwidth utilization and end-to-end throughput on the target GPU while varying client batch size; if the measured traffic stays high or throughput fails to scale as predicted, the central performance claim does not hold.

Figures

Figures reproduced from arXiv: 2604.04696 by G. Edward Suh, Hyesung Ji, Hyunah Yu, Jongmin Kim, Jung Ho Ahn, Wonseok Choi.

Figure 1
Figure 1. Figure 1: OnionPIRv2 computation process. the GPU roofline’s balanced ridge point [13]. However, batching dramatically expands the working sets of ExpandQuery and ColTor, pushing memory demands beyond the GPU’s L2 cache capacity. When these working sets exceed the hardware threshold, perfor￾mance collapses due to excessive DRAM traffic. Naïvely applying existing GPU kernels fails to resolve these bottlenecks, which … view at source ↗
Figure 2
Figure 2. Figure 2: Four job partitioning strategies for PIR operations. [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Roofline analysis of each PIR phase on an RTX 5090 [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Operation-wise working set variation across Ex [PITH_FULL_IMAGE:figures/full_fig_p005_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Stage-wise DRAM transaction and execution time of operation- and stage-level kernels under various batch sizes. (a, [PITH_FULL_IMAGE:figures/full_fig_p006_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Achieved throughput under a stream-like bench [PITH_FULL_IMAGE:figures/full_fig_p006_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: (a) Required GEMMs for RowSel and (b)(c) two [PITH_FULL_IMAGE:figures/full_fig_p007_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: Gradually applying additional partitioning meth [PITH_FULL_IMAGE:figures/full_fig_p008_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: DB sharding and all-gathering expanded cts in multi￾GPU PIR execution on two GPUs. Comm. indicates inter-GPU communication. Since each GPU sends only a single ct per query after ColTor (the right side of [PITH_FULL_IMAGE:figures/full_fig_p009_9.png] view at source ↗
Figure 11
Figure 11. Figure 11: DRAM transactions under different batch sizes [PITH_FULL_IMAGE:figures/full_fig_p010_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: Latency breakdown across GPUs for baseline and [PITH_FULL_IMAGE:figures/full_fig_p010_12.png] view at source ↗
read the original abstract

Private information retrieval (PIR) allows private database queries; however, it is hindered by intense server-side computation and memory traffic. Numerous modern lattice-based PIR protocols consist of three phases: ExpandQuery (expanding a query into encrypted indices), RowSel (encrypted row selection), and ColTor (recursive "column tournament" for final selection). ExpandQuery and ColTor primarily perform number-theoretic transforms (NTTs), whereas RowSel reduces to large-scale independent matrix-matrix multiplications (GEMMs). GPUs are well suited for these tasks when combined with multi-client batching, which is necessary for high throughput. However, batching fundamentally reshapes the performance bottlenecks: while it amortizes database access costs, it expands working sets beyond the L2 cache capacity, causing divergent memory access behavior and excessive DRAM traffic. We present GPIR, a GPU-accelerated PIR system that rethinks kernel design, data layout, and execution scheduling. We introduce a stage-aware hybrid execution model that dynamically switches between operation-level kernels, which execute each primitive operation separately, and stage-level kernels, which fuse all operations within a stage into a single kernel to maximize on-chip data reuse. For RowSel, we resolve the mismatch between NTT-driven layouts and tiled GEMMs using a transposed-layout design with fine-grained pipelining. We further extend GPIR to multi-GPU systems, scaling throughput and database capacity with negligible communication overhead. GPIR achieves up to 297.2x higher throughput than PIRonGPU, the state-of-the-art GPU implementation.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

3 major / 2 minor

Summary. The paper presents GPIR, a GPU-accelerated implementation of lattice-based PIR that optimizes the three phases (ExpandQuery via NTTs, RowSel via GEMMs, ColTor via NTTs) through a stage-aware hybrid execution model (switching between operation-level and stage-level fused kernels) and a transposed-layout pipelining scheme for RowSel to reduce DRAM traffic under multi-client batching. It claims up to 297.2x throughput improvement over PIRonGPU and demonstrates multi-GPU scaling with low communication cost.

Significance. If the performance results are reproducible with full experimental details, the work could meaningfully advance practical server-side PIR by addressing batch-induced memory bottlenecks on GPUs, enabling higher throughput for privacy-preserving queries. The hybrid scheduling and layout optimizations represent a concrete systems contribution that could be adopted in other NTT/GEMM-heavy cryptographic workloads.

major comments (3)
  1. [§5] §5 (Performance Evaluation): The central claim of up to 297.2x higher throughput versus PIRonGPU is presented without any description of benchmark methodology, database sizes, batch sizes, security parameters (e.g., ring dimension, modulus), error bars, or ablation studies isolating the hybrid model and transposed pipelining; this prevents verification of the speedup and attribution to the proposed techniques.
  2. [§3.2] §3.2 (Stage-aware Hybrid Execution Model): The assertion that stage-level kernels eliminate excess DRAM traffic by keeping intermediates on-chip lacks any quantitative memory-access analysis, cache-miss profiling, or working-set size measurements to confirm that fusion succeeds when batching expands data beyond L2 capacity.
  3. [§3.3] §3.3 (Transposed-layout Pipelining for RowSel): No pseudocode, kernel launch configuration, or arithmetic error analysis is supplied for the fine-grained NTT-GEMM pipelining; it is therefore unclear whether the layout transposition preserves NTT/GEMM semantics or merely shifts bandwidth bottlenecks.
minor comments (2)
  1. [Figure 2] Figure 2: The execution timeline diagram would be clearer with explicit annotations for on-chip data reuse points and DRAM access phases.
  2. [§4] §4 (Multi-GPU Extension): The communication overhead claim would benefit from a table showing scaling efficiency across different GPU counts and database partitions.

Simulated Author's Rebuttal

3 responses · 0 unresolved

We thank the referee for the thorough and constructive review. The comments highlight areas where additional details will improve clarity and verifiability. We will revise the manuscript to incorporate expanded experimental methodology, quantitative memory analysis, and implementation pseudocode. Our point-by-point responses follow.

read point-by-point responses

  1. Referee: [§5] §5 (Performance Evaluation): The central claim of up to 297.2x higher throughput versus PIRonGPU is presented without any description of benchmark methodology, database sizes, batch sizes, security parameters (e.g., ring dimension, modulus), error bars, or ablation studies isolating the hybrid model and transposed pipelining; this prevents verification of the speedup and attribution to the proposed techniques.

    Authors: We agree that Section 5 requires more explicit experimental details to support reproducibility. In the revised manuscript we will add a dedicated 'Benchmark Methodology' subsection that specifies: database sizes (2^20 to 2^24 entries), batch sizes (1–4096 concurrent clients), security parameters (ring dimension N=4096, modulus q≈2^32, error distribution), hardware (NVIDIA A100 80 GB GPUs), number of runs (minimum 5) with standard deviation error bars, and the exact PIRonGPU baseline configuration used for the 297.2× result. We will also include ablation studies that isolate the contribution of the stage-aware hybrid scheduler versus pure operation-level kernels and the transposed-layout pipelining versus standard row-major layouts. revision: yes

  2. Referee: [§3.2] §3.2 (Stage-aware Hybrid Execution Model): The assertion that stage-level kernels eliminate excess DRAM traffic by keeping intermediates on-chip lacks any quantitative memory-access analysis, cache-miss profiling, or working-set size measurements to confirm that fusion succeeds when batching expands data beyond L2 capacity.

    Authors: We acknowledge the need for quantitative backing. The revision will augment §3.2 with memory-access analysis derived from NVIDIA Nsight Compute traces. We will report DRAM transaction counts, L2 cache miss rates, and working-set sizes for representative batch sizes, demonstrating that stage-level fusion reduces DRAM traffic by keeping intermediate NTT outputs within on-chip memory when the batched working set exceeds L2 capacity. These measurements will be presented alongside the throughput results to directly attribute the observed gains to reduced memory traffic. revision: yes

  3. Referee: [§3.3] §3.3 (Transposed-layout Pipelining for RowSel): No pseudocode, kernel launch configuration, or arithmetic error analysis is supplied for the fine-grained NTT-GEMM pipelining; it is therefore unclear whether the layout transposition preserves NTT/GEMM semantics or merely shifts bandwidth bottlenecks.

    Authors: We will add pseudocode (Algorithm X) and kernel launch parameters (thread-block size 256, grid dimensions derived from batch size and matrix dimensions) to §3.3. The description will clarify that the transposed layout is a pure reordering of data that preserves the algebraic semantics of both NTT and GEMM; the operations remain mathematically identical and incur no additional rounding error beyond the original fixed-point arithmetic. We will also include a short arithmetic-error bound analysis confirming that the pipelined schedule does not alter the final PIR result. revision: yes

Circularity Check

0 steps flagged

No circularity in empirical GPU systems optimization

full rationale

The paper describes concrete engineering techniques (stage-aware hybrid kernels, transposed-layout pipelining for RowSel, multi-GPU scaling) and reports measured throughput numbers against an external baseline (PIRonGPU). No equations, fitted parameters, or first-principles derivations are presented whose outputs reduce to the inputs by construction. Performance claims are external benchmark comparisons rather than self-referential predictions or self-citation chains. The work is self-contained as an implementation artifact whose validity rests on reproducible code and hardware measurements, not on any load-bearing internal definition or renaming.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

This is an applied systems paper; the central claim rests on standard GPU architecture assumptions rather than new mathematical axioms or fitted parameters.

axioms (1)
  • domain assumption GPU memory hierarchy and kernel launch overheads behave as described in vendor documentation and prior systems literature.
    The hybrid execution and pipelining strategies presuppose known cache sizes, DRAM latency, and kernel fusion costs.

pith-pipeline@v0.9.0 · 5590 in / 1223 out tokens · 113803 ms · 2026-05-10T19:54:13.977015+00:00 · methodology

discussion (0)

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