arxiv: 2604.12635 · v1 · submitted 2026-04-14 · 🪐 quant-ph

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The Impact of Qubit Connectivity on Quantum Advantage in Noisy IQP Circuits

Chen-Yu Liu, Enrico Rinaldi, Keisuke Fujii, Leonardo Placidi

Authors on Pith no claims yet

Pith reviewed 2026-05-10 15:13 UTC · model grok-4.3

classification 🪐 quant-ph

keywords compiledconnectivitydeptheffectivesimulatabilitysparseboundarycircuits

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The pith

Qubit connectivity determines the noise threshold for quantum advantage in noisy IQP circuits.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

This paper investigates how the arrangement of qubit connections influences the potential for quantum advantage in noisy Instantaneous Quantum Polynomial-time circuits. These circuits are expected to be hard for classical computers when ideal, but noise turns them simulatable past a depth threshold. Sparse connections add routing gates that increase depth, shifting the circuit toward easier simulation. By analyzing compiled depths on various real hardware topologies and estimating noise from gate errors, the work shows sparse setups need better noise control to stay in the hard regime. A sympathetic reader would care because this guides which hardware features matter most for demonstrating advantage soon.

Core claim

For any fixed IQP circuit, hardware with sparse qubit connectivity produces longer compiled circuits due to the need for routing swaps or additional gates to realize distant interactions. This increased depth moves the noisy implementation closer to the boundary where classical simulation becomes feasible. Using both analytic depth formulas for grid-like architectures and actual compilation runs on seven device models, the paper quantifies how much lower the effective noise must be on sparse graphs to maintain the same distance from the simulatability limit as on denser graphs.

What carries the argument

Connectivity-aware compilation that calculates the depth overhead from routing on sparse graphs and the resulting shift in the position relative to the noisy IQP simulatability boundary.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

Hardware designers might prioritize adding more connections even at the cost of other resources to enable deeper useful circuits.
The approach could be applied to other near-term quantum tasks where circuit depth is a limiting factor.
Future work could incorporate more detailed noise models beyond two-qubit errors to refine these predictions.

Load-bearing premise

That the boundary for classical simulability of noisy IQP circuits depends mainly on the total compiled depth and the average two-qubit gate error rate.

What would settle it

Compiling an IQP circuit to two different connectivities, running it on hardware or a noise model, and checking whether the output distribution hardness transitions at the depth predicted by the analysis.

Figures

Figures reproduced from arXiv: 2604.12635 by Chen-Yu Liu, Enrico Rinaldi, Keisuke Fujii, Leonardo Placidi.

**Figure 2.** Figure 2: Percolation-based fragmentation for four IQP interaction patterns at [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗

**Figure 3.** Figure 3: Native hardware connectivity graphs used in the routing [PITH_FULL_IMAGE:figures/full_fig_p006_3.png] view at source ↗

**Figure 4.** Figure 4: Phase diagrams for k=2 IQP circuits across four interaction patterns. The critical boundary D∗(p, k) = c/(p ln(k/p)) (black curve) separates the simulatable regime (teal, m(H) < 0) from the potentially hard regime (coral, m(H) > 0). Each platform is plotted at its operating point (peff(H), DH); the legend reports the ideal fully-connected depth DFC and the compiled depth DH as (DFC/DH). Reported depths are… view at source ↗

**Figure 5.** Figure 5: Compilation efficiency ηH := DFC/DH versus qubit count for four interaction patterns. Solid segments correspond to compiled data; dashed segments show per-hardware linear extrapolations beyond the measured range. Panels (a)–(c) use compiled data for n = 4–32 and extrapolate to n = 70; panel (d) shows RHG lattice instances extrapolations at the valid sizes n ∈ {18, 44, 90, 127} [PITH_FULL_IMAGE:figures/ful… view at source ↗

**Figure 6.** Figure 6: Reference connectivity graphs used as simplified [PITH_FULL_IMAGE:figures/full_fig_p009_6.png] view at source ↗

read the original abstract

Instantaneous Quantum Polynomial-time (IQP) circuits are a candidate for demonstrating near-term quantum advantage, as their sampling task is believed to be classically hard in the ideal theoretical setting under standard complexity-theoretic assumptions. In noisy implementations, however, this hardness can disappear once circuit depth exceeds a noise-dependent critical threshold. We show that qubit connectivity is a key parameter in this transition, since sparse architectures require additional routing to implement long-range interactions, thereby increasing compiled circuit depth. To make this explicit, we present a connectivity-aware analysis of compiled IQP circuits. For a fixed abstract IQP instance, different hardware connectivity graphs yield different compiled depths and thus different effective positions relative to the noisy-IQP simulatability boundary. We quantify this architecture-dependent shift using the compiled depth overhead and the corresponding simulatability margin. We combine analytic depth estimates for sparse geometries, including the two-dimensional grid, with native-gateset-aware compilation experiments across seven hardware-grounded experimental device models derived from publicly available topologies. To compare these device models under a unified empirical framework, we approximate the effective noise level primarily through reported two-qubit gate error rates. This lets us compare how much effective noise sparse and fully connected architectures can tolerate for the same position relative to the noisy-IQP simulatability boundary. Our results show that sparse connectivity requires a lower effective noise level to sustain the same margin relative to the noisy-IQP simulatability boundary, and they provide a quantitative framework for determining when compiled IQP experiments are likely to remain outside, or instead enter, the classically simulatable regime.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Desk Editor's Note private letter to a colleague

The paper quantifies how sparser qubit connectivity forces extra compiled depth in IQP circuits and therefore lowers the noise level needed to stay outside the classical simulatability regime.

read the letter

The central point is that different hardware graphs change the effective depth of the same abstract IQP circuit through routing overhead, which moves the noise threshold for when sampling becomes classically easy. They make this concrete with analytic depth formulas for sparse layouts like grids and then compile the circuits to seven device models drawn from real hardware topologies. Using reported two-qubit error rates as the main noise proxy, they compare how much effective noise each architecture can tolerate before the margin to the simulatability boundary disappears. This is the new piece: a direct, quantitative link between connectivity, compiled depth, and the position relative to that boundary for IQP specifically. The analytic estimates and the native-gateset compilation runs are the parts that hold up cleanly and give readers something they can check or extend. The experiments are grounded in publicly available device data, which is a plus. The soft spot is the noise approximation itself. Treating effective noise as driven primarily by two-qubit gate errors leaves out single-qubit errors, readout noise, and the idle or extra SWAP errors that come with the routing layers on sparse graphs. Those terms are not uniform across architectures, so the ranking of which devices keep a larger simulatability margin could shift once they are included. The paper does not appear to run a sensitivity check on this. Readers working on near-term IQP experiments or device topology choices will get the most out of it; it supplies a practical way to estimate whether a compiled circuit is still plausibly hard. The work is clear enough on its own terms to deserve referee time, even if the noise model needs tightening.

Referee Report

3 major / 3 minor

Summary. The paper claims that for a fixed abstract IQP instance, different qubit connectivity graphs on hardware lead to different compiled circuit depths due to routing overhead, thereby shifting the circuits' positions relative to the noisy-IQP simulatability boundary. Using analytic depth estimates for sparse geometries (e.g., 2D grids) and native-gateset compilation experiments on seven hardware-derived device models, with effective noise approximated primarily from two-qubit gate error rates, it concludes that sparse architectures require lower effective noise levels than denser ones to maintain the same margin against classical simulability.

Significance. If substantiated, the work supplies a practical quantitative framework for experimentalists to assess architecture-dependent prospects for noisy IQP advantage, by explicitly linking connectivity-induced depth overhead to the simulatability threshold. It extends prior noisy IQP analyses with device-grounded comparisons and analytic estimates, providing a tool to rank hardware topologies for this task. The combination of analytic depth calculations and multi-device experiments is a methodological strength that could aid reproducible evaluations.

major comments (3)

[Abstract / unified empirical framework] Abstract and unified empirical framework: The simulatability boundary is positioned via compiled depth plus an effective noise proxy derived primarily from reported two-qubit gate error rates. However, without sensitivity checks or bounds on contributions from single-qubit errors, readout noise, or idle errors during routing/SWAP layers, the claimed architecture-dependent margin shifts (sparse vs. dense) rest on an incomplete noise model that may mis-rank the devices. This approximation is load-bearing for the central quantitative conclusion.
[native-gateset-aware compilation experiments] Native-gateset-aware compilation experiments: For the seven device models, the paper must detail the exact compilation procedure, including how routing overhead is quantified in depth and whether non-uniform error propagation from extra SWAPs is folded into the effective noise or boundary calculation. Absent this, the depth-to-margin mapping for a fixed IQP instance cannot be verified as robust.
[analytic depth estimates] Analytic depth estimates for sparse geometries: The translation from 2D-grid (and other) connectivity overhead to simulatability margin assumes the boundary depends primarily on total depth and the scalar noise proxy. The paper should provide the explicit functional form or reference used for the boundary and test whether the overhead formula holds under the paper's own noise approximation.

minor comments (3)

Define 'simulatability margin' explicitly (with formula or reference) at first use to avoid ambiguity in the quantitative comparisons.
Include a table or figure summarizing the seven device models' connectivity graphs, qubit counts, and reported error rates for full reproducibility.
Ensure consistent use of 'compiled depth' versus any variant terms across analytic and experimental sections.

Simulated Author's Rebuttal

3 responses · 0 unresolved

We thank the referee for the thorough and constructive report. The comments highlight important aspects of our noise modeling and methodological details. We address each major comment below and will revise the manuscript to incorporate clarifications, additional details, and sensitivity discussions where feasible.

read point-by-point responses

Referee: [Abstract / unified empirical framework] Abstract and unified empirical framework: The simulatability boundary is positioned via compiled depth plus an effective noise proxy derived primarily from reported two-qubit gate error rates. However, without sensitivity checks or bounds on contributions from single-qubit errors, readout noise, or idle errors during routing/SWAP layers, the claimed architecture-dependent margin shifts (sparse vs. dense) rest on an incomplete noise model that may mis-rank the devices. This approximation is load-bearing for the central quantitative conclusion.

Authors: We agree that the effective noise proxy, derived primarily from two-qubit gate error rates, is a simplification. While two-qubit errors dominate in current superconducting and trapped-ion devices, we will add a dedicated subsection in the revised manuscript providing bounds on the relative contributions of single-qubit, readout, and idle errors during routing. This will include a sensitivity analysis showing that the architecture-dependent ranking of margins remains qualitatively robust under reasonable variations in these terms, as the additional noise sources scale similarly across the compared device models. revision: yes
Referee: [native-gateset-aware compilation experiments] Native-gateset-aware compilation experiments: For the seven device models, the paper must detail the exact compilation procedure, including how routing overhead is quantified in depth and whether non-uniform error propagation from extra SWAPs is folded into the effective noise or boundary calculation. Absent this, the depth-to-margin mapping for a fixed IQP instance cannot be verified as robust.

Authors: We will expand the Methods and Supplementary Information sections to provide the precise compilation workflow, including the routing algorithm employed, the metric used to quantify depth overhead (total two-qubit gate count after decomposition), and the handling of SWAP layers. Our effective noise proxy applies the reported average two-qubit error rate uniformly to all two-qubit operations, including those arising from routing; we will explicitly state this approximation and note that non-uniform propagation is not modeled at the gate level but is captured at the aggregate depth level. revision: yes
Referee: [analytic depth estimates] Analytic depth estimates for sparse geometries: The translation from 2D-grid (and other) connectivity overhead to simulatability margin assumes the boundary depends primarily on total depth and the scalar noise proxy. The paper should provide the explicit functional form or reference used for the boundary and test whether the overhead formula holds under the paper's own noise approximation.

Authors: The simulatability boundary follows the depth-dependent threshold derived in the noisy IQP literature (specifically the exponential decay of the output distribution's total variation distance with depth under local noise). We will insert the explicit functional form, together with the relevant reference, into the main text. We will also add a short verification subsection confirming that the analytic overhead formula for 2D grids and other sparse graphs remains consistent when evaluated under the same effective noise proxy used for the device models. revision: yes

Circularity Check

0 steps flagged

No circularity: analysis uses external topologies and reported error rates as independent inputs

full rationale

The paper derives architecture-dependent shifts in compiled IQP depth and position relative to the noisy simulatability boundary via analytic estimates for sparse graphs plus native-gate compilation experiments on seven publicly documented device topologies. Effective noise is approximated directly from reported two-qubit gate error rates (external data) rather than fitted within the paper. No equation or claim reduces by construction to a self-defined quantity, a fitted parameter renamed as prediction, or a load-bearing self-citation; the simulatability boundary itself is invoked as an external benchmark. The derivation therefore remains self-contained against independent hardware data.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The abstract relies on standard complexity assumptions for IQP hardness and conventional noise models; no new free parameters, axioms, or invented entities are introduced.

axioms (1)

domain assumption IQP sampling is classically hard under standard complexity-theoretic assumptions in the ideal case
Invoked to establish IQP as a candidate for quantum advantage before discussing noise effects.

pith-pipeline@v0.9.0 · 5593 in / 1179 out tokens · 80822 ms · 2026-05-10T15:13:32.572449+00:00 · methodology

discussion (0)

Forward citations

Cited by 1 Pith paper

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Compositional Quantum Heuristics for Max-Clique Detection
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Compositional quantum circuits with symmetry-induced invariant losses produce trainable equivariant quantum GNNs that generalize on max-clique problems and improve hybrid recursive search accuracy and scalability.

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