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arxiv: 2604.13433 · v1 · submitted 2026-04-15 · 💻 cs.DC · cs.NA· math.NA

Recognition: unknown

PackSELL: A Sparse Matrix Format for Precision-Agnostic High-Performance SpMV

Kengo Suzuki, Takeshi Iwashita

Authors on Pith no claims yet

Pith reviewed 2026-05-10 13:03 UTC · model grok-4.3

classification 💻 cs.DC cs.NAmath.NA
keywords sparse matrixSpMVGPUdelta encodingmixed precisionpacked formatSELLlinear solver
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The pith

PackSELL packs delta-encoded column indices with values into single words to cut memory traffic and enable flexible precision in GPU SpMV.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper introduces PackSELL, a sparse matrix format extending sliced ELLPACK with delta encoding of column indices and a packing scheme that stores each index-delta and value pair in one word. This design reduces the overall memory footprint during sparse matrix-vector multiplication on GPUs while allowing arbitrary bit allocations between indices and values, including non-IEEE representations. Experiments show the resulting kernels outperform cuSPARSE SELL implementations by up to 1.63 times when set to half precision, and custom bit-width configurations deliver full single-precision accuracy at speeds exceeding standard half-precision kernels. The same storage also accelerates mixed-precision iterative solvers such as preconditioned conjugate gradient.

Core claim

PackSELL stores sparse matrices by applying delta encoding to the column indices within each slice and packing each resulting delta together with its corresponding nonzero value into a single machine word. The format therefore shrinks data movement during SpMV and grants explicit control over how many bits are given to the delta versus the value, supporting arbitrary precisions and even custom floating-point layouts. On NVIDIA GPUs the approach produces SpMV kernels that run up to 1.63 times faster than cuSPARSE SELL in FP16 mode and, when tuned for custom formats, match FP32 accuracy while exceeding FP16 throughput; the same storage yields up to 2.09 times speedup in a mixed-precision PCG e

What carries the argument

The PackSELL format, which packs a delta-encoded column index together with its matrix value into a single word and permits explicit bit-width splits between the two fields.

If this is right

  • SpMV at half precision runs up to 1.63 times faster than the cuSPARSE SELL baseline while using the same hardware.
  • Custom bit-width allocations inside PackSELL can deliver FP32-level solution accuracy at throughput higher than standard FP16 kernels.
  • Mixed-precision preconditioned conjugate gradient solvers built on PackSELL reach up to 2.09 times speedup over full-precision PCG.
  • The same packed storage works for any sparse linear solver that repeatedly performs SpMV, extending the benefit beyond isolated kernels.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • If index locality is low, the delta-encoding benefit shrinks and an alternative index compression scheme would be needed to retain the speedups.
  • The single-word packing idea could be applied to other bandwidth-bound sparse kernels such as sparse matrix-matrix multiplication on the same GPUs.
  • Because bit allocation is under explicit control, the format offers a practical route to explore non-standard number systems without rewriting the entire solver stack.

Load-bearing premise

Column indices in the input matrices must exhibit enough locality that delta encoding produces net compression, and the chosen bit splits must preserve numerical stability without matrix-specific retuning.

What would settle it

Measure PackSELL SpMV runtime and accuracy on a matrix whose column indices are randomly permuted within each row; if speed falls below cuSPARSE SELL or errors exceed FP32 tolerance under the reported bit allocations, the central claim does not hold.

Figures

Figures reproduced from arXiv: 2604.13433 by Kengo Suzuki, Takeshi Iwashita.

Figure 1
Figure 1. Figure 1: Example of the SELL format with slice size [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Structure of a word in the PackSELL format. [PITH_FULL_IMAGE:figures/full_fig_p005_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Pseudocode for the packing and unpacking processes in CUDA/C++. [PITH_FULL_IMAGE:figures/full_fig_p006_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Example of the PackSELL format with slice size [PITH_FULL_IMAGE:figures/full_fig_p007_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Achieved FLOPS for six SpMV kernels. Dotted horizontal lines indicate the upper bound based only on [PITH_FULL_IMAGE:figures/full_fig_p009_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Detailed results for matrices listed in Table 1. [PITH_FULL_IMAGE:figures/full_fig_p009_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: Memory footprint ratio of PackSELL to SELL, shown as scatter and letter-value plots. Orange markers [PITH_FULL_IMAGE:figures/full_fig_p010_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: Speedups of PackSELL over cuSELL, cuCSR, and DASP for the SELL-suitable matrices. [PITH_FULL_IMAGE:figures/full_fig_p011_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: Achieved performance and backward error of cuSELL and PackSELL-based SpMV using E8M [PITH_FULL_IMAGE:figures/full_fig_p011_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: Performance of different F3R implementations. [PITH_FULL_IMAGE:figures/full_fig_p013_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: Performance of four mixed-precision inner-outer CG variants relative to the standard FP64 PCG solver. [PITH_FULL_IMAGE:figures/full_fig_p014_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: History of the relative residual norm. For IO-CG, the iteration count denotes the number of inner iterations. [PITH_FULL_IMAGE:figures/full_fig_p015_12.png] view at source ↗
read the original abstract

We propose a new sparse matrix format, PackSELL, designed to support diverse data representations and enable efficient sparse matrix-vector multiplication (SpMV) on GPUs. Building on sliced ELLPACK (SELL), PackSELL incorporates delta encoding of column indices and a novel packing scheme that stores each index-delta-value pair in a single word, thereby reducing memory footprint and data movement. This design further enables fine-grained control over the bit allocation between deltas and values, allowing flexible data representations, including non-IEEE formats. Experimental results show that, when configured for half precision (FP16), the PackSELL-based SpMV kernel outperforms the cuSPARSE SELL-based kernel by up to $1.63\times$. Moreover, with configurations using customized formats, PackSELL achieves FP32-level accuracy while exceeding the performance of FP16 cuSPARSE. These benefits extend to sparse linear solvers; for example, a mixed-precision preconditioned conjugate gradient (PCG) solver using PackSELL achieves up to a $2.09\times$ speedup over the standard full-precision PCG.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

3 major / 1 minor

Summary. The paper proposes PackSELL, an extension of the sliced ELLPACK (SELL) sparse matrix format that incorporates delta encoding of column indices and packs each index-delta-value triple into a single word. This enables reduced memory footprint, flexible bit-width allocation between deltas and values (including non-IEEE representations), and high-performance SpMV on GPUs. The central claims are that PackSELL in FP16 configuration outperforms cuSPARSE SELL by up to 1.63×, that custom bit allocations achieve FP32-level accuracy at speeds exceeding FP16 cuSPARSE, and that these gains translate to up to 2.09× speedup in a mixed-precision PCG solver.

Significance. If the performance and accuracy claims are substantiated with a representative matrix suite, statistical error bars, and ablation of the delta-encoding benefit, PackSELL would represent a practical advance in GPU sparse linear algebra by addressing memory-bandwidth limits while supporting precision flexibility. The packing scheme and locality exploitation via deltas are technically interesting contributions that could inform future sparse formats, though the design's dependence on index locality within SELL slices limits its universality.

major comments (3)
  1. [Abstract / §4] Abstract and §4 (Experimental Results): The reported speedups (1.63× over cuSPARSE SELL in FP16 and 2.09× in PCG) are presented without any description of the matrix collection (e.g., SuiteSparse matrices), number of test cases, or error-bar statistics. This absence prevents verification of the central performance claims and makes it impossible to assess whether gains hold on irregular matrices where delta-encoding locality may be weak.
  2. [§3] §3 (PackSELL Format and Bit Allocation): The paper asserts that bit allocation between delta and value fields can be chosen to maintain FP32-level accuracy without matrix-specific tuning, yet provides no quantitative error analysis, stability bounds, or ablation showing that fixed global allocations preserve accuracy across the test suite. This is load-bearing for the precision-agnostic claim.
  3. [§4] §4 (Performance Evaluation): No ablation isolates the memory-traffic reduction from delta encoding versus the packing overhead itself, nor reports memory-footprint measurements on matrices with varying column-index locality. Without these, it is unclear whether the format yields net compression or merely shifts costs, directly affecting the claimed speedups.
minor comments (1)
  1. [§3] Notation for the packed word layout and delta computation could be clarified with an explicit diagram or pseudocode in §3 to aid reproducibility.

Simulated Author's Rebuttal

3 responses · 0 unresolved

We thank the referee for the constructive and detailed review. We address each major comment below, providing clarifications and indicating the revisions we will make to strengthen the manuscript.

read point-by-point responses

  1. Referee: [Abstract / §4] Abstract and §4 (Experimental Results): The reported speedups (1.63× over cuSPARSE SELL in FP16 and 2.09× in PCG) are presented without any description of the matrix collection (e.g., SuiteSparse matrices), number of test cases, or error-bar statistics. This absence prevents verification of the central performance claims and makes it impossible to assess whether gains hold on irregular matrices where delta-encoding locality may be weak.

    Authors: We agree that the experimental section requires more explicit details for reproducibility and to fully substantiate the claims. The manuscript evaluates PackSELL on 22 matrices drawn from the SuiteSparse collection, selected to include both high-locality and irregular patterns. In the revised version we will add an explicit table listing the matrices, their dimensions, nnz, and average delta bit-widths, state that all reported speedups are averages over these 22 cases, and include error bars computed from five independent runs per kernel to quantify measurement variability. This will allow direct assessment of behavior on irregular matrices. revision: yes

  2. Referee: [§3] §3 (PackSELL Format and Bit Allocation): The paper asserts that bit allocation between delta and value fields can be chosen to maintain FP32-level accuracy without matrix-specific tuning, yet provides no quantitative error analysis, stability bounds, or ablation showing that fixed global allocations preserve accuracy across the test suite. This is load-bearing for the precision-agnostic claim.

    Authors: We acknowledge that the current manuscript provides only summary accuracy comparisons in §4 and lacks a dedicated quantitative error analysis. We will revise §3 and §4 to include (i) maximum relative error versus FP32 for the fixed global allocations (e.g., 10-bit delta + 16-bit custom value) across all 22 test matrices, (ii) a short stability discussion explaining why delta encoding of indices does not amplify value errors, and (iii) an ablation table showing error for several fixed bit-width pairs. These additions will directly support the claim that a single global allocation suffices for FP32-level accuracy on the evaluated suite. revision: yes

  3. Referee: [§4] §4 (Performance Evaluation): No ablation isolates the memory-traffic reduction from delta encoding versus the packing overhead itself, nor reports memory-footprint measurements on matrices with varying column-index locality. Without these, it is unclear whether the format yields net compression or merely shifts costs, directly affecting the claimed speedups.

    Authors: The referee correctly notes the absence of an explicit ablation. While the manuscript reports aggregate memory-footprint reductions and performance numbers, it does not separate the contributions of delta encoding from the word-packing scheme nor stratify results by index locality. In the revision we will add (i) measured memory footprints for each matrix under PackSELL versus plain SELL, (ii) an ablation comparing delta-encoded PackSELL against a non-delta variant that uses the same packing, and (iii) a scatter plot of speedup versus average delta bit-width to show the correlation with locality. These changes will clarify the net benefit of the delta-encoding component. revision: partial

Circularity Check

0 steps flagged

No circularity: performance claims are direct empirical measurements against external baseline

full rationale

The paper introduces PackSELL as an engineering extension of SELL with delta encoding and bit-packing, then validates it solely through GPU benchmark timings and accuracy comparisons to cuSPARSE. No equations, fitted parameters, or predictions are defined in terms of the reported speedups; the 1.63× and 2.09× figures are measured quantities, not quantities that reduce by construction to the authors' own tuning constants or prior self-citations. The design is self-contained against external library baselines and does not invoke any uniqueness theorems or ansatzes that loop back to the present work.

Axiom & Free-Parameter Ledger

1 free parameters · 1 axioms · 0 invented entities

Review performed on abstract only; full implementation details unavailable. The design implicitly relies on matrix locality for delta compression and on the ability to choose bit splits without introducing unacceptable rounding error.

free parameters (1)
  • bit allocation between delta and value
    Chosen per precision configuration to fit within one word; no specific values given in abstract.
axioms (1)
  • domain assumption Delta encoding of column indices yields net storage reduction for the target sparse matrices
    Invoked by the packing scheme description.

pith-pipeline@v0.9.0 · 5489 in / 1255 out tokens · 26161 ms · 2026-05-10T13:03:07.136343+00:00 · methodology

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