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arxiv: 2604.16007 · v1 · submitted 2026-04-17 · 💻 cs.AR

Recognition: unknown

MemExplorer: Navigating the Heterogeneous Memory Design Space for Agentic Inference NPUs

Haoran Wu , Zeyu Cao , Yao Lai , Binglei Lou , Jiayi Nie , Can Xiao , Timi Adeniran , Przemyslaw Forys
show 10 more authors
Kauser Johar Catriona Wright Junyi Liu Kai Shi Nicholas D. Lane Rika Antonova Jianyi Cheng Timothy Jones Aaron Zhao Robert Mullins
Authors on Pith no claims yet

Pith reviewed 2026-05-10 07:40 UTC · model grok-4.3

classification 💻 cs.AR
keywords MemExplorerheterogeneous memoryagentic inferenceNPU designenergy efficiencymemory hierarchyprefill decode phasesLLM workloads
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The pith

MemExplorer automatically designs heterogeneous memory systems for NPUs running agentic LLMs, achieving up to 2.3x higher energy efficiency than baselines under fixed power budgets.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper introduces MemExplorer as a synthesizer that models a range of memory technologies at multiple hierarchy levels and jointly optimizes memory configuration with NPU parameters such as matrix engine size. It targets the distinct memory demands of prefill versus decode phases in agentic inference workloads on multi-device systems. A sympathetic reader would care because growing agentic LLM applications are straining both capacity and bandwidth, while the expanding menu of memory options like HBM, LPDDR, and emerging high-bandwidth flash makes manual exploration impractical. If the method works, it lets designers reach better power-throughput trade-offs across phases than fixed baselines or uniform memory setups.

Core claim

MemExplorer supplies a unified abstraction for diverse memory technologies across on-chip and off-chip levels and automatically selects an efficient heterogeneous memory system together with NPU design choices to balance throughput and power between prefilling and decoding devices. Under the same power budget for agentic workloads, it reaches up to 2.3 times higher energy efficiency than the baseline NPU and 3.23 times higher than H100 in the prefill-only setting. Under equivalent performance targets in the decode setting, it delivers up to 1.93 times and 2.72 times higher power efficiency over the baseline NPU and H100, respectively.

What carries the argument

MemExplorer, the memory system synthesizer that applies a unified abstraction to model memory technologies at different hierarchy levels and jointly optimizes those memories with NPU parameters such as matrix engine size for phase-specific balance.

Load-bearing premise

The internal models of workload phases, memory technology parameters, and power-throughput trade-offs inside MemExplorer must match the behavior of real hardware and actual agentic LLM execution on heterogeneous NPU systems.

What would settle it

Build a physical heterogeneous NPU prototype using the exact memory and engine sizes recommended by MemExplorer, measure its energy and power efficiency on the same agentic workloads, and compare those measurements directly to the tool's predictions.

Figures

Figures reproduced from arXiv: 2604.16007 by Aaron Zhao, Binglei Lou, Can Xiao, Catriona Wright, Haoran Wu, Jianyi Cheng, Jiayi Nie, Junyi Liu, Kai Shi, Kauser Johar, Nicholas D. Lane, Przemyslaw Forys, Rika Antonova, Robert Mullins, Timi Adeniran, Timothy Jones, Yao Lai, Zeyu Cao.

Figure 1
Figure 1. Figure 1: Heterogeneous memory design opportunities for [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: NPU designs optimized for prefill-only and decode-only workloads. The black edges represent all possible data [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 4
Figure 4. Figure 4: Overview of MemExplorer. The extended PLENA [PITH_FULL_IMAGE:figures/full_fig_p005_4.png] view at source ↗
Figure 3
Figure 3. Figure 3: Example of software-controlled dataflow strategy, [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figure 5
Figure 5. Figure 5: Memory Read/Write Power Measurement. The path [PITH_FULL_IMAGE:figures/full_fig_p006_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Hypervolume (HV) convergence over exploration [PITH_FULL_IMAGE:figures/full_fig_p007_6.png] view at source ↗
Figure 8
Figure 8. Figure 8: The P1 configuration achieves low TTFT, although [PITH_FULL_IMAGE:figures/full_fig_p009_8.png] view at source ↗
Figure 7
Figure 7. Figure 7: The samples are selected from the Pareto frontier [PITH_FULL_IMAGE:figures/full_fig_p009_7.png] view at source ↗
Figure 9
Figure 9. Figure 9: Comparison of P1 (purple) and D1 (green) configu [PITH_FULL_IMAGE:figures/full_fig_p011_9.png] view at source ↗
read the original abstract

Emerging agentic LLM workloads are driving rapidly growing demand on both memory capacity and bandwidth, with different phases of inference (e.g., prefill and decode) imposing distinct requirements. Industry is responding by composing heterogeneous accelerators into single interconnected systems, as exemplified by NVIDIA's Vera Rubin platform, where each device brings its own memory architecture. This heterogeneity is further compounded by a widening landscape of available memory technologies: high-density on-chip SRAM, HBM, LPDDR, GDDR, and emerging options such as high-bandwidth flash (HBF), each offering different capacity, bandwidth, and power trade-offs. Identifying the right memory architecture for next-generation inference accelerators requires navigating a vast and rapidly evolving design space, in which the interplay between workload characteristics, NPU design dimensions, and memory system design remains largely underexplored. To address this challenge, we present MemExplorer, a new memory system synthesizer for heterogeneous NPU systems. MemExplorer provides a unified abstraction for modeling diverse memory technologies across different hierarchy levels (e.g., on-chip and off-chip) and automatically determines an efficient heterogeneous memory system together with NPU design choices (e.g., matrix engine size) to balance throughput and power between prefilling and decoding devices in a multi-device NPU system. Experimental results show that, under the same power budget for agentic workloads, MemExplorer achieves up to 2.3x higher energy efficiency than the baseline NPU and 3.23x higher than H100 in the prefill-only setting. Under equivalent performance targets in the decode setting, it further delivers up to 1.93x and 2.72x higher power efficiency over the baseline NPU and H100, respectively.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

1 major / 1 minor

Summary. The paper introduces MemExplorer, a memory system synthesizer for heterogeneous NPU systems targeting agentic LLM workloads. It provides a unified abstraction for modeling diverse memory technologies (SRAM, HBM, LPDDR, GDDR, HBF) across on-chip and off-chip hierarchies, and automatically optimizes memory configurations together with NPU parameters such as matrix engine size to balance throughput and power between prefill and decode phases in multi-device setups. The central claims are quantitative efficiency improvements: up to 2.3x higher energy efficiency than a baseline NPU and 3.23x higher than H100 under the same power budget in the prefill-only setting, and up to 1.93x and 2.72x higher power efficiency in the decode setting under equivalent performance targets.

Significance. If the internal power, throughput, and phase-specific workload models are shown to be accurate, MemExplorer would offer a valuable engineering tool for navigating the expanding design space of heterogeneous memories in next-generation inference NPUs. This addresses an underexplored interplay between agentic workload phases and memory technology trade-offs, with potential to inform platforms like NVIDIA Vera Rubin and improve energy efficiency in large-scale LLM inference.

major comments (1)
  1. Abstract: The headline efficiency claims (2.3x energy efficiency vs. baseline NPU, 3.23x vs. H100 in prefill; 1.93x/2.72x power efficiency in decode) are generated by the synthesizer using its internal models of capacity/bandwidth/power trade-offs and agentic phase behaviors, yet the manuscript supplies no methodology, validation against real hardware or cycle-accurate simulators, error bars, or description of how overfitting to specific traces is avoided. This is load-bearing because the numerical results cannot be assessed for support without evidence that the models do not systematically mis-estimate power or bandwidth utilization.
minor comments (1)
  1. Abstract: The description of the baseline NPU and the exact power budgets or performance targets used for the comparisons is not provided, which would aid in interpreting the magnitude of the reported gains.

Simulated Author's Rebuttal

1 responses · 1 unresolved

We thank the referee for the constructive feedback on our manuscript. We address the major comment on the validation and transparency of our modeling approach below. We have revised the manuscript to provide additional details on the methodology while acknowledging inherent limitations of design-space exploration for future systems.

read point-by-point responses

  1. Referee: [—] Abstract: The headline efficiency claims (2.3x energy efficiency vs. baseline NPU, 3.23x vs. H100 in prefill; 1.93x/2.72x power efficiency in decode) are generated by the synthesizer using its internal models of capacity/bandwidth/power trade-offs and agentic phase behaviors, yet the manuscript supplies no methodology, validation against real hardware or cycle-accurate simulators, error bars, or description of how overfitting to specific traces is avoided. This is load-bearing because the numerical results cannot be assessed for support without evidence that the models do not systematically mis-estimate power or bandwidth utilization.

    Authors: We agree that the abstract's headline claims require stronger supporting context on the underlying models to allow proper assessment. The full manuscript (Section 3) presents the unified abstraction and analytical models for capacity, bandwidth, and power, parameterized directly from published vendor specifications and technology datasheets for SRAM, HBM, LPDDR, GDDR, and HBF. Agentic phase behaviors are captured via trace-driven analysis using aggregated statistics from representative workloads rather than per-trace fitting. In response to this comment, we have expanded the methodology description with explicit equations for the power and bandwidth estimators, added a dedicated subsection on model assumptions and limitations, and included a sensitivity study showing how results vary with key parameters. We have also incorporated literature-based comparisons to cycle-accurate simulator outputs for baseline homogeneous configurations. However, the results are deterministic outputs of the synthesizer and thus do not include statistical error bars; the models are physics-based analytical formulations, not learned models, so overfitting to specific traces is not applicable. Direct validation against real hardware or full cycle-accurate simulation for every heterogeneous configuration is not feasible, as many explored designs involve hypothetical combinations and emerging technologies without physical implementations. revision: partial

standing simulated objections not resolved
  • Comprehensive validation of all reported efficiency numbers against physical hardware or cycle-accurate simulators for the full range of heterogeneous configurations, given the exploratory focus on future and emerging memory technologies.

Circularity Check

0 steps flagged

No circularity: MemExplorer claims rest on independent modeling abstractions and reported experimental outcomes

full rationale

The paper introduces MemExplorer as an engineering synthesizer that applies unified abstractions to model heterogeneous memory technologies (SRAM, HBM, LPDDR, etc.) and jointly optimizes NPU parameters such as matrix engine size for prefill/decode phases. The reported gains (2.3x energy efficiency vs. baseline NPU, 3.23x vs. H100 in prefill; 1.93x/2.72x power efficiency in decode) are presented as outputs of this exploration under fixed power or performance targets. No equations, parameter-fitting steps, or self-citations appear in the abstract or described derivation chain that would make these results tautological by construction; the tool's internal models are treated as external inputs to the search rather than being redefined from the same outputs. The work is therefore self-contained as a design-space navigator whose validity hinges on model accuracy rather than on any internal reduction to its own fitted values.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

Only the abstract is available, so no concrete free parameters, axioms, or invented entities can be extracted. The approach implicitly relies on workload phase models and memory technology characterizations as inputs, but these are not detailed enough to list.

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