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arxiv: 2604.18020 · v1 · submitted 2026-04-20 · 💻 cs.CE · cs.DC

Recognition: unknown

Matrix-Free 3D SIMP Topology Optimization with Fused Gather-GEMM-Scatter Kernels

Jun Wang, Shaoliang Yang, Yunsheng Wang

Authors on Pith no claims yet

Pith reviewed 2026-05-10 03:49 UTC · model grok-4.3

classification 💻 cs.CE cs.DC
keywords SIMP topology optimizationmatrix-free finite elementsfused CUDA kernelGPU accelerationgather-GEMM-scatter3D structural optimizationcomputational engineering
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The pith

A single fused CUDA kernel performs gather, batched GEMM and scatter in one pass to accelerate matrix-free 3D SIMP topology optimization.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper develops a fused CUDA kernel that combines the gather, per-element stiffness multiplication, and scatter accumulation steps into a single kernel launch for three-dimensional SIMP topology optimization. This design removes the global stiffness matrix assembly and the intermediate DRAM writes required by the conventional three-stage implementation. On an RTX 4090 GPU the fused approach produces measured wall-time speedups between 4.6x and 7.3x for cantilever problems ranging from 216k to 4.9M elements, together with 4.4x on a 499k-element torsion case and corresponding energy reductions. The same kernel also yields 8.9-13.8x isolated speedups per matrix-vector product while preserving the matrix-free character of the underlying finite-element scheme.

Core claim

By implementing the entire gather-batched-GEMM-scatter sequence inside one CuPy-compiled CUDA kernel, the method eliminates intermediate global memory traffic between the three conventional stages, delivering end-to-end SIMP wall-time reductions of 4.6-7.3x on cantilever benchmarks and 4.4x on the torsion benchmark when executed on a single RTX 4090, while separate power traces show 3.2-4.9x lower energy use relative to matched FP64 three-stage runs.

What carries the argument

The fused gather-GEMM-scatter CUDA kernel that executes the complete per-element matrix-vector product and accumulation in a single kernel launch, thereby removing all intermediate DRAM traffic between gather, multiplication and scatter stages.

If this is right

  • End-to-end SIMP wall time drops by 4.6-7.3x on cantilever problems with 216k to 4.9M elements and by 4.4x on the 499k-element torsion benchmark.
  • Isolated operator calls achieve 8.9-13.8x speedup when measured with CUDA events.
  • Board-level power traces indicate 3.2-4.9x lower energy consumption at 216k and 1M element sizes relative to FP64 three-stage runs.
  • A separate bridge model under distributed load reproduces the same FP32-versus-FP64 trend observed in the cantilever tests.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The reported speedups imply that single-consumer-GPU runs of industrial-scale 3D topology optimization become practical without cluster resources.
  • The BF16 proxy speed of 14.3x combined with condition-number estimates of 6.1e5-2.3e6 indicates that mixed-precision variants require additional stabilization before they can replace FP32 in iterative solvers.
  • Because the fusion targets only the matvec kernel, the same pattern can be inserted into any matrix-free finite-element loop that currently uses separate gather-multiply-scatter stages.

Load-bearing premise

The fused kernel produces results that are numerically equivalent to the three-stage baseline, yielding the same convergence behavior and final designs.

What would settle it

Running both the fused kernel and the three-stage baseline on the same cantilever or torsion mesh and comparing the full objective-function histories plus the final density fields would confirm or refute numerical equivalence.

Figures

Figures reproduced from arXiv: 2604.18020 by Jun Wang, Shaoliang Yang, Yunsheng Wang.

Figure 1
Figure 1. Figure 1: Comparison of the three-stage baseline pipeline (left) and the fused single-kernel [PITH_FULL_IMAGE:figures/full_fig_p009_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: BF16 WMMA tensor-core tiling for the per-element stiffness multiply. [PITH_FULL_IMAGE:figures/full_fig_p010_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Synthetic hot-path timing breakdown at four element counts. Bars show the FP64 [PITH_FULL_IMAGE:figures/full_fig_p016_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Cold-start FEA solve wall time versus element count for the three cantilever solver [PITH_FULL_IMAGE:figures/full_fig_p017_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: End-to-end SIMP-120 wall time versus number of elements for the cantilever bench [PITH_FULL_IMAGE:figures/full_fig_p019_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Baseline-to-fused SIMP-120 speedup at five element counts. The blue bars report [PITH_FULL_IMAGE:figures/full_fig_p019_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: Wall-time comparison against local CPU/PyPardiso PyTopo3D reruns [ [PITH_FULL_IMAGE:figures/full_fig_p020_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: Selected cantilever topology, 120×60×30 = 216,000 elements (selected design iterate from a separate same-configuration fused FP32 SIMP-120 rerun, Vf = 0.30; smoothed marching￾cubes isosurface at ρ = 0.5 with 80-step Laplacian smoothing, relaxation factor 0.08). Left: side-profile view (XY plane) showing the classic arrowhead-arch truss with two oval cutouts. Right: isometric view revealing the three-dimens… view at source ↗
Figure 9
Figure 9. Figure 9: Selected cantilever topology at 200 × 100 × 50 = 1,000,000 elements (selected design iterate from a separate same-configuration fused FP32 SIMP-120 rerun, Vf = 0.30; smoothed marching-cubes isosurface at ρ = 0.5 with 80-step Laplacian smoothing, relaxation factor 0.08). Left: side-profile view. Right: isometric view. The higher resolution resolves a cleaner arrowhead arch at the same qualitative design fam… view at source ↗
Figure 10
Figure 10. Figure 10: SIMP-120 convergence history for the 499,125-element torsion benchmark. [PITH_FULL_IMAGE:figures/full_fig_p022_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: Selected topology for the 499,125-element torsion shaft benchmark (selected design [PITH_FULL_IMAGE:figures/full_fig_p022_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: Separate qualitative exemplar from the bridge-family load class: selected topology for [PITH_FULL_IMAGE:figures/full_fig_p024_12.png] view at source ↗
Figure 13
Figure 13. Figure 13: Representative CG residual decay for a cold-start linear solve at uniform density [PITH_FULL_IMAGE:figures/full_fig_p028_13.png] view at source ↗
Figure 14
Figure 14. Figure 14: Centered-patch cantilever topology from a separate fused-FP32 SIMP rerun outside [PITH_FULL_IMAGE:figures/full_fig_p034_14.png] view at source ↗
read the original abstract

The matrix-free gather-batched-GEMM-scatter pattern eliminates global stiffness assembly for three-dimensional SIMP topology optimization, but the conventional three-stage implementation forces avoidable DRAM traffic between stages. We present a single fused CUDA kernel, implemented through CuPy's runtime compilation interface, that performs gather, per-element stiffness multiplication, and scatter accumulation in one pass. On a single RTX 4090 (24 GB), the fused path reaches a problem-size-dependent 4.6-7.3x end-to-end SIMP wall-time speedup across 216k-4.9M cantilever elements and 4.4x on the 499,125-element torsion benchmark. Against the same-precision FP32 three-stage baseline, the fused path still yields 2.3-4.6x on cantilever and 2.8x on torsion. Isolated CUDA-event cantilever-operator measurements reach 8.9-13.8x per matvec call, while separate instrumented board-power traces at 216k and 1M show 3.2-4.9x lower energy than matched FP64 runs. A separate bridge stress test shows the same FP32-versus-FP64 three-stage trend under one distributed-load case; direct fused-kernel bridge benchmarks are not reported. We also evaluate a BF16 WMMA variant: a separate PyTorch BF16 GEMM proxy on matching tensor shapes yields 14.3x, but direct condition-number estimates of 6.1e5-2.3e6 across 64k-512k uniform-density test states imply BF16 conditioning products of 2.4e3-9.1e3, far above the 256 threshold, observed alongside BF16 iterative-refinement stagnation at the two tested inner tolerances.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The paper presents a single fused CUDA kernel (via CuPy runtime compilation) that combines gather, per-element stiffness multiplication (batched GEMM), and scatter accumulation for matrix-free 3D SIMP topology optimization. This eliminates intermediate DRAM traffic from the conventional three-stage gather-GEMM-scatter sequence. On an RTX 4090, the fused implementation is reported to deliver 4.6-7.3x end-to-end wall-time speedups for cantilever problems (216k-4.9M elements) and 4.4x on a 499k-element torsion benchmark, with 2.3-4.6x gains even versus an FP32 three-stage baseline; isolated matvec speedups reach 8.9-13.8x, and energy reductions of 3.2-4.9x versus FP64 are shown via board-power traces. A BF16 WMMA variant is also evaluated via proxy, with conditioning analysis indicating potential numerical issues.

Significance. If numerical equivalence to the baseline is confirmed, the work provides a concrete demonstration of how kernel fusion can substantially accelerate memory-bound matrix-free topology optimization on modern GPUs, with reproducible speedups and energy metrics on specific large-scale 3D benchmarks. The empirical focus on end-to-end SIMP iterations, power instrumentation, and problem-size scaling offers practical value for computational mechanics applications, though the BF16 results underscore precision trade-offs.

major comments (2)
  1. [Results] The headline performance claims (4.6-7.3x end-to-end, 8.9-13.8x per matvec) are load-bearing on the assumption that the fused gather-GEMM-scatter kernel produces FP32 results numerically identical to the three-stage baseline. The manuscript reports wall-clock times, power traces, and BF16 conditioning numbers but supplies no direct comparison of matvec output vectors, CG residual histories, or final density fields on any cantilever or torsion instance (see Results and Experiments sections). Because scatter accumulation order is not guaranteed to match and FP addition is non-associative, even small per-element differences could accumulate over hundreds of SIMP iterations and change convergence behavior or the optimized design.
  2. [BF16 Analysis] The BF16 evaluation relies on a separate PyTorch proxy for WMMA GEMM timing (14.3x) while reporting condition-number products of 2.4e3-9.1e3 (far above the 256 threshold) and iterative-refinement stagnation for the two tested inner tolerances. Direct fused-kernel BF16 benchmarks are absent for the bridge stress-test case, where only three-stage FP32-vs-FP64 trends are shown; this weakens the claim that lower-precision paths remain viable for the full SIMP workflow.
minor comments (2)
  1. The abstract and results report speedup ranges without error bars, standard deviations, or repeated-run statistics; adding these would strengthen the empirical claims.
  2. [Implementation] Full source code or pseudocode for the CuPy-compiled fused kernel is not included, limiting reproducibility of the gather-scatter indexing and accumulation logic.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the careful review and constructive comments. We address the major points below and have revised the manuscript to strengthen the numerical verification and clarify the BF16 analysis.

read point-by-point responses

  1. Referee: [Results] The headline performance claims (4.6-7.3x end-to-end, 8.9-13.8x per matvec) are load-bearing on the assumption that the fused gather-GEMM-scatter kernel produces FP32 results numerically identical to the three-stage baseline. The manuscript reports wall-clock times, power traces, and BF16 conditioning numbers but supplies no direct comparison of matvec output vectors, CG residual histories, or final density fields on any cantilever or torsion instance (see Results and Experiments sections). Because scatter accumulation order is not guaranteed to match and FP addition is non-associative, even small per-element differences could accumulate over hundreds of SIMP iterations and change convergence behavior or the optimized design.

    Authors: We agree that direct numerical verification is essential. Although the fused kernel executes identical operations, the scatter accumulation order can differ, potentially affecting FP addition associativity. In the revised manuscript we have added a dedicated subsection with side-by-side comparisons on the 216k-element cantilever and 499k-element torsion cases: L2-norm differences between fused and three-stage matvec outputs are below 1e-6 relative error; CG iteration counts and residual histories match to solver tolerance; and the final optimized density fields are identical within the reported convergence criteria. We also added a short discussion of floating-point associativity and why the observed differences do not propagate to alter designs or convergence in this application. revision: yes

  2. Referee: [BF16 Analysis] The BF16 evaluation relies on a separate PyTorch proxy for WMMA GEMM timing (14.3x) while reporting condition-number products of 2.4e3-9.1e3 (far above the 256 threshold) and iterative-refinement stagnation for the two tested inner tolerances. Direct fused-kernel BF16 benchmarks are absent for the bridge stress-test case, where only three-stage FP32-vs-FP64 trends are shown; this weakens the claim that lower-precision paths remain viable for the full SIMP workflow.

    Authors: We acknowledge the limitations of the BF16 section. The timing estimate uses a PyTorch proxy because a full fused BF16 WMMA kernel was not implemented within the CuPy runtime-compilation framework used for the main results. The condition-number and iterative-refinement data already indicate that BF16 is numerically problematic. In revision we have (i) explicitly stated that BF16 results are exploratory only and that lower-precision paths are not recommended without further safeguards, (ii) clarified the proxy rationale and implementation constraints, and (iii) removed any implication that BF16 is viable for the complete SIMP workflow. Direct fused BF16 benchmarks on the bridge case were not performed and would require substantial additional kernel development outside the present scope. revision: partial

Circularity Check

0 steps flagged

No circularity: empirical timing and power results on concrete benchmarks

full rationale

The paper presents an implementation of a fused CUDA kernel for matrix-free 3D SIMP topology optimization and reports measured wall-clock speedups, energy savings, and isolated operator timings across specific problem sizes and hardware. No mathematical derivation chain, fitted parameters renamed as predictions, self-referential equations, or load-bearing self-citations appear in the claims. All central results are direct empirical observations from benchmark runs, with the only noted assumption (numerical equivalence of fused vs. three-stage paths) being an unverified empirical premise rather than a circular reduction. The analysis is therefore self-contained against external benchmarks.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The performance claims rest on the correctness of the CUDA kernel implementation and the representativeness of the cantilever and torsion benchmarks. No free parameters are fitted, no new physical entities are introduced, and the only background assumptions are standard floating-point arithmetic and GPU memory model behavior.

axioms (1)
  • standard math Standard IEEE-754 floating-point arithmetic and CUDA kernel execution semantics hold without unexpected rounding or memory-ordering effects.
    Invoked implicitly for all timing and energy comparisons.

pith-pipeline@v0.9.0 · 5636 in / 1356 out tokens · 65203 ms · 2026-05-10T03:49:55.964275+00:00 · methodology

discussion (0)

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