pith. machine review for the scientific record. sign in

arxiv: 2604.23195 · v1 · submitted 2026-04-25 · 💻 cs.CV · cs.AI

Recognition: unknown

AnalogRetriever: Learning Cross-Modal Representations for Analog Circuit Retrieval

Yihan Wang , Lei Li , Yao Lai , Jing Wang , Yan Lu
Authors on Pith no claims yet

Pith reviewed 2026-05-08 08:35 UTC · model grok-4.3

classification 💻 cs.CV cs.AI
keywords analog circuit retrievalcross-modal learningcontrastive learningSPICE netlistsschematicsvision-language modelsgraph neural networksretrieval augmented generation
0
0 comments X

The pith

AnalogRetriever aligns schematics, netlists, and descriptions into a shared space for analog circuit retrieval.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper aims to solve the problem of searching for analog circuits when they are represented in incompatible formats such as SPICE netlists, visual schematics, and textual functional specs. It builds a cleaned tri-modal dataset and trains a model with separate encoders for each modality that are pulled into one vector space through progressive contrastive learning. A reader should care because analog IP reuse is central to efficient design, and semantic cross-modal search could replace slow manual or exact-match lookups. When plugged into an AI coding agent, the retriever raises the rate at which generated circuits pass functional tests and solves tasks that were previously out of reach.

Core claim

AnalogRetriever is a tri-modal retrieval system that first repairs a dataset of analog circuits to achieve 100% netlist compile rate, then encodes schematics and descriptions via a vision-language model while using a port-aware relational graph convolutional network for netlists, and finally aligns the three embeddings with curriculum contrastive learning to reach 75.2% average Recall@1 across six retrieval directions; integrating the system into the AnalogCoder framework further boosts functional pass rates on design tasks.

What carries the argument

Curriculum contrastive learning applied to embeddings from a vision-language model for schematics and descriptions and a port-aware relational graph convolutional network for netlists.

If this is right

  • Cross-modal retrieval accuracy improves markedly over existing single-modality or exact-match methods.
  • Retrieval-augmented generation in analog design agents achieves higher functional success rates.
  • Tasks that could not be completed before become solvable through better example retrieval.
  • The framework supports semantic search rather than requiring identical representations.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Engineers could query in natural language and receive matching netlists or schematics from a library.
  • The repair pipeline might be adapted to clean other electronic design datasets.
  • Future work could add more modalities such as simulation waveforms to the shared space.
  • Performance on real fabrication data would test whether the learned alignments hold outside the training distribution.

Load-bearing premise

The two-stage repair pipeline yields training examples that represent actual analog circuits without systematic bias, and the curriculum contrastive objective learns alignments that transfer beyond the specific dataset.

What would settle it

Running the trained retriever on a collection of analog circuits obtained independently and not passed through the repair pipeline, then checking whether Recall@1 remains near 75% or drops to baseline levels.

Figures

Figures reproduced from arXiv: 2604.23195 by Jing Wang, Lei Li, Yan Lu, Yao Lai, Yihan Wang.

Figure 1
Figure 1. Figure 1: Motivation for AnalogRetriever. (a) In tradi view at source ↗
Figure 2
Figure 2. Figure 2: AnalogRetriever framework. Three modality view at source ↗
Figure 4
Figure 4. Figure 4: Two-stage LLM-based dataset refinement pipeline. Stage 1 uses a base LLM for initial netlist repair with Ngspice validation. Stage 2 applies iterative feedback-guided refinement: a teacher model repairs failed cases using DC error logs until convergence. Stage 2a: Netlist Repair You are an expert SPICE engineer debugging a netlist that failed Ngspice compilation or DC simulation. Given the schematic image,… view at source ↗
Figure 5
Figure 5. Figure 5: Stage 2 prompts: feedback-guided netlist re view at source ↗
Figure 6
Figure 6. Figure 6: Before/after refinement. Top: SPICE netlist view at source ↗
Figure 7
Figure 7. Figure 7: Case studies showing how retrieval improves LLM-based circuit generation. Task 9: Miller amplifier view at source ↗
read the original abstract

Analog circuit design relies heavily on reusing existing intellectual property (IP), yet searching across heterogeneous representations such as SPICE netlists, schematics, and functional descriptions remains challenging. Existing methods are largely limited to exact matching within a single modality, failing to capture cross-modal semantic relationships. To bridge this gap, we present AnalogRetriever, a unified tri-modal retrieval framework for analog circuit search. We first build a high-quality dataset on top of Masala-CHAI through a two-stage repair pipeline that raises the netlist compile rate from 22\% to 100\%. Built on this foundation, AnalogRetriever encodes schematics and descriptions with a vision-language model and netlists with a port-aware relational graph convolutional network, mapping all three modalities into a shared embedding space via curriculum contrastive learning. Experiments show that AnalogRetriever achieves an average Recall@1 of 75.2\% across all six cross-modal retrieval directions, significantly outperforming existing baselines. When integrated into the AnalogCoder agentic framework as a retrieval-augmented generation module, it consistently improves functional pass rates and enables previously unsolved tasks to be completed. Our code and dataset will be released.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The paper introduces AnalogRetriever, a tri-modal retrieval framework for analog circuits that aligns SPICE netlists, schematic images, and textual descriptions in a shared embedding space. It constructs a repaired Masala-CHAI dataset via a two-stage pipeline that increases the netlist compile rate from 22% to 100%, encodes images and text with a vision-language model and netlists with a port-aware relational graph convolutional network, and trains via curriculum contrastive learning. The central empirical result is an average Recall@1 of 75.2% across the six cross-modal directions, outperforming baselines, with additional gains when the retriever is integrated as a RAG module into the AnalogCoder agentic framework.

Significance. If the repaired dataset faithfully represents real analog circuits and the learned alignments capture semantic rather than artifactual correlations, the work would meaningfully advance cross-modal IP search in analog design automation, a domain where exact single-modality matching currently dominates. The planned public release of code and dataset is a concrete strength that supports reproducibility and downstream use.

major comments (2)
  1. [§3.2] §3.2 (two-stage repair pipeline): the claim that the pipeline produces unbiased, high-quality training data rests on the unverified assumption that raising compile rate from 22% to 100% does not alter circuit behavior or introduce spurious regularities (e.g., standardized ports, component values, or connection patterns). No functional-equivalence checks, pre/post-repair topology/parameter comparisons, or ablation of retrieval performance on unrepaired netlists are reported; this directly undermines the central 75.2% Recall@1 claim and its generalization to production IP.
  2. [§5] §5 (Experiments and downstream evaluation): the reported average Recall@1 of 75.2% and the functional-pass-rate improvements in AnalogCoder are presented without baselines, statistical significance tests, error bars, or ablations isolating the contribution of the port-aware RGCN versus the curriculum contrastive objective; these omissions make it impossible to assess whether the gains are robust or attributable to the claimed cross-modal semantic alignment.
minor comments (1)
  1. [Abstract] The abstract and §1 would benefit from a brief enumeration of the six cross-modal retrieval directions (e.g., netlist-to-schematic, description-to-netlist) to clarify the evaluation protocol.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive feedback. We address each major comment below and will revise the manuscript to incorporate additional validation and reporting where appropriate.

read point-by-point responses

  1. Referee: [§3.2] §3.2 (two-stage repair pipeline): the claim that the pipeline produces unbiased, high-quality training data rests on the unverified assumption that raising compile rate from 22% to 100% does not alter circuit behavior or introduce spurious regularities (e.g., standardized ports, component values, or connection patterns). No functional-equivalence checks, pre/post-repair topology/parameter comparisons, or ablation of retrieval performance on unrepaired netlists are reported; this directly undermines the central 75.2% Recall@1 claim and its generalization to production IP.

    Authors: We agree that explicit validation of the repair pipeline is needed to support claims of high-quality, unbiased data. The two-stage pipeline performs targeted syntactic repairs (e.g., port standardization and net name fixes) intended to preserve original topologies and parameters, but these details and supporting checks were not included in the manuscript. In revision, we will add pre/post-repair comparisons of component counts, connection patterns, and parameter distributions on the full dataset, plus functional-equivalence verification via SPICE simulation on a random subset of 100 circuits. We will also report an ablation of retrieval performance using only the originally compilable netlists (the 22% subset) to demonstrate that gains are not solely due to repair artifacts. This will directly address concerns about generalization to production IP. revision: yes

  2. Referee: [§5] §5 (Experiments and downstream evaluation): the reported average Recall@1 of 75.2% and the functional-pass-rate improvements in AnalogCoder are presented without baselines, statistical significance tests, error bars, or ablations isolating the contribution of the port-aware RGCN versus the curriculum contrastive objective; these omissions make it impossible to assess whether the gains are robust or attributable to the claimed cross-modal semantic alignment.

    Authors: The manuscript reports comparisons to multiple baselines in §5 and shows outperformance, but we acknowledge the absence of statistical tests, error bars, and targeted ablations. In the revised version, we will add: error bars from five independent runs with different seeds; statistical significance testing (e.g., paired t-tests or Wilcoxon tests) on the Recall@1 and AnalogCoder pass-rate improvements; and ablations that replace the port-aware RGCN with a standard GCN and the curriculum contrastive loss with standard contrastive learning. These changes will allow clearer attribution of gains to the cross-modal alignment and improve assessment of robustness. revision: yes

Circularity Check

0 steps flagged

No circularity: empirical retrieval metrics measured on trained model, not derived by construction

full rationale

The paper describes a data-repair pipeline followed by training of a tri-modal encoder (VLM + port-aware RGCN) under curriculum contrastive loss, then reports measured Recall@1 on held-out retrieval tasks. No equations, uniqueness theorems, or first-principles derivations are invoked whose outputs reduce to the inputs by definition. The central performance numbers are experimental outcomes, not algebraic identities or self-referential fits. Self-citations, if present, are not load-bearing for the reported metrics.

Axiom & Free-Parameter Ledger

0 free parameters · 2 axioms · 0 invented entities

The central claim rests on standard supervised contrastive learning assumptions plus the unverified claim that the repaired Masala-CHAI subset preserves functional semantics. No new physical entities or ad-hoc constants are introduced.

axioms (2)
  • domain assumption Contrastive learning on paired modalities produces semantically meaningful shared embeddings
    Invoked implicitly when the authors map all three modalities into one space and evaluate retrieval performance.
  • ad hoc to paper The two-stage repair pipeline does not change circuit behavior
    Required for the dataset to be treated as high-quality ground truth.

pith-pipeline@v0.9.0 · 5504 in / 1458 out tokens · 47384 ms · 2026-05-08T08:35:36.696051+00:00 · methodology

discussion (0)

Sign in with ORCID, Apple, or X to comment. Anyone can read and Pith papers without signing in.

Reference graph

Works this paper leans on

30 extracted references · 10 canonical work pages · 3 internal anchors

  1. [1]

    Analogcoder: Analog circuit design via training-free code generation,

    Y. Lai, S. Lee, G. Chen, S. Poddar, M. Hu, D. Z. Pan, and P. Luo, “Analogcoder: Analog circuit design via training-free code generation, ”ArXiv, vol. abs/2405.14918, 2024. [Online]. Available: https://api.semanticscholar.org/CorpusID:270045319

    work page arXiv 2024

  2. [2]

    Analogcoder-pro: Unifying analog circuit generation and optimization via multi-modal llms,

    Y. Lai, S. Poddar, S. Lee, G. Chen, M. Hu, B. Yu, P. Luo, and D. Z. Pan, “Analogcoder-pro: Unifying analog circuit generation and optimization via multi-modal llms, ”ArXiv, vol. abs/2508.02518, 2025. [Online]. Available: https://api.semanticscholar.org/CorpusID:280422637

    work page arXiv 2025

  3. [3]

    LaMAGIC: Language-model-based topology gen- eration for analog integrated circuits,

    C.-C. Changet al., “LaMAGIC: Language-model-based topology gen- eration for analog integrated circuits, ” inInternational Conference on Machine Learning (ICML), 2024

    2024

  4. [4]

    Artisan: Automated operational amplifier design via domain-specific large language model,

    Z. Chenet al., “Artisan: Automated operational amplifier design via domain-specific large language model, ” inProceedings of the 61st ACM/IEEE Design Automation Conference (DAC). San Francisco, CA, USA: ACM, Jun. 2024, pp. 1–6

    2024

  5. [5]

    AnalogGenie: A generative engine for automatic discovery of analog circuit topologies,

    J. Gao, W. Cao, J. Yang, and X. Zhang, “AnalogGenie: A generative engine for automatic discovery of analog circuit topologies, ” Feb. 2025

    2025

  6. [6]

    Principle-guided verilog optimization: IP-Safe knowledge transfer via local-cloud collaboration,

    J. Wang, Z. Li, L. Li, F. He, L. Lin, Y. Lai, Y. Li, X. Zeng, and Y. Guo, “Principle-guided verilog optimization: IP-Safe knowledge transfer via local-cloud collaboration, ”arXiv preprint arXiv:2508.05675, 2025

    work page arXiv 2025

  7. [7]

    Image2net: Datasets, benchmark and hybrid framework to convert analog circuit diagrams into netlists,

    H. Xu, C. Liu, Q. Wang, W. Huang, Y. Xu, W. Chen, A. Peng, Z. Li, B. Li, L. Qi, J. Yang, Y. Du, and L. Du, “Image2net: Datasets, benchmark and hybrid framework to convert analog circuit diagrams into netlists, ”2025 International Symposium of Electronics Design Automation (ISEDA), pp. 807–816, 2025. [Online]. Available: https://api.semanticscholar.org/Cor...

    2025

  8. [8]

    arXiv preprint arXiv:2411.14299 (2024)

    J. Bhandari, V. P. V. Bhat, Y. He, S. Garg, H. Rahmani, and R. Karri, “Masala-chai: A large-scale spice netlist dataset for analog circuits by harnessing ai, ”ArXiv, vol. abs/2411.14299, 2024. [Online]. Available: https://api.semanticscholar.org/CorpusID:274166126

    work page arXiv 2024

  9. [9]

    Customized retrieval aug- mented generation and benchmarking for eda tool documentation qa,

    Y. Pu, Z. He, T. Qiu, H. Wu, and B. Yu, “Customized retrieval aug- mented generation and benchmarking for eda tool documentation qa, ” inProceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024, pp. 1–9

    2024

  10. [10]

    The dawn of ai-native eda: Opportuni- ties and challenges of large circuit models,

    L. Chen, Y. Chen, C. Chuet al., “The dawn of ai-native eda: Opportuni- ties and challenges of large circuit models, ”ArXiv, vol. abs/2403.07257, 2024

    work page arXiv 2024

  11. [11]

    Llm4eda: Emerging progress in large language models for electronic design automation,

    R. Zhong, X. Du, S. Kai, Z. Tang, S. Xu, H.-L. Zhen, J. Hao, Q. Xu, M. jie Yuan, and J. Yan, “Llm4eda: Emerging progress in large language models for electronic design automation, ”ArXiv, vol. abs/2401.12224,

    work page arXiv

  12. [12]

    Available: https://api.semanticscholar.org/CorpusID: 267095366

    [Online]. Available: https://api.semanticscholar.org/CorpusID: 267095366

  13. [13]

    Representation Learning with Contrastive Predictive Coding

    A. v. d. Oord, Y. Li, and O. Vinyals, “Representation learning with contrastive predictive coding, ”arXiv preprint arXiv:1807.03748, 2018

    work page internal anchor Pith review arXiv 2018

  14. [14]

    Learning transferable visual models from natural language supervi- sion,

    A. Radford, J. W. Kim, C. Hallacy, A. Ramesh, G. Goh, S. Agarwal, G. Sastry, A. Askell, P. Mishkin, J. Clark, G. Krueger, and I. Sutskever, “Learning transferable visual models from natural language supervi- sion, ” inICML, ser. Proceedings of Machine Learning Research, vol. 139, 2021, pp. 8748–8763

    2021

  15. [15]

    CROP: Circuit retrieval and optimization with parameter guidance using LLMs,

    J. Panet al., “CROP: Circuit retrieval and optimization with parameter guidance using LLMs, ” in2025 IEEE/ACM International Conference on Computer Aided Design (ICCAD). Munich, Germany: IEEE, Oct. 2025, pp. 1–9

    2025

  16. [16]

    Amsnet: Netlist dataset for ams circuits,

    Z. Tao, Y. Shi, Y. Huo, R. Ye, Z. Li, L. Huang, C. Wu, N. Bai, Z. Yu, T.-J. Lin, and L. He, “Amsnet: Netlist dataset for ams circuits, ”2024 IEEE LLM Aided Design Workshop (LAD), pp. 1–5, 2024. [Online]. Available: https://api.semanticscholar.org/CorpusID:269773064

    2024

  17. [17]

    Amsnet 2.0: A large ams database with ai segmentation for net detection,

    Y. Shi, Z. Tao, Y. Gao, L. Huang, H. Wang, Z. Yu, T.-J. Lin, and L. He, “Amsnet 2.0: A large ams database with ai segmentation for net detection, ”2025 IEEE International Conference on LLM- Aided Design (ICLAD), pp. 242–248, 2025. [Online]. Available: https://api.semanticscholar.org/CorpusID:278602633

    2025

  18. [18]

    Functionality matters in netlist representation learning,

    Z. Wang, C. Bai, Z. He, G. Zhang, Q. Xu, T.-Y. Ho, B. Yu, and Y. Huang, “Functionality matters in netlist representation learning, ” inProceed- ings of the 59th ACM/IEEE Design Automation Conference, 2022, pp. 61–66

    2022

  19. [19]

    Netlistify: Transforming circuit schematics into netlists with deep learning

    C.-Y. Huang, H.-I. Chen, H.-W. Ho, P.-H. Kang, M. P.-H. Lin, W.-H. Liu, and H. Ren, “Netlistify: Transforming circuit schematics into netlists with deep learning. ” [Online]. Available: https://api.semanticscholar. org/CorpusID:281826794

  20. [20]

    Analogxpert: Automating analog topology synthesis by incorporating circuit design expertise into large language models,

    H. Zhang, S. Sun, Y. Lin, R. Wang, and J. Bian, “Analogxpert: Automating analog topology synthesis by incorporating circuit design expertise into large language models, ”2025 International Symposium of Electronics Design Automation (ISEDA), pp. 772–777, 2024. [Online]. Available: https://api.semanticscholar.org/CorpusID:275134444

    2025

  21. [21]

    Analogseeker: An open-source foundation language model for analog circuit design,

    Z. Chen, Z. Ji, J. Shen, X. Ke, X. Yang, M. Zhou, Z. Du, X. Yan, Z. Wu, Z. Xu, J. Huang, L. Shang, X. Zeng, and F. Yang, “Analogseeker: An open-source foundation language model for analog circuit design, ”ArXiv, vol. abs/2508.10409, 2025. [Online]. Available: https://api.semanticscholar.org/CorpusID:280650151

    work page arXiv 2025

  22. [22]

    Semi-Supervised Classification with Graph Convolutional Networks

    T. Kipf, “Semi-supervised classification with graph convolutional net- works, ”arXiv preprint arXiv:1609.02907, 2016

    work page internal anchor Pith review arXiv 2016

  23. [23]

    Modeling relational data with graph convolutional net- works,

    M. Schlichtkrull, T. N. Kipf, P. Bloem, R. Van Den Berg, I. Titov, and M. Welling, “Modeling relational data with graph convolutional net- works, ” inEuropean semantic web conference. Springer, 2018, pp. 593–607

    2018

  24. [24]

    An image is worth 16x16 words: Transformers for image recognition at scale,

    A. Dosovitskiy, L. Beyer, A. Kolesnikov, D. Weissenborn, X. Zhai, T. Unterthiner, M. Dehghani, M. Minderer, G. Heigold, S. Gellyet al., “An image is worth 16x16 words: Transformers for image recognition at scale, ” inInternational Conference on Learning Representations

  25. [25]

    Attention is all you need,

    A. Vaswani, N. Shazeer, N. Parmar, J. Uszkoreit, L. Jones, A. N. Gomez, L. Kaiser, and I. Polosukhin, “Attention is all you need, ” inNeurIPS, 2017, pp. 5998–6008

    2017

  26. [26]

    Graphnorm: A principled approach to accelerating graph neural network training,

    T. Cai, S. Luo, K. Xu, D. He, T.-y. Liu, and L. Wang, “Graphnorm: A principled approach to accelerating graph neural network training, ” inInternational Conference on Machine Learning. PMLR, 2021, pp. 1204–1215

    2021

  27. [27]

    Introducing GPT-5.4,

    OpenAI, “Introducing GPT-5.4, ” Mar. 2026, accessed: 2026-04-05. [Online]. Available: https://openai.com/index/introducing-gpt-5-4/

    2026

  28. [28]

    Qwen2 Technical Report

    Q. Team, “Qwen2 technical report, ”ArXiv preprint, vol. abs/2407.10671, 2024

    work page internal anchor Pith review arXiv 2024

  29. [29]

    ChatLS: Multimodal retrieval-augmented generation and chain-of-thought for logic synthesis script customiza- tion,

    H. Zheng, H. Wu, and Z. He, “ChatLS: Multimodal retrieval-augmented generation and chain-of-thought for logic synthesis script customiza- tion, ” in2025 62nd ACM/IEEE Design Automation Conference (DAC). San Francisco, CA, USA: IEEE, Jun. 2025, pp. 1–7

    2025

  30. [30]

    NetTAG: A multimodal rtl-and-layout-aligned netlist foundation model via text- attributed graph,

    W. Fang, W. Li, S. Liu, Y. Lu, H. Zhang, and Z. Xie, “NetTAG: A multimodal rtl-and-layout-aligned netlist foundation model via text- attributed graph, ” Apr. 2025. 10

    2025