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arxiv: 2605.01935 · v1 · submitted 2026-05-03 · 💻 cs.AR · cs.CV· cs.LG

Recognition: 3 theorem links

· Lean Theorem

ViM-Q: Scalable Algorithm-Hardware Co-Design for Vision Mamba Model Inference on FPGA

Patrick S. Y. Hung, Ray C. C. Cheung, Shengzhe Lyu, Weitao Xu, Yuhan She

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Pith reviewed 2026-05-08 19:34 UTC · model grok-4.3

classification 💻 cs.AR cs.CVcs.LG
keywords quantizationmodelsco-designfpgainferencelinearvim-qwhile
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The pith

ViM-Q delivers 4.96x speedup and 59.8x energy efficiency for Vision Mamba inference on FPGA versus a quantized GPU baseline using dynamic activation quantization, per-block APoT weights, and a pipelined SSM engine.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

Vision Mamba models process images using state space models that scale linearly with input size, unlike the quadratic cost of transformers. This efficiency is attractive, but running them on FPGAs for edge devices faces two practical problems: activation values fluctuate sharply and break simple low-bit quantization, and the associative scan operation used in state space models does not map well to the streaming, pipelined dataflow of FPGA hardware. ViM-Q tackles the first problem with a hardware-aware scheme that applies dynamic per-token quantization to activations, adds per-channel smoothing to reduce outlier impact, and uses a 4-bit per-block Additive Power-of-Two format for weights. For the second problem, it builds a runtime-configurable FPGA accelerator containing a linear engine that replaces multiplications with shift-add operations via lookup tables and a fine-grained pipelined SSM engine that parallelizes the state dimension while preserving the required sequential recurrence. The design is parameterizable at runtime so the same hardware can handle different ViM model sizes and input resolutions. When implemented on an AMD ZCU102 FPGA, the system reports an average 4.96 times speedup and 59.8 times better energy efficiency than a quantized NVIDIA RTX 3090 GPU for low-batch inference on the smallest ViM model. The work therefore combines model-level number-format changes with architecture-level streaming optimizations to make these models practical on resource-constrained hardware.

Core claim

Implemented on an AMD ZCU102 FPGA, ViM-Q achieves an average 4.96x speedup and 59.8x energy efficiency gain over a quantized NVIDIA RTX 3090 GPU baseline for low-batch inference on ViM-tiny.

Load-bearing premise

The quantization scheme preserves sufficient model accuracy for the target use cases and the hardware design generalizes across the ViM family without major accuracy or performance loss; the abstract provides no accuracy metrics, ablation studies, or error bars to support this.

Figures

Figures reproduced from arXiv: 2605.01935 by Patrick S. Y. Hung, Ray C. C. Cheung, Shengzhe Lyu, Weitao Xu, Yuhan She.

Figure 1
Figure 1. Figure 1: Architecture of the ViM encoder and the detailed dataflow view at source ↗
Figure 2
Figure 2. Figure 2: Input images and the corresponding input activation distri view at source ↗
Figure 4
Figure 4. Figure 4: Unified linear engine design with LUT pre-computation. Key optimizations include: view at source ↗
Figure 5
Figure 5. Figure 5: Latency breakdown of quantized versus FP16 linear layers view at source ↗
Figure 6
Figure 6. Figure 6: Data access misalignment between the token-major input view at source ↗
Figure 7
Figure 7. Figure 7: Fine-grained pipelined SSM architecture. view at source ↗
Figure 8
Figure 8. Figure 8: Design space exploration of weight bit-widths view at source ↗
Figure 10
Figure 10. Figure 10: Physical floorplan of the implementation on ZCU102 view at source ↗
Figure 11
Figure 11. Figure 11: Normalized throughput and energy efficiency across view at source ↗
read the original abstract

Vision Mamba (ViM) models offer a compelling efficiency advantage over Transformers by leveraging the linear complexity of State Space Models (SSMs), yet efficiently deploying them on FPGAs remains challenging. Linear layers struggle with dynamic activation outliers that render static quantization ineffective, while uniform quantization fails to capture the weight distribution at low bit-widths. Furthermore, while associative scan accelerates SSMs on GPUs, its memory access patterns are misaligned with the streaming dataflow required by FPGAs. To address these challenges, we present ViM-Q, a scalable algorithm-hardware co-design for end-to-end ViM inference on the edge. We introduce a hardware-aware quantization scheme combining dynamic per-token activation quantization and per-channel smoothing to mitigate outliers, alongside a custom 4-bit per-block Additive Power-of-Two (APoT) weight quantization. The models are deployed on a runtime-parameterizable FPGA accelerator featuring a linear engine employing a Lookup-Table (LUT) unit to replace multiplications with shift-add operations, and a fine-grained pipelined SSM engine that parallelizes the state dimension while preserving sequential recurrence. Crucially, the hardware supports runtime configuration, adapting to diverse dimensions and input resolutions across the ViM family. Implemented on an AMD ZCU102 FPGA, ViM-Q achieves an average 4.96x speedup and 59.8x energy efficiency gain over a quantized NVIDIA RTX 3090 GPU baseline for low-batch inference on ViM-tiny. This co-design shows a viable path for deploying ViM models on resource-constrained edge devices.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

This is an applied systems paper; it introduces no free parameters in a derivation, no mathematical axioms, and no new postulated entities such as particles or forces.

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Reference graph

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