arxiv: 2605.02047 · v1 · submitted 2026-05-03 · 💻 cs.AR · cs.ET

Recognition: 2 theorem links

· Lean Theorem

Monolithic 3D Integration for Null Convention Logic (NCL)-Based Asynchronous Circuits

Ashiq Sakib, Kushal Ponugoti, Madhava Vemuri, Xiameng Zhang

Authors on Pith no claims yet

Pith reviewed 2026-05-08 18:55 UTC · model grok-4.3

classification 💻 cs.AR cs.ET

keywords monolithic 3D integrationnull convention logicasynchronous circuitsquasi-delay-insensitivearea reductionstandard cellsarray multiplierlow-power design

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The pith

Monolithic 3D integration applied to Null Convention Logic reduces area by 44 percent while also lowering delay and power.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper develops a methodology for building standard cells of Null Convention Logic circuits using monolithic 3D stacking to address the excessive area that has hindered adoption of quasi-delay-insensitive asynchronous designs. The authors apply this method to create an unsigned array multiplier and run simulations that compare it against conventional planar versions. Under a conservative assumption of wirelength reduction from vertical integration, the 3D version delivers 44 percent smaller area along with 31 percent lower delay and 17 percent lower power. A sympathetic reader would care because this directly tackles the main practical barrier to using asynchronous circuits in high-speed, low-power electronics.

Core claim

Stacking NCL threshold gates across monolithic 3D layers produces an unsigned array multiplier whose simulated area is 44 percent smaller than its 2D counterpart, with corresponding reductions in delay of 31 percent and power of 17 percent, when only a conservative wirelength benefit is credited to the vertical integration.

What carries the argument

The M3D-NCL standard-cell design methodology that places threshold gates in vertically stacked layers to shorten interconnects while retaining the quasi-delay-insensitive behavior of NCL.

If this is right

NCL-based asynchronous circuits become viable for area-constrained applications once their footprint is reduced by nearly half.
The same stacking approach can be applied to other quasi-delay-insensitive asynchronous blocks beyond multipliers.
Power and speed advantages of asynchronous designs become more attainable when area overhead is mitigated by vertical integration.
Standard-cell libraries for NCL can be extended to M3D processes without altering the fundamental threshold-gate logic.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

Widespread use of this method would require new place-and-route tools that account for vertical vias and layer-specific parasitics in asynchronous timing analysis.
The area savings could make NCL attractive for battery-powered or thermally limited devices where clock distribution costs are high.
Testing the approach on larger circuits such as processors or filters would reveal whether the reported gains scale beyond the multiplier example.

Load-bearing premise

That monolithic 3D stacking yields a net wirelength reduction without adding parasitic effects, thermal gradients, or manufacturing defects large enough to erase the reported area, delay, and power improvements.

What would settle it

A physical prototype of the M3D-NCL multiplier fabricated in an actual monolithic 3D process whose measured area, delay, and power are compared against the simulation results that assumed only conservative wirelength savings.

Figures

Figures reproduced from arXiv: 2605.02047 by Ashiq Sakib, Kushal Ponugoti, Madhava Vemuri, Xiameng Zhang.

**Figure 1.** Figure 1: (b). The NCL logic, including registers and completion, comprises 27 fundamental gates with hysteresis, i.e., state holding capability. Each gate is characterized by unique input configurations and threshold levels. Together, these gates can implement any function of up to 4 variables. The threshold gates are classified into two categories: non-weighted and weighted. A non-weighted gate, also known as an… view at source ↗

**Figure 3.** Figure 3: 2D and proposed M3D process comparison (not to scale) the length of the channel region to be 50 nm, and the length and width of the source and drain regions to be 90 nm. The width and pitch of the interconnect wires are 65 nm and 130 nm, respectively. We have considered the copper connecting region to have a sheet resistance of 0.38Ω/sq and a capacitance per unit length of 179.93 fF/mm, based on [33], [37]… view at source ↗

**Figure 5.** Figure 5: Power and delay improvements of M3D over 2D view at source ↗

**Figure 6.** Figure 6: (%) Improvement of M3D implementation over 2D view at source ↗

read the original abstract

As the demand for high-speed and low-power electronics continues to grow, the quasi-delay-insensitive (QDI) asynchronous domain of digital design has emerged as a promising alternative to traditional clock-based designs. However, the adoption of the paradigm has been greatly limited due to the lack of mature computer-aided design (CAD) tools and a substantially larger area footprint, owing to various architectural constraints. Monolithic-3D (M3D) technology has recently paved the way for manufacturing highly dense integrated circuits (ICs) through sequential integration, resulting in a reduced area footprint, shorter wirelengths, and increased performance. In this study, we integrate M3D technology with QDI Null Convention Logic (NCL) and propose a design methodology for the implementation of M3D-based NCL standard cells, aimed at mitigating the area inefficiencies of traditional planar or 2D counterparts. Furthermore, we employed the threshold gates to design an M3D-NCL unsigned array multiplier circuit. Simulation results suggest that, for a conservative wirelength reduction resulting from M3D implementation, a substantial area reduction of 44% can be achieved while simultaneously reducing delay and power by approximately 31% and 17%, respectively.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Desk Editor's Note private letter to a colleague

The paper applies M3D to NCL circuits and reports area/delay/power gains in simulation, but those numbers rest on an unquantified wirelength reduction without parasitic or thermal modeling.

read the letter

This paper shows how monolithic 3D integration can shrink the area overhead of Null Convention Logic by stacking standard cells and shortening wires. For an unsigned array multiplier they get 44% area savings, 31% delay cut, and 17% power drop under what they call a conservative wirelength reduction from the 3D layout. That is the core new result: a concrete design flow for M3D NCL cells plus one worked example with numbers attached to it. The approach is straightforward and directly addresses the known footprint problem in QDI designs, which is useful for anyone trying to make asynchronous logic more practical in low-power chips. The methodology for building the threshold-gate cells in 3D is the part that feels like actual engineering progress rather than just another simulation study. The soft spot is the simulation foundation. The gains are tied to a fixed wirelength reduction that is labeled conservative but never derived from NCL-specific placement or routing constraints. The abstract and description give no detail on how monolithic vias, inter-tier capacitance, or thermal gradients would change the dual-rail timing and power numbers. Without those effects modeled, the reported percentages could shrink or disappear once real extraction is done. The work is aimed at computer architects and CAD researchers who already care about asynchronous circuits and 3D stacking. It is not a foundational paper, but it supplies a specific data point that others can build on or challenge. I would send it to peer review. The idea is clear, the example is relevant, and referees can push for the missing methodology details without starting from zero.

Referee Report

2 major / 1 minor

Summary. The manuscript proposes a design methodology for Monolithic 3D (M3D) integration of Null Convention Logic (NCL) standard cells to reduce the area footprint of quasi-delay-insensitive asynchronous circuits. It demonstrates the approach on an unsigned array multiplier and reports simulation results of 44% area reduction, 31% delay reduction, and 17% power reduction under a conservative wirelength reduction assumption arising from M3D stacking.

Significance. If the quantitative claims can be substantiated with explicit M3D parasitic and thermal models, the work would offer a concrete path to mitigating the well-known area penalty of NCL/QDI designs while preserving their timing robustness, which could accelerate adoption in low-power, high-reliability domains. The cell-level methodology itself constitutes a targeted, reusable contribution at the intersection of asynchronous logic and sequential 3D integration.

major comments (2)

[Abstract / Simulation Results] Abstract and Simulation Results section: the reported 44% area, 31% delay, and 17% power improvements rest on an unquantified 'conservative wirelength reduction' that is neither derived from NCL threshold-gate placement rules nor from measured 2D routing statistics; without the exact factor or its justification, the numerical claims cannot be independently reproduced or stress-tested.
[Methodology / Simulation Setup] Methodology and Simulation Setup: the evaluation omits monolithic via series resistance, inter-tier coupling capacitance, and vertical thermal gradients. Because NCL employs dual-rail signaling and threshold gates whose delay is sensitive to interconnect parasitics, these omitted effects constitute a load-bearing modeling gap that could materially alter the claimed gains.

minor comments (1)

[Abstract] The abstract refers to 'various architectural constraints' limiting NCL adoption without enumerating them; a short parenthetical list would improve accessibility for readers outside the asynchronous-design community.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive and detailed comments. We have revised the manuscript to address the concerns regarding quantification of assumptions and explicit discussion of modeling limitations. Point-by-point responses follow.

read point-by-point responses

Referee: [Abstract / Simulation Results] Abstract and Simulation Results section: the reported 44% area, 31% delay, and 17% power improvements rest on an unquantified 'conservative wirelength reduction' that is neither derived from NCL threshold-gate placement rules nor from measured 2D routing statistics; without the exact factor or its justification, the numerical claims cannot be independently reproduced or stress-tested.

Authors: We agree that the wirelength reduction factor must be quantified for reproducibility. The revised manuscript now explicitly states in the abstract and Simulation Results section that a conservative 25% average wirelength reduction is assumed. This value is justified as a pessimistic estimate drawn from typical M3D wirelength improvements reported in the literature for comparable logic blocks (often 30-50%), adjusted downward to account for NCL-specific dual-rail routing overhead without claiming direct derivation from our own 2D placement statistics. A short explanatory sentence has been added to the methodology to clarify the basis of the assumption. revision: yes
Referee: [Methodology / Simulation Setup] Methodology and Simulation Setup: the evaluation omits monolithic via series resistance, inter-tier coupling capacitance, and vertical thermal gradients. Because NCL employs dual-rail signaling and threshold gates whose delay is sensitive to interconnect parasitics, these omitted effects constitute a load-bearing modeling gap that could materially alter the claimed gains.

Authors: We concur that these parasitic and thermal effects are important and were not modeled. The revised Simulation Setup section now explicitly lists the omissions (via resistance, inter-tier coupling, and thermal gradients) as study limitations. We note that the conservative wirelength reduction was selected in part to provide margin against unmodeled parasitic penalties. Full extraction of these effects would require a complete M3D process design kit and thermal simulation infrastructure that was unavailable for the 45 nm node used here. The paper now includes a forward-looking statement on incorporating such models in follow-on work. revision: partial

Circularity Check

0 steps flagged

No significant circularity detected

full rationale

The paper's central claims rest on simulation outcomes conditioned on an explicitly stated external input ('conservative wirelength reduction resulting from M3D implementation'). This assumption is presented as a modeling choice rather than derived from the NCL threshold-gate equations or prior results within the paper. No self-definitional loops, fitted parameters renamed as predictions, or load-bearing self-citations appear in the abstract or described methodology. The reported area/delay/power figures are therefore outputs of the simulation under the given input and do not reduce to the input by construction.

Axiom & Free-Parameter Ledger

1 free parameters · 1 axioms · 0 invented entities

The central claim rests on the domain assumption that M3D provides net wirelength and density benefits when applied to NCL cells, plus an unquantified simulation parameter for wirelength reduction. No new physical entities are postulated.

free parameters (1)

conservative wirelength reduction
The 44/31/17 percent gains are conditioned on this assumption whose exact numerical value is not stated or derived in the abstract.

axioms (1)

domain assumption Monolithic 3D integration reduces effective wirelength and area footprint relative to planar 2D layouts for the same logic function
Invoked as the basis for all reported area, delay, and power improvements.

pith-pipeline@v0.9.0 · 5527 in / 1433 out tokens · 32025 ms · 2026-05-08T18:55:42.748367+00:00 · methodology

discussion (0)

Reference graph

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