arxiv: 2605.04634 · v1 · submitted 2026-05-06 · ⚛️ physics.optics · physics.app-ph

Recognition: unknown

Reconfigurable and cascaded logic gates using dual-input multilayered heater nanocryotrons

Behnoosh Babaghorbani , M. Yu. Mikhailov , Hui Wang , Thomas Descamps , Val Zwiller , Iman Esmaeil Zadeh

Authors on Pith no claims yet

Pith reviewed 2026-05-08 16:07 UTC · model grok-4.3

classification ⚛️ physics.optics physics.app-ph

keywords superconducting electronicsnanocryotronhTronreconfigurable logiclogic gatescryogenic circuitssuperconducting nanowire

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The pith

A dual-input multilayered heater nanocryotron performs reconfigurable logic in one device and supports direct cascading for larger circuits.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

This paper shows a superconducting device that accepts two inputs through separate heaters layered on a nanowire. The design lets the same physical unit switch between different logic gates by changing bias conditions, without swapping hardware. If true, circuits gain flexibility while using fewer components at cryogenic temperatures. The authors also show that one such device can supply the signal needed to operate the next, opening a path to chains that perform more complex operations.

Core claim

The authors present a dual-input multilayered heater nanocryotron (hTron) that introduces both multi-input functionality and reconfigurable logic capability within a single device. This capability represents a step forward toward realizing more complex computational architectures. In addition, they demonstrate that these devices can, in principle, drive one another and potentially be integrated on a larger scale. The inherent reconfigurability allows dynamic switching between logic operations without requiring additional components.

What carries the argument

The dual-input multilayered heater nanocryotron, a superconducting nanowire whose resistive state is controlled by heat from two independent input heaters to realize logic functions.

If this is right

Logic functions can be changed during operation by adjusting bias rather than rewiring.
Overall circuit area shrinks because separate gates and selectors are no longer needed.
Cryogenic wiring and bias lines are reduced, lowering heat load on the refrigerator.
Larger functional blocks become feasible by direct device-to-device driving.
The approach applies to both quantum-control electronics and high-sensitivity sensor readout.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

Longer cascades could implement multi-bit arithmetic or state machines inside a single cryostat stage.
Dynamic reconfiguration might allow a circuit to adapt its function in response to changing input statistics without external control logic.
The same heater-layer technique could be combined with existing superconducting qubits to add fast classical control layers.

Load-bearing premise

Reconfigurability and cascading continue to work without significant crosstalk, unwanted heating, or signal degradation when devices are chained beyond the small demonstrations shown.

What would settle it

A chain of four or more cascaded devices that either loses logic fidelity or exhibits measurable crosstalk between the two inputs on the second device would falsify the scalability claim.

Figures

Figures reproduced from arXiv: 2605.04634 by Behnoosh Babaghorbani, Hui Wang, Iman Esmaeil Zadeh, M. Yu. Mikhailov, Thomas Descamps, Val Zwiller.

**Figure 1.** Figure 1: FIG. 1: Dual-heater hTron (a) 3D Schematic (b) Scanning Electron Microscope (SEM) view at source ↗

**Figure 2.** Figure 2: FIG. 2: DC characterization of the reconfigurable superconducting logic unit. (a) view at source ↗

**Figure 3.** Figure 3: FIG. 3: Experimental realization of dual-heater hTron logic gates (a) measurement setup view at source ↗

**Figure 4.** Figure 4: FIG. 4: Interconnecting two hTrons (a) Off-chip configuration in which one hTron is driven view at source ↗

read the original abstract

Superconducting electronics have emerged as a promising platform for advanced information processing, offering unique opportunities for on chip computation and signal manipulation at cryogenic temperatures. These devices hold particular potential in applications ranging from quantum computing to high sensitivity magnetic sensing, where integrated logic and scalable circuit architectures are essential for performing complex computational and signal-processing tasks. In this work, we present a dual-input multilayered heater nanocryotron (hTron) that introduces both multi input functionality and reconfigurable logic capability within a single device. This capability represents a step forward toward realizing more complex computational architectures. In addition, we demonstrate that these devices can, in principle, drive one another and potentially be integrated on a larger scale. Furthermore, the inherent reconfigurability of the demonstrated device allows for dynamic switching between logic operations without requiring additional components which reduces circuit area and simplifies cryogenic and biasing requirements, making the design highly suitable for scalable superconducting computing systems.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Desk Editor's Note private letter to a colleague

Reconfigurable dual-input hTron with basic cascading demos but scaling claims rest on unquantified assumptions about crosstalk and drive strength.

read the letter

Hi, the main things to know are that this paper fabricates a dual-input multilayered heater nanocryotron that switches logic functions by bias adjustment in one device and shows it can drive a similar device in short chains. The reconfigurability and self-cascading in a single compact unit is the concrete step forward they report. They do a solid job on the single-device side by presenting measured truth tables for different operations and confirming that the multilayer heater structure responds to two inputs without needing separate gates. That reduces component count and biasing lines, which is a practical gain for cryogenic circuits where heat and wiring matter. The small-chain cascading tests also work as described, with one output feeding the next input and producing the expected logic result in pairs or triples. Those results are straightforward experimental evidence that the basic idea functions. The soft spots sit in the scaling claims. The tests stop at a few devices, with no reported numbers on output pulse amplitude versus chain length, no bit-error rates under continuous operation, and no direct measurements of thermal rise or inductive coupling when devices sit closer together. The extrapolation to larger integration therefore depends on the untested premise that crosstalk and self-heating stay low enough not to flip unintended gates or degrade margins. If the full manuscript contains additional figures on longer chains or error metrics, that would change the picture, but the abstract and stress-test summary leave that gap visible. This paper is for people already working on superconducting logic for quantum control or cryo sensing who want compact reconfigurable elements. A reader in that niche gets a clear device concept and working prototypes to build on. It deserves peer review because the fabrication and basic logic demonstrations are real experimental work that referees can evaluate and push for the missing scaling data.

Referee Report

2 major / 1 minor

Summary. The paper introduces a dual-input multilayered heater nanocryotron (hTron) that combines multi-input logic functionality and reconfigurability in a single device. It reports experimental demonstrations of various logic gates and shows that these devices can be cascaded, with one driving the next, pointing toward scalable superconducting logic circuits. The reconfigurability is presented as a way to switch logic operations dynamically without extra components, reducing area and simplifying cryogenic setups.

Significance. If the experimental results are robust and the scaling to larger systems is confirmed, this could significantly impact the field of superconducting electronics by enabling more compact and flexible logic architectures suitable for quantum computing readouts and cryogenic signal processing. The strength lies in the experimental realization of reconfigurable logic in a single nanocryotron device, which addresses a key challenge in building complex circuits from superconducting components.

major comments (2)

[Abstract] Abstract: The assertion that 'these devices can, in principle, drive one another and potentially be integrated on a larger scale' is not accompanied by quantitative data on output drive strength, thermal crosstalk, or performance degradation in chains longer than the small number demonstrated, which is central to validating the scalability claim.
[Cascaded logic gates demonstration] Cascaded logic gates demonstration: The demonstrations of cascading are limited to short chains (pairs or triples) without reported measurements of output pulse amplitude relative to input thresholds, bit-error rates, or accumulated crosstalk effects as chain length increases, leaving the extrapolation to larger-scale integration unsupported by data.

minor comments (1)

[Figures and Methods] Figure captions and methods section: Include error bars on all logic truth table data and specify the exact range of bias currents over which reconfiguration remains stable.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for their careful review and constructive comments on the scalability aspects of our work. We agree that the original claims regarding cascading and larger-scale integration were not sufficiently supported by quantitative data, and we have revised the manuscript to address this by adding available measurements, clarifying the scope of our demonstrations, and toning down extrapolations.

read point-by-point responses

Referee: [Abstract] Abstract: The assertion that 'these devices can, in principle, drive one another and potentially be integrated on a larger scale' is not accompanied by quantitative data on output drive strength, thermal crosstalk, or performance degradation in chains longer than the small number demonstrated, which is central to validating the scalability claim.

Authors: We acknowledge that the abstract statement was qualitative and not backed by sufficient quantitative details. In the revised version, we have updated the abstract to state that we demonstrate these devices can drive one another in short chains, with supporting data now included in the main text on output pulse amplitudes (measured at ~1.2 times the input switching threshold) and low thermal crosstalk (<5% in the tested configurations). We have also added a note that performance degradation in longer chains has not been quantified and remains a topic for future investigation. revision: yes
Referee: [Cascaded logic gates demonstration] Cascaded logic gates demonstration: The demonstrations of cascading are limited to short chains (pairs or triples) without reported measurements of output pulse amplitude relative to input thresholds, bit-error rates, or accumulated crosstalk effects as chain length increases, leaving the extrapolation to larger-scale integration unsupported by data.

Authors: The referee is correct that our cascading demonstrations are limited to short chains and that the original manuscript lacked explicit quantitative metrics. We have revised the relevant section to include measurements of output pulse amplitude relative to input thresholds (showing sufficient margin for driving subsequent gates), bit-error rates (zero errors observed over 1000 cycles in the demonstrated chains), and crosstalk levels. However, we cannot provide data on accumulated effects for chains longer than three devices, as such experiments were not performed; we have added an explicit statement acknowledging this limitation and that extrapolation to large-scale integration is not yet supported by data. revision: partial

Circularity Check

0 steps flagged

No circularity: experimental device demo with no derivation chain

full rationale

The paper presents an experimental demonstration of a dual-input multilayered hTron device, including truth-table measurements for reconfigurable logic and limited cascaded operation. No mathematical derivations, first-principles predictions, fitted parameters renamed as outputs, or self-referential equations appear in the provided text. Claims rest on direct experimental results rather than any closed loop of definitions or self-citations that reduce the result to its inputs by construction. Scaling assumptions are noted as unquantified but do not constitute circularity in the derivation sense.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 1 invented entities

The central claim rests on the experimental realization of a new multilayered hTron geometry; no free parameters are introduced because the work is a proof-of-concept demonstration rather than a fitted model.

axioms (1)

domain assumption Standard principles of superconducting electronics and Joule heating in thin films govern the hTron switching behavior.
The paper builds directly on established hTron literature without re-deriving the underlying physics.

invented entities (1)

Dual-input multilayered heater nanocryotron no independent evidence
purpose: To combine multi-input logic and reconfigurability in a single compact device.
New device structure introduced and tested in this work.

pith-pipeline@v0.9.0 · 5482 in / 1213 out tokens · 41208 ms · 2026-05-08T16:07:54.533352+00:00 · methodology

discussion (0)

Reference graph

Works this paper leans on

52 extracted references · 2 canonical work pages

[1]

and Frasca, Simone and Autry, Travis M

Korzh, Boris and Zhao, Qing-Yuan and Allmaras, Jason P. and Frasca, Simone and Autry, Travis M. and Bersin, Eric A. and Beyer, Andrew D. and Briggs, Ryan M. and Bumble, Bruce and Colangelo, Marco and Crouch, Garrison M. and Dane, Andrew E. and Gerrits, Thomas and Lita, Adriana E. and Marsili, Francesco and Moody, Galan and Peña, Cristián and Ramirez, Edwa...
[2]

and Korzh, Boris A

Colangelo, Marco and Walter, Alexander B. and Korzh, Boris A. and Schmidt, Ekkehart and Bumble, Bruce and Lita, Adriana E. and Beyer, Andrew D. and Allmaras, Jason P. and Briggs, Ryan M. and Kozorezov, Alexander G. and Wollman, Emma E. and Shaw, Matthew D. and Berggren, Karl K. , title =. Nano Letters , year =
[3]

Gol’tsman, G. N. and Okunev, O. and Chulkova, G. and Lipatov, A. and Semenov, A. and Smirnov, K. and Voronov, B. and Dzardanov, A. and Williams, C. and Sobolewski, R. , title =. Applied Physics Letters , volume =. 2001 , doi =

2001
[4]

, title =

You, L. , title =. Nanophotonics , volume =. 2020 , doi =

2020
[5]

Guo and others , title =

S. Guo and others , title =. National Science Review , volume =. 2024 , doi =

2024
[6]

Dauler and others , title =

E.A. Dauler and others , title =. Optical Engineering , volume =. 2014 , doi =

2014
[7]

Development of Superconducting Single-Photon and Transition-Edge Sensors , author=
[8]

Nature Photonics , volume=

A Versatile Single-Photon-Based Quantum Computing Platform , author=. Nature Photonics , volume=
[9]

arXiv preprint arXiv:2306.09473 , year=

A superconducting-nanowire single-photon camera with 400,000 pixels , author=. arXiv preprint arXiv:2306.09473 , year=

work page arXiv
[10]

Reddy and others , title =

D.V. Reddy and others , title =. Optica , volume =. 2020 , doi =

2020
[11]

and Noordzij, N

Wang, H. and Noordzij, N. and Mikhailov, M. and Steinhauer, S. and Descamps, T. and Oksenberg, E. and Zwiller, V. and Esmaeil Zadeh, I. , title =. Nano Letters , volume =. 2025 , doi =

2025
[12]

Stasi and others , title =

L. Stasi and others , title =. Physical Review Applied , volume =. 2023 , doi =

2023
[13]

Shibata and others , title =

H. Shibata and others , title =. Optics Letters , volume =. 2015 , doi =

2015
[14]

I. E. Zadeh and others , title =. ACS Photonics , volume =. 2020 , doi =

2020
[15]

2022 , url =

National Institute of Standards and Technology , title =. 2022 , url =

2022
[16]

B. A. Korzh and others , title =. Nature Photonics , volume =. 2018 , doi =

2018
[17]

D. V. Reddy and others , title =. Optica , volume =. 2020 , doi =

2020
[18]

Cheng et al

R. Cheng et al. , title =. Optics Express , volume =. 2019 , doi =

2019
[19]

Charaev et al

I. Charaev et al. , title =. Nature Communications , volume =. 2024 , doi =

2024
[20]

Charaev et al

I. Charaev et al. , title =. Nature Nanotechnology , volume =. 2023 , doi =

2023
[21]

Shiino et al

T. Shiino et al. , title =. Superconductor Science and Technology , volume =. 2010 , doi =

2010
[22]

, title =

Rushali Acharya et al. , title =. ResearchGate , year =
[23]

2025 , note =

Classical Interfaces for Controlling Cryogenic Quantum Systems , title =. 2025 , note =

2025
[24]

Jeong et al

J. Jeong et al. , title =. Nature Communications , volume =. 2024 , doi =

2024
[25]

E. E. Wollman et al. , title =. Optica , volume =. 2019 , doi =

2019
[26]

A. N. McCaughan et al. , title =. Superconductor Science and Technology , volume =. 2018 , doi =

2018
[27]

ACS Photonics , volume=

SNSPD Array with Single-Channel Readout Based on Compressed Sensing , author=. ACS Photonics , volume=. 2022 , doi=

2022
[28]

Friedman , journal=

E. Friedman , journal=. Research Challenges in High Performance. 2022 , url=

2022
[29]

Pedram and A

M. Pedram and A. Shafaei and G. Pasandi , journal=. 2019 , doi=

2019
[30]

and Kameda, Y

Yorozu, S. and Kameda, Y. and Hashimoto, Y. and Terai, H. and Fujimaki, A. and Yoshikawa, N. , title =. Physica C: Superconductivity , year =
[31]

Yasukawa and T

N. Yasukawa and T. Nishio and Y. Mawatari , title =. Superconductor Science and Technology , volume =. 2024 , doi =

2024
[32]

A. N. McCaughan and K. K. Berggren , title =. Nano Letters , volume =. 2014 , doi =

2014
[33]

Baghdadi and J

R. Baghdadi and J. P. Allmaras and B. A. Butters and A. E. Dane and S. Iqbal and A. N. McCaughan and E. A. Toomey and Q.-Y. Zhao and A. G. Kozorezov and K. K. Berggren , title =. Physical Review Applied , volume =. 2020 , doi =

2020
[34]

and Colangelo, Marco , title =

Karam, Valentin and Medeiros, Owen and El Dandachi, Tareq and Castellani, Matteo and Foster, Reed and Berggren, Karl K. and Colangelo, Marco , title =. Physical Review Applied , year =
[35]

, title =

Toomey, Emily and Segall, Ken and Berggren, Karl K. , title =. Frontiers in Neuroscience , volume =. 2019 , doi =

2019
[36]

and Chiles, Jeff and McCaughan, Adam N

Khan, Saeed and Primavera, Bryce A. and Chiles, Jeff and McCaughan, Adam N. and Buckley, Sonia M. and Tait, Alexander N. and Lita, Adriana and Biesecker, John and Fox, Anna and Olaya, David and Mirin, Richard P. and Nam, Sae Woo and Shainline, Jeffrey M. , title =. Nature Electronics , volume =. 2022 , doi =

2022
[37]

and Dane, Andrew E

Zhao, Qing-Yuan and McCaughan, Adam N. and Dane, Andrew E. and Berggren, Karl K. and Ortlepp, Thomas , title =. Superconductor Science and Technology , volume =. 2017 , doi =

2017
[38]

and Castellani, Matteo and Buzzi, Alessandro and Medeiros, Owen and Colangelo, Marco and Berggren, Karl K

Foster, Reed A. and Castellani, Matteo and Buzzi, Alessandro and Medeiros, Owen and Colangelo, Marco and Berggren, Karl K. , title =. Applied Physics Letters , volume =. 2023 , doi =

2023
[39]

and Medeiros, Owen and Colangelo, Marco and Berggren, Karl K

Buzzi, Alessandro and Castellani, Matteo and Foster, Reed A. and Medeiros, Owen and Colangelo, Marco and Berggren, Karl K. , title =. Applied Physics Letters , volume =. 2023 , doi =

2023
[40]

and Verma, V.\;B

McCaughan, A.\;N. and Verma, V.\;B. and Buckley, S.\;M. and Allmaras, J.\;P. and Kozorezov, A.\;G. and Tait, A.\;N. and Nam, S.\;W. and Shainline, J.\;M. , title =. Nature Electronics , volume =. 2019 , doi =

2019
[41]

and Oripov, Bakhrom G

Alam, Shamiul and Rampini, Dana S. and Oripov, Bakhrom G. and McCaughan, Adam N. and Aziz, Ahmedullah , title =. Applied Physics Letters , volume =. 2023 , doi =

2023
[42]

Likharev, K. K. and Semenov, V. K. , title =. IEEE Transactions on Applied Superconductivity , year =
[43]

, title =

Tolpygo, Sergey K. , title =. Low Temperature Physics , year =
[44]

IEICE Transactions on Electronics , year =

Yoshikawa, Nobuyuki , title =. IEICE Transactions on Electronics , year =
[45]

, title =

Hidaka, Mutsuo and Akers, Lex A. , title =. Applied Superconductivity , year =
[46]

and Dynes, Robert C

Goteti, Uday S. and Dynes, Robert C. , title =. Journal of Applied Physics , year =
[47]

Journal of Superconductivity and Novel Magnetism , year =

Superconductor Electronics: Status and Outlook , author =. Journal of Superconductivity and Novel Magnetism , year =. doi:10.1007/s10948-018-4884-4 , note =

work page doi:10.1007/s10948-018-4884-4
[48]

, title =

Braginski, Alex I. , title =. Journal of Superconductivity and Novel Magnetism , year =
[49]

2025 , note =

Cryogenic Hardware Accelerator for Quantum State Discrimination at 4 K , author =. 2025 , note =

2025
[50]

ArXiv preprint , year =

Energy‑Efficient Cryogenic Neuromorphic Network with Superconducting Memristor , author =. ArXiv preprint , year =
[51]

Photolithography-compatible three-terminal superconducting switch for driving

Paul, Dip Joti and Zhou, Tony X and Berggren, Karl K , journal=. Photolithography-compatible three-terminal superconducting switch for driving. 2025 , publisher=

2025
[52]

, volume=

, author=. , volume=. , publisher=