arxiv: 2605.11248 · v1 · submitted 2026-05-11 · 💻 cs.SE · cs.SY· eess.SY

Recognition: no theorem link

SHIA: A Direct SysML-Hardware Interface Architecture for Model-Centric Verification

Amal Elsokary, Charles Lewis, Siyuan Ji

Authors on Pith no claims yet

Pith reviewed 2026-05-13 01:34 UTC · model grok-4.3

classification 💻 cs.SE cs.SYeess.SY

keywords SysMLhardware verificationmodel-based systems engineeringdirect interfacebidirectional communicationdigital threadlogic gate

0 comments

The pith

SysML models can directly stimulate, observe, and verify physical hardware behavior through a bidirectional server link without any model transformations.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper introduces SHIA to keep an executable SysML model inside the hardware verification process by exchanging messages directly with physical systems. This setup uses a server written in embedded C++ on the SysML side and a corresponding server on hardware, eliminating intermediate transformations, co-simulations, or plugins that usually cause the model to drift from the implementation. A logic gate case study shows correct bidirectional messaging and identical outputs when compared via Karnaugh maps. A sympathetic reader would care because the original system model remains the active reference for stimulating and checking hardware rather than becoming a static document passed to other tools. The result points to a shorter path from architecture to verified hardware.

Core claim

SHIA realizes a direct bidirectional connection between an executable SysML model in IBM Rhapsody and physical hardware via a SysML-side server and a Raspberry Pi-based hardware server. In the end-to-end logic gate demonstration, the integrated system exchanged messages correctly in both directions with zero discrepancy between SysML-generated and hardware-generated outputs.

What carries the argument

The SysML Hardware Interface Architecture (SHIA), a pair of servers that establish bidirectional message exchange between the executable SysML model and hardware without transformation chains.

If this is right

Hardware verification can be driven directly by the executable system model rather than by derived simulations.
The system model remains the authoritative reference for both structure and observed behavior throughout testing.
Verification of individual components and full integration can occur while the model stays in the loop.
The digital thread from architecture to hardware realization shortens by removing transformation steps.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

The approach could be tested on systems larger than a single logic gate to check whether the interface scales without added synchronization overhead.
Similar direct links might apply to other executable modeling languages if their tool environments support embedded server code.
Adoption would reduce reliance on separate co-simulation platforms for MBSE hardware projects.

Load-bearing premise

A direct server-based interface can be maintained reliably across different hardware platforms and SysML tools without introducing synchronization errors or custom protocol problems.

What would settle it

A discrepancy appearing in output comparison or a failed message exchange when the same interface is applied to a multi-component system on different hardware would show the direct link does not hold.

Figures

Figures reproduced from arXiv: 2605.11248 by Amal Elsokary, Charles Lewis, Siyuan Ji.

**Figure 2.** Figure 2: SysML-integrated HiL workflow in which the SysML model [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗

**Figure 3.** Figure 3: (a & b) M2T vs. M2M transformation approaches [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗

**Figure 4.** Figure 4: (a) General considerations required for model transforma [PITH_FULL_IMAGE:figures/full_fig_p004_4.png] view at source ↗

**Figure 5.** Figure 5: Development and verification stages of the proposed SHIA workflow. (a) shows SysML modelling, (b) hardware assembly, (c) SHIA [PITH_FULL_IMAGE:figures/full_fig_p006_5.png] view at source ↗

**Figure 6.** Figure 6: SHIA architecture showing the SysML server, serial com [PITH_FULL_IMAGE:figures/full_fig_p007_6.png] view at source ↗

**Figure 7.** Figure 7: Excutable stateChart of NAND block The upper region determines the current output state of the gate, represented by OutputLow and OutputHigh, while the lower region monitors incoming signal events on the input ports and updates the internal input-state variables accordingly. Based on these stored input values, guarded transitions in the upper region evaluate the NAND condition and activate the appropriate … view at source ↗

**Figure 8.** Figure 8: IBD diagram of the intended HW prototype with 5 input pins and 5 output pins in red box, and a corresponding test harness in green box [PITH_FULL_IMAGE:figures/full_fig_p009_8.png] view at source ↗

**Figure 9.** Figure 9: (User interface panel diagram for applying stimuli to and testing the hardware model [PITH_FULL_IMAGE:figures/full_fig_p010_9.png] view at source ↗

**Figure 10.** Figure 10: SysML Hardware Model Truth Table and its converting to [PITH_FULL_IMAGE:figures/full_fig_p010_10.png] view at source ↗

**Figure 11.** Figure 11: Isolated Hardware Testing Setup The recorded results from the physical hardware testing were manually checked by the operator to confirm that the assembled physical chassis was functioning as expected, 3.4.2. 5.3. SHIA Servers Development As discussed previously, the SHIA mechanism is divided into two servers. The first is the SysML server, which refers to the C++ implementation associated with the SysM… view at source ↗

**Figure 12.** Figure 12: SHIA Hardware Server Implementation 5.4.2. SHIA SysML Preparation To prepare for SHIA server verification, the behavioural workflow was governed directly within the SysML environment. This demonstrates SysML functioning as the single source of truth, as the operational logic of the interface was defined and controlled by the SysML model itself. Accordingly, the model served not only as a representation… view at source ↗

**Figure 13.** Figure 13: Test Harness behavioural response to operator inputs, showing the concurrent states [PITH_FULL_IMAGE:figures/full_fig_p012_13.png] view at source ↗

**Figure 14.** Figure 14: SHIA SysML Server Model Interface Transmit State [PITH_FULL_IMAGE:figures/full_fig_p013_14.png] view at source ↗

**Figure 15.** Figure 15: Screenshot of the Hardware Server in operation on the Raspberry Pi [PITH_FULL_IMAGE:figures/full_fig_p014_15.png] view at source ↗

**Figure 16.** Figure 16: (a) System Verification Method and (b) Karnaugh comparison map showing verification of full SHIA system [PITH_FULL_IMAGE:figures/full_fig_p014_16.png] view at source ↗

**Figure 17.** Figure 17: SHIA mechanism as a direct real time interface between virtual and physical counterparts [PITH_FULL_IMAGE:figures/full_fig_p015_17.png] view at source ↗

**Figure 18.** Figure 18: Test Harness Context and Comparison to Forecast Opera [PITH_FULL_IMAGE:figures/full_fig_p016_18.png] view at source ↗

read the original abstract

Model-Based Systems Engineering (MBSE) is widely treated as the backbone of digital engineering, with languages such as the Systems Modeling Language (SysML) providing the means to capture system structure, behaviour, and verification intent. Yet once verification moves to hardware, the system model is routinely left behind. Domain-specific simulation environments, model transformations, and bespoke tool integrations take over, and the model that began as the authoritative reference drifts out of sync with the implementation it was meant to govern. This paper introduces the SysML Hardware Interface Architecture (SHIA), which keeps an executable SysML model directly inside the verification loop, exchanging messages with physical hardware without intermediate transformation chains, co-simulation platforms, or broker-mediated plugins. SHIA is realised through a SysML side server, written in embedded C++ within IBM Rhapsody, and a hardware side server running on a Raspberry Pi, together establishing a bidirectional link between the digital model and the physical system. A logic gate case study demonstrates the approach end-to-end, from hardware model construction and prototype assembly to test harness design, behavioural statechart control, and staged verification of each component before integration. The integrated system exchanged messages correctly in both directions, and Karnaugh map comparison between the SysML-generated and hardware-generated outputs showed zero discrepancy. The result shows that, when paired with a suitable interface, SysML need not remain a static description that informs downstream tools; it can serve as the executable layer through which hardware behaviour is stimulated, observed, and verified. The work demonstrates a route to model-governed verification and a shorter digital thread between system architecture and the hardware that realises it.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Desk Editor's Note private letter to a colleague

SHIA shows a working direct server link from Rhapsody SysML to Raspberry Pi hardware for a single logic gate, but the demo is too narrow to support broader claims about keeping models authoritative in verification.

read the letter

The main takeaway is that the authors built and ran a bidirectional messaging setup between an executable SysML model in IBM Rhapsody and physical hardware on a Raspberry Pi, using custom embedded C++ servers on each side. They report correct message exchange in both directions and exact output match on a basic logic gate via Karnaugh map comparison. That direct-interface approach without co-simulation or model transformation is the concrete new piece relative to the prior work they cite in the abstract. It is a practical engineering step for anyone already inside MBSE workflows who wants the SysML model to stay in the verification loop rather than being sidelined once hardware appears. The end-to-end case study covers model construction, prototype build, statechart control, and staged testing, which gives a clear picture of how the pieces fit together for this small example. The implementation details are light, but the reported result is straightforward and reproducible in principle for the same narrow setup. The soft spot is the scope. Everything rests on one logic-gate demonstration. There are no timing measurements, no tests with concurrent statechart elements, no checks for message ordering under load, and no discussion of how the custom protocol would hold up across tool versions or different hardware platforms. The stress-test note is right on this point: without those checks, it is hard to know whether synchronization or drift becomes an issue once the behavior gets more complex. The paper does not claim generality beyond the prototype, so the limitation is not hidden, but it does cap how far the result can be taken. This is the kind of paper that would interest MBSE practitioners and tool integrators who already use Rhapsody and need a short digital thread to hardware. A reader looking for a reusable architecture or formal guarantees would find it thin. It deserves a serious referee because the implementation is real and the problem it targets is common, even if the current evidence is limited to one case. I would send it out for review with the expectation that the authors add at least one more complex example and basic timing or error-handling data.

Referee Report

2 major / 2 minor

Summary. The manuscript introduces the SysML Hardware Interface Architecture (SHIA), which uses custom servers (embedded C++ in IBM Rhapsody on the model side and a Raspberry Pi on the hardware side) to enable direct bidirectional message exchange between an executable SysML model and physical hardware. It demonstrates the approach end-to-end via a logic-gate case study, reporting correct message exchange in both directions and zero output discrepancy as confirmed by Karnaugh-map comparison, with the goal of keeping the SysML model inside the verification loop without intermediate transformations or co-simulation.

Significance. If the direct-interface approach generalizes, it would be a useful contribution to model-based systems engineering by shortening the digital thread and reducing model drift during hardware verification. The explicit end-to-end prototype with exact matching on a simple case provides a concrete, reproducible demonstration of feasibility using standard tools.

major comments (2)

[Case Study] Case Study section: the demonstration is restricted to a single basic logic gate. No tests or measurements are reported for concurrent statechart behaviors, multiple signals, message queuing, clock skew, or protocol stability under load, which are required to substantiate the central claim that SHIA reliably keeps the model inside the verification loop for general SysML models.
[Architecture and Implementation] Architecture and Implementation sections: the paper describes the two servers but supplies no details on the custom protocol, error handling, timing, or synchronization mechanisms. This omission is load-bearing for assessing whether the bidirectional link avoids drift or errors beyond the narrow prototype.

minor comments (2)

[Abstract] The abstract states that 'staged verification of each component' was performed, but the main text does not enumerate or detail these stages, reducing clarity on the verification process.
[Introduction] Consider adding a brief related-work subsection contrasting SHIA with existing co-simulation or broker-based MBSE-hardware integrations to better situate the contribution.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive feedback and for recognizing the potential of SHIA to shorten the digital thread in model-based systems engineering. We respond to each major comment below and describe the revisions we will incorporate.

read point-by-point responses

Referee: [Case Study] Case Study section: the demonstration is restricted to a single basic logic gate. No tests or measurements are reported for concurrent statechart behaviors, multiple signals, message queuing, clock skew, or protocol stability under load, which are required to substantiate the central claim that SHIA reliably keeps the model inside the verification loop for general SysML models.

Authors: We agree that the case study is limited to a single logic gate and does not include tests for concurrent statecharts, multiple signals, queuing, clock skew, or load stability. The manuscript presents the logic-gate prototype as an end-to-end feasibility demonstration rather than a comprehensive validation across all SysML behaviors. In revision we will add an explicit limitations subsection that acknowledges these gaps and outlines how the architecture could be extended to statechart concurrency and multi-signal scenarios. We maintain that the zero-discrepancy result on the implemented prototype supports the core claim of direct model-hardware exchange, while generalization to arbitrary SysML models remains future work. revision: partial
Referee: [Architecture and Implementation] Architecture and Implementation sections: the paper describes the two servers but supplies no details on the custom protocol, error handling, timing, or synchronization mechanisms. This omission is load-bearing for assessing whether the bidirectional link avoids drift or errors beyond the narrow prototype.

Authors: We acknowledge that the current manuscript lacks sufficient detail on the custom protocol, error handling, timing assumptions, and synchronization. In the revised version we will insert a dedicated subsection that specifies the message format (including headers and payloads), error-detection method (checksum plus retransmission), timing model (Rhapsody execution cycle versus Raspberry Pi loop), and synchronization via request-acknowledge handshakes. These additions will allow readers to evaluate drift avoidance beyond the reported prototype. revision: yes

Circularity Check

0 steps flagged

No circularity: empirical demonstration of implemented architecture

full rationale

The paper presents a descriptive account of the SHIA architecture, its implementation via custom servers in Rhapsody and on Raspberry Pi, and an end-to-end case study on a single logic gate. The central result (correct bidirectional message exchange with zero discrepancy via Karnaugh map comparison) is obtained directly from the physical integration and testing process rather than from any equations, fitted parameters, predictions, or self-citations that reduce the outcome to prior inputs by construction. No derivation chain exists; the work is self-contained as an engineering demonstration.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

This is an applied engineering architecture paper; it introduces no free parameters, mathematical axioms, or new postulated entities.

pith-pipeline@v0.9.0 · 5609 in / 1071 out tokens · 46872 ms · 2026-05-13T01:34:26.966729+00:00 · methodology

discussion (0)

Reference graph

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