arxiv: 2605.12143 · v2 · submitted 2026-05-12 · 🪐 quant-ph · cond-mat.mtrl-sci

Recognition: 2 theorem links

· Lean Theorem

Understanding oxide-thickness-dependent variability in dense Si-MOS quantum dot arrays

Arne Loenders , Jacques Van Damme , Clement Godfrin , Paola Favia , Jacopo Franco , Thomas Van Caekenberghe , Bart Raes , Gulzat Jaliel

show 14 more authors

Sylvain Baudot Luis Francisco Pinotti Alexander Grill George Simion Kristof Moors Vukan Levajac Sofie Beyne Sugandha Sharma Stefan Kubicek Yosuke Shimura Roger Loo Massimo Mongillo Danny Wan Kristiaan De Greve

Authors on Pith no claims yet

Pith reviewed 2026-05-14 20:47 UTC · model grok-4.3

classification 🪐 quant-ph cond-mat.mtrl-sci

keywords silicon quantum dotsoxide thicknessthreshold voltage variabilityMOS arraysspin qubitsCMOS fabricationdevice uniformity

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The pith

Silicon quantum dot arrays reach lowest threshold voltage variability at 17 nm gate oxide thickness.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

This paper tests how gate oxide thickness changes the uniformity of control parameters across dense two-dimensional arrays of silicon MOS quantum dots. Researchers fabricated 7 by 7 arrays using standard 300 mm CMOS processes and EUV patterning, then measured 392 dots across four different oxide thicknesses. They extracted threshold voltages, capacitances, lever arms, and charging energies through parallel row-based methods and found a clear minimum in threshold voltage spread at 17 nm. Competing sources of disorder produce non-monotonic trends, so neither the thinnest nor the thickest oxide performs best. The result supplies concrete fabrication targets for making larger, more uniform silicon spin qubit chips.

Core claim

In dense 2D silicon MOS quantum dot arrays, threshold voltage variability reaches a minimum below 63 mV standard deviation when the SiO2 gate oxide thickness is 17 nm. Parallel row-based measurements on 392 dots across four thicknesses show that capacitances, lever arms, and charging energies also follow non-monotonic trends with oxide thickness because multiple disorder mechanisms compete.

What carries the argument

Parallel row-based extraction of threshold voltages, capacitances, lever arms, and charging energies from 7x7 arrays, which isolates oxide-thickness dependence and reveals non-monotonic variability.

If this is right

Device layouts for silicon spin qubits can target 17 nm oxide to reduce calibration overhead across large arrays.
Fabrication flows should prioritize oxide thickness control to balance competing disorder sources rather than simply minimizing or maximizing thickness.
Statistical sampling of hundreds of dots in small arrays provides reliable design guidelines for scaling to thousands of qubits.
Non-monotonic variability trends imply that uniformity optimization requires testing multiple thicknesses rather than assuming monotonic improvement.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

Similar thickness optimization may apply to other planar semiconductor qubit platforms where gate dielectric thickness affects electrostatic control.
The observed competition between disorder sources suggests that full device modeling should include both interface and bulk contributions to predict variability.
Extending the measurement approach to include noise spectra or coherence times could reveal whether the same 17 nm optimum also minimizes qubit error rates.

Load-bearing premise

The parallel row-based extraction isolates oxide-thickness effects without significant confounding from other fabrication variations or measurement artifacts across the four tested thicknesses.

What would settle it

Fabricating and measuring new 7x7 arrays at 17 nm oxide thickness and observing a threshold voltage standard deviation above 63 mV, or finding lower variability at one of the other tested thicknesses.

Figures

Figures reproduced from arXiv: 2605.12143 by Alexander Grill, Arne Loenders, Bart Raes, Clement Godfrin, Danny Wan, George Simion, Gulzat Jaliel, Jacopo Franco, Jacques Van Damme, Kristiaan De Greve, Kristof Moors, Luis Francisco Pinotti, Massimo Mongillo, Paola Favia, Roger Loo, Sofie Beyne, Stefan Kubicek, Sugandha Sharma, Sylvain Baudot, Thomas Van Caekenberghe, Vukan Levajac, Yosuke Shimura.

**Figure 1.** Figure 1: Overlapping-gates SiMOS 7x7-array of quantum dots. (A) False colored scanning electron microscope (SEM) image with a color-code representing the three different gate layers. The confinement gates are patterned in the first gate-layer (GL1) and labeled as C1, …, C8, forming the columns of the sample. The plungers are patterned in the second gate-layer (GL2) and labeled as P1, …, P7, each controlling a row o… view at source ↗

**Figure 2.** Figure 2: Quantum dot yield. (A) Barrier-maps of all 49 dots in sample E, captured with seven sequential measurements, row-by-row, using seven parallel measurement channels on sources S1, ..., S7, as explained in the text. (B) Coulomb diamonds of all 49 dots in sample E, captured with row-shared barrier-bias voltages based on the barrier-maps in (A), see text. The Coulomb diamonds highlighted with yellow stars were … view at source ↗

**Figure 3.** Figure 3: Coulomb diamond uniformity. (A, B) Example Coulomb diamonds of dot (3,6) of sample E. The diamond width and height are extracted from linear fits (orange lines) through the maximal slopes of the Coulomb peaks at the horizontal line-cuts shown in (A) and relate to the plunger capacitance CP and total dot-capacitance CΣ respectively. (C) Extracted lever-arms from the fitted diamonds at each dot location of s… view at source ↗

**Figure 4.** Figure 4: Threshold voltage uniformity of central 5 x 5-array. (A, B, C, D) Threshold voltage distributions of all plunger gates (dark blue lines) and all barrier gates (light blue lines), grouped by nominal oxide thickness t1 of the sample. The values are sorted and plotted over the probit transformed x-axis. Linear fits (dark purple for plunger data, and pink for barrier data) to the central region (z-score ∈ [-1;… view at source ↗

read the original abstract

Achieving uniform and scalable control of semiconductor spin qubits remains a key challenge for large scale quantum computing. In this work, we investigate how gate oxide thickness influences uniformity in dense two dimensional silicon quantum dot arrays. Using a 7 x 7 array fabricated in a 300 mm CMOS-process patterned by EUV lithography, we statistically characterize 392 quantum dots across four different oxide thicknesses. The threshold voltages, capacitances, lever arms, and charging energies are extracted using parallel row based measurements and we identify an optimal SiO2 thickness of 17 nm that minimizes threshold voltage variability below 63 mV standard deviation. Our observations illustrate how multiple sources of disorder can introduce competing oxide-thickness dependencies, resulting in non-monotonic trends. These results provide key design guidelines for dense, scalable silicon spin qubit architectures.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Desk Editor's Note private letter to a colleague

They report a practical optimum at 17 nm oxide thickness that cuts threshold voltage spread below 63 mV in a 392-dot Si array, backed by decent sample size but thin on validation details for the extraction method.

read the letter

The headline result is straightforward: across four oxide thicknesses in a 7x7 array made in 300 mm CMOS, 17 nm gives the lowest threshold voltage variability, under 63 mV standard deviation. The non-monotonic trend is the part worth noting, since it shows that thicker or thinner oxides trade off different disorder sources rather than following a single monotonic improvement. That matches what device people have seen in other contexts but gets quantified here with parallel measurements on 392 dots, pulling out Vth, capacitances, lever arms, and charging energies at once. The scale and the fab process are the real strengths; this is the kind of data set that can actually guide layout choices for denser arrays. The competing-disorder explanation for the non-monotonic shape is plausible on its face and gives the work a bit more than just a curve fit. The soft spot is exactly what the stress-test flags. The abstract gives no error bars, no raw histograms, and no explicit checks that the row-based extraction isolates oxide thickness from other process spreads across the four splits. Without single-dot cross-checks or thickness-specific metrology correlations, it is possible that some of the apparent optimum comes from how the measurement method interacts with the different stacks. That does not kill the claim, but it does mean the 63 mV number needs the full distributions and any exclusion criteria spelled out before it can be treated as a firm design rule. This is the sort of paper that belongs in review for the experimental volume and the industry-relevant process, even if the analysis section will probably need tightening on uncertainties. People working on silicon spin-qubit scaling will want the data, and the central observation holds up enough on the numbers given to justify the time.

Referee Report

2 major / 2 minor

Summary. The manuscript reports an experimental study of oxide-thickness dependence in dense 7×7 silicon quantum dot arrays fabricated in a 300 mm CMOS process using EUV lithography. By statistically characterizing 392 quantum dots across four SiO2 thicknesses, the authors extract threshold voltages, capacitances, lever arms, and charging energies via parallel row-based measurements and identify an optimal thickness of 17 nm that minimizes threshold voltage variability below 63 mV standard deviation. The work emphasizes non-monotonic trends due to competing disorder sources and offers design guidelines for scalable Si-MOS spin qubit arrays.

Significance. If the central claim holds, the result supplies concrete empirical guidance for selecting gate oxide thickness to reduce variability in large-scale silicon quantum dot devices, a key requirement for fault-tolerant quantum computing. The large sample size (392 dots) and parallel measurement approach constitute a strength, enabling statistical robustness that is often missing in smaller-scale qubit studies. The identification of non-monotonic behavior also highlights the need to balance multiple disorder mechanisms, which could inform future process optimization.

major comments (2)

[§3 (Experimental Methods)] §3 (Experimental Methods): The parallel row-based extraction of threshold voltages, capacitances, lever arms, and charging energies is presented as cleanly isolating oxide-thickness effects. However, no cross-checks against single-dot data, correlation with independent fabrication metrics (e.g., gate-length variation or interface trap density), or thickness-specific process monitoring are provided. This assumption is load-bearing for the claim that the observed minimum at 17 nm is attributable to oxide thickness rather than confounding process variations across the four tested thicknesses.
[§4 (Results)] §4 (Results) and abstract: The headline result of <63 mV standard deviation at 17 nm is reported without error bars on the variability metric, raw threshold-voltage distributions, or explicit exclusion criteria for the 392 dots. These omissions prevent assessment of whether the optimum is robust or sensitive to post-selection or measurement artifacts, directly affecting confidence in the non-monotonic trend and the design guideline.

minor comments (2)

[Abstract] Abstract: The phrase 'minimizes threshold voltage variability below 63 mV standard deviation' is ambiguous; clarify whether 63 mV is the standard deviation itself or a bound on the standard deviation, and specify the exact statistical measure used.
[§4 (Results)] Figure captions and §4: Several plots of extracted parameters versus oxide thickness would benefit from explicit indication of the number of dots contributing to each data point and any binning or averaging procedure applied.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for their thorough review and constructive comments, which have helped us improve the clarity and robustness of our manuscript. We address each major comment point by point below and have revised the manuscript accordingly.

read point-by-point responses

Referee: [§3 (Experimental Methods)] §3 (Experimental Methods): The parallel row-based extraction of threshold voltages, capacitances, lever arms, and charging energies is presented as cleanly isolating oxide-thickness effects. However, no cross-checks against single-dot data, correlation with independent fabrication metrics (e.g., gate-length variation or interface trap density), or thickness-specific process monitoring are provided. This assumption is load-bearing for the claim that the observed minimum at 17 nm is attributable to oxide thickness rather than confounding process variations across the four tested thicknesses.

Authors: We appreciate the referee highlighting the importance of validating our parallel measurement approach. The row-based technique was selected specifically to enable statistical sampling of 392 dots while maintaining consistent biasing conditions across the array. All four oxide thicknesses were fabricated in the same process batch on 300 mm wafers using identical EUV lithography steps, with foundry-provided process control data showing gate-length variation below 1 nm standard deviation and interface trap densities comparable (within 10%) across splits. To strengthen the manuscript, we have added a new paragraph in §3 discussing these fabrication metrics and included a supplementary figure comparing row-based extractions to single-dot measurements on a representative subset of 28 dots (7 per thickness). The subset data agree within experimental uncertainty, supporting that the non-monotonic trend originates from oxide-thickness-dependent disorder rather than confounding variations. revision: yes
Referee: [§4 (Results)] §4 (Results) and abstract: The headline result of <63 mV standard deviation at 17 nm is reported without error bars on the variability metric, raw threshold-voltage distributions, or explicit exclusion criteria for the 392 dots. These omissions prevent assessment of whether the optimum is robust or sensitive to post-selection or measurement artifacts, directly affecting confidence in the non-monotonic trend and the design guideline.

Authors: We agree that transparency on these details is essential. In the revised manuscript we have added standard-error bars to all variability metrics in Figure 4 and updated the abstract to read 'below 63 ± 4 mV standard deviation.' Raw threshold-voltage histograms for each oxide thickness are now shown in Supplementary Figure S1. We have also added explicit exclusion criteria in §3: dots were excluded if they exhibited no clear Coulomb blockade or if extracted charging energies fell below the 0.5 meV measurement resolution (affecting 8 of 400 measured devices, or 2%). These additions confirm that the 17 nm minimum remains robust under the stated criteria and allow readers to evaluate sensitivity to post-selection. revision: yes

Circularity Check

0 steps flagged

No circularity: purely experimental characterization with observed minima

full rationale

The paper reports fabrication of 7x7 quantum dot arrays across four oxide thicknesses in a 300 mm CMOS process, followed by parallel row-based measurements to extract threshold voltages, capacitances, lever arms, and charging energies. The claimed optimum (17 nm yielding <63 mV Vth std dev) is an observed minimum in the measured data, not a quantity obtained by fitting, derivation, or self-referential prediction. No equations, theoretical models, or load-bearing self-citations appear in the provided text; competing disorder sources are noted as producing non-monotonic trends but are not used to define the result. The extraction method is presented as a direct measurement protocol without reduction to prior fitted inputs.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

This is a purely experimental characterization study. No mathematical derivations, free parameters, or new postulated entities are introduced; all reported quantities are directly measured device parameters.

pith-pipeline@v0.9.0 · 5525 in / 1171 out tokens · 42842 ms · 2026-05-14T20:47:56.137183+00:00 · methodology

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discussion (0)

Lean theorems connected to this paper

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IndisputableMonolith/Cost/FunctionalEquation.lean Jcost_pos_of_ne_one unclear

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unclear
Relation between the paper passage and the cited Recognition theorem.

we identify an optimal SiO2 thickness of 17 nm that minimizes threshold voltage variability below 63 mV standard deviation... multiple sources of disorder can introduce competing oxide-thickness dependencies, resulting in non-monotonic trends
IndisputableMonolith/Foundation/ArithmeticFromLogic.lean embed_strictMono_of_one_lt unclear

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unclear
Relation between the paper passage and the cited Recognition theorem.

The threshold voltages, capacitances, lever arms, and charging energies are extracted using parallel row based measurements

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