arxiv: 2605.12217 · v1 · submitted 2026-05-12 · 💻 cs.AR · cs.AI

Recognition: no theorem link

Heterogeneous SoC Integrating an Open-Source Recurrent SNN Accelerator for Neuromorphic Edge Computing on FPGA

Michelangelo Barocci , Vittorio Fra , Enrico Macii , Gianvito Urgese

Authors on Pith no claims yet

Pith reviewed 2026-05-13 04:19 UTC · model grok-4.3

classification 💻 cs.AR cs.AI

keywords heterogeneous SoCrecurrent spiking neural networksneuromorphic acceleratorFPGA implementationedge computingonline learningRISC-VReckOn

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The pith

Heterogeneous FPGA SoC integrates open-source recurrent SNN accelerator and matches silicon accuracy for neuromorphic edge computing.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

This paper presents a heterogeneous System-on-Chip on FPGA that incorporates the ReckOn recurrent spiking neural network accelerator alongside RISC-V and ARM processors. The design aims to bring efficient, low-power neuromorphic computation to edge devices as a more accessible alternative to custom silicon fabrication. Validation comes from porting the taped-out ReckOn design to FPGA and confirming matching classification accuracy along with physical implementation traits. Additional experiments demonstrate the system's online learning ability on a Braille digit classification dataset. Such an approach could lower barriers for developing and testing neuromorphic hardware.

Core claim

The authors establish that their heterogeneous SoC, which integrates the open-source ReckOn accelerator with the X-HEEP RISC-V microcontroller and Zynq ARM processor, faithfully reproduces the accuracy and characteristics of the original silicon-taped-out ReckOn when implemented on FPGA, while also enabling online learning for neuromorphic tasks like Braille digit recognition.

What carries the argument

The integration of ReckOn accelerator operations managed by traditional processors in a heterogeneous SoC on Zynq Ultrascale FPGA.

If this is right

The FPGA implementation allows direct comparison of accuracy with the silicon version.
Online learning capabilities are demonstrated on the Braille digit dataset.
This setup provides a flexible platform for neuromorphic edge computing without tape-out costs.
Equivalence in physical characteristics supports reliable prototyping.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

This validation method could encourage more open-source neuromorphic designs to be tested on FPGAs first.
The approach might extend to other SNN architectures for broader edge AI applications.
Potential reduction in development time and cost for neuromorphic systems.

Load-bearing premise

The FPGA implementation of the taped-out ReckOn design accurately mirrors the behavior and metrics of the actual silicon chip without notable discrepancies.

What would settle it

A mismatch in classification accuracy or physical implementation characteristics between the FPGA and silicon versions of ReckOn would disprove the equivalence.

Figures

Figures reproduced from arXiv: 2605.12217 by Enrico Macii, Gianvito Urgese, Michelangelo Barocci, Vittorio Fra.

**Figure 1.** Figure 1: Logic Blocks-level schematic of ReckOn 2.2 X-HEEP X-HEEP [14] is an FPGA-synthesizable open source4 microcontroller based on RISC-V cores such as the CV32E20, CV32E40P and the CV32E40X. It has been conceived to offer flexible support for external accelerators and to be extended with custom IPs through dedicated interfaces such as the CORE-V-XIF and the Extendible Accelerator InterFace (XAIF) that use the O… view at source ↗

**Figure 2.** Figure 2: The firmware leverages the Hardware Abstraction Layer (HAL) functions [PITH_FULL_IMAGE:figures/full_fig_p005_2.png] view at source ↗

**Figure 3.** Figure 3: Left: FSM state diagram of the AER decoder in the implementation with X-HEEP. Right: I/O connection of the AER decoder subsystem. In [PITH_FULL_IMAGE:figures/full_fig_p006_3.png] view at source ↗

**Figure 4.** Figure 4: System-level schematic of the ARM-controlled architecture. The dashed [PITH_FULL_IMAGE:figures/full_fig_p008_4.png] view at source ↗

**Figure 5.** Figure 5: Left: FSM state diagram of the AER decoder in the implementation with the ARM cores, Right: Detailed I/O connection of the AER decoder subsystem with the AXI layer and ReckOn. 4 Results We synthesized our architectures targeting the XC7Z020 programmable chip, demonstrating the feasibility of performing on-the-edge machine learning applications on low-end hardware. The following subsections report the deta… view at source ↗

**Figure 6.** Figure 6: Per-epoch accuracy during training and validation of the binary naviga [PITH_FULL_IMAGE:figures/full_fig_p012_6.png] view at source ↗

**Figure 7.** Figure 7: Per-epoch accuracy during training and validation of the RSNN imple [PITH_FULL_IMAGE:figures/full_fig_p013_7.png] view at source ↗

**Figure 8.** Figure 8: Per-epoch accuracy during training and validation of the RSNN imple [PITH_FULL_IMAGE:figures/full_fig_p013_8.png] view at source ↗

read the original abstract

The growing popularity of Spiking Neural Networks (SNNs) and their applications has led to a significant fast-paced increase of neuromorphic architectures capable of mimicking the spike-based data processing typical of biological neurons. The efficient power consumption and parallel computing capabilities of the SNNs lead researchers towards the development of digital accelerators, which exploit such features to bring fast and low-power computation on edge devices. The spread of digital neuromorphic hardware however is slowed down by the prohibitive costs that the silicon tape out of circuits brings, that's why targeting Field Programmable Gate Arrays (FPGAs) could represent a viable alternative, offering a flexible and cost-effective platform for implementing digital neuromorphic systems and helping the spread of open-source hardware designs. In this work we present an heterogeneous System-on-Chip (SoC) where the operations of ReckOn, a Recurrent SNN accelerator, are managed through the integration with traditional processors. These include the RISC-V-based, open-source microcontroller X-HEEP and the ARM processor featured in Zynq Ultrascale systems. We validate our design by reproducing the classification results through the implementation on FPGA of the taped-out version of ReckOn in order to check the equivalence of the accuracy and the characteristics in terms of physical implementation. In a second set of experiments, we evaluate the online learning capability of the solution in classifying a subset of the Braille digit dataset recently used to compare neuromorphic frameworks and platforms.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Desk Editor's Note private letter to a colleague

The paper builds a working FPGA heterogeneous SoC around the ReckOn recurrent SNN accelerator with X-HEEP and Zynq cores and adds online learning runs on Braille digits, but the physical equivalence claim to the original ASIC does not hold.

read the letter

The core of this paper is a concrete FPGA implementation that wires the ReckOn accelerator into a heterogeneous SoC using the open-source X-HEEP RISC-V microcontroller and the ARM core on Zynq Ultrascale. They also run a second set of experiments showing online learning on a subset of the Braille digit dataset. That combination of integration and learning test is the new piece relative to earlier ReckOn work. The reproduction of classification accuracy on the FPGA version is a straightforward and useful check that the port preserves logical behavior. The open-source angle and the avoidance of another tape-out cost are practical points that matter for edge neuromorphic prototyping. The integration appears functional enough to support those results. The main weakness sits in the validation statement. The abstract says the FPGA version checks equivalence for both accuracy and physical implementation characteristics. Accuracy and spike behavior can be matched with bit-accurate execution. Physical numbers cannot. FPGA LUT and routing overhead changes power, area, and timing by large factors compared with the taped-out silicon, and the description gives no scaling model, calibrated post-PAR estimates, or side-by-side characterization to bridge the gap. Without that, the physical-equivalence part of the claim is unsupported. The online learning results are on a narrow dataset slice, so they show feasibility more than broad capability. This paper is aimed at groups building FPGA-based neuromorphic systems or open-source SoCs who need a working example of accelerator-plus-processor integration. It has enough system-level substance and empirical checks to deserve referee time, even though the equivalence wording needs tightening or removal. I would send it to review with a request to clarify the physical metrics section.

Referee Report

1 major / 1 minor

Summary. The paper presents a heterogeneous SoC on FPGA integrating the open-source ReckOn recurrent SNN accelerator with the RISC-V X-HEEP microcontroller and the ARM processor on Zynq Ultrascale devices. It claims validation by porting the taped-out ASIC version of ReckOn to FPGA to reproduce classification results and verify equivalence in both accuracy and physical implementation characteristics (power, area, timing). A second experiment demonstrates online learning on a subset of the Braille digit dataset.

Significance. If the core integration and accuracy reproduction hold, the work provides a practical, open-source FPGA platform for recurrent SNN acceleration that lowers barriers to neuromorphic edge computing by avoiding ASIC tape-out costs. The explicit use of standard open-source processors (X-HEEP) and a real-world online-learning task on Braille data adds concrete utility for heterogeneous neuromorphic systems.

major comments (1)

[Abstract] Abstract: The validation statement asserts that the FPGA port of the taped-out ReckOn 'check[s] the equivalence of the accuracy and the characteristics in terms of physical implementation.' Physical metrics (power, area, critical-path delay) cannot be equivalent between FPGA and ASIC; FPGA LUT/routing overhead systematically inflates dynamic power by 5-20× and alters timing. No scaling models, calibrated post-PAR power estimates, or separate ASIC-vs-FPGA characterization tables are referenced, leaving the physical-equivalence half of the claim unsupported and load-bearing for the stated validation goal.

minor comments (1)

The abstract and validation description would benefit from explicit numerical metrics (accuracy delta, power numbers, resource utilization) rather than qualitative statements of 'reproducing the classification results.'

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for the constructive feedback on our manuscript. We address the single major comment point-by-point below, agreeing that the abstract wording requires clarification regarding physical implementation metrics.

read point-by-point responses

Referee: [Abstract] Abstract: The validation statement asserts that the FPGA port of the taped-out ReckOn 'check[s] the equivalence of the accuracy and the characteristics in terms of physical implementation.' Physical metrics (power, area, critical-path delay) cannot be equivalent between FPGA and ASIC; FPGA LUT/routing overhead systematically inflates dynamic power by 5-20× and alters timing. No scaling models, calibrated post-PAR power estimates, or separate ASIC-vs-FPGA characterization tables are referenced, leaving the physical-equivalence half of the claim unsupported and load-bearing for the stated validation goal.

Authors: We agree with the referee that direct numerical equivalence of physical metrics (power, area, timing) between the FPGA port and the original ASIC is not possible or claimed, due to inherent FPGA overheads in LUTs, routing, and power. The manuscript's intent was to port the taped-out ReckOn design to FPGA to (1) reproduce classification accuracy results as a functional correctness check of the hardware port and (2) report the resulting FPGA-specific physical implementation characteristics (resource utilization, achieved frequency, power on the target device) for the heterogeneous SoC. The abstract wording is imprecise and could be read as implying cross-technology equivalence, which was not our intention and is unsupported. We will revise the abstract to state that we reproduce the accuracy results to validate the port and separately present the FPGA implementation metrics without any equivalence claim to the ASIC. No scaling models or ASIC-FPGA comparison tables exist in the paper because none were performed; the focus remains on the open-source heterogeneous FPGA platform. This change will be incorporated in the revised manuscript. revision: yes

Circularity Check

0 steps flagged

No circularity: empirical hardware integration and validation only

full rationale

The paper presents a heterogeneous SoC design integrating the existing ReckOn recurrent SNN accelerator with RISC-V and ARM processors on FPGA, followed by empirical validation through FPGA implementation of the taped-out ASIC version to reproduce classification accuracy on datasets like Braille digits. No mathematical derivations, predictions, fitted parameters, ansatzes, or self-citation load-bearing steps are present. The central claim is direct reproduction and measurement, which is self-contained and externally falsifiable via bit-accurate execution and physical metrics on the target platform. No reduction of any result to its own inputs by construction occurs.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

This is a hardware implementation and validation paper with no mathematical derivations; it relies on existing components (ReckOn accelerator, X-HEEP microcontroller, Zynq platform) without introducing new free parameters, axioms, or invented entities.

pith-pipeline@v0.9.0 · 5569 in / 1014 out tokens · 90179 ms · 2026-05-13T04:19:58.188623+00:00 · methodology

discussion (0)

Reference graph

Works this paper leans on

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