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arxiv: 2605.15638 · v1 · pith:ILNMSBVXnew · submitted 2026-05-15 · 💻 cs.AR · cs.SE

ITHICA: Intra-Thread Instruction Checking Approach for Defect-Induced Silent Data Corruptions

Ioanna Vavelidou , Subho S. Banerjee , Eric X. Liu , Mike Fuller , Subhasish Mitra , Caroline Trippel This is my paper

Pith reviewed 2026-05-19 19:49 UTC · model grok-4.3

classification 💻 cs.AR cs.SE
keywords silent data corruptiondefect detectionfunctional testingCPU reliabilityinstruction duplicationhyperscale serversintra-thread checkingsilent errors
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The pith

Intra-thread instruction duplication detects 39% more defective servers by catching inconsistent defect errors.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper presents ITHICA as a way to automatically convert any program into a functional test for silicon defects that cause silent data corruptions. It works by adding checks that duplicate the same instruction inside one thread and compare the results. The method rests on the observation that the worst defects make an instruction produce different outputs for identical inputs depending on the surrounding execution context. This lets existing industrial programs, datacenter workloads, and libraries serve as stronger tests. Evaluation across thousands of servers shows the new checks find 39% more defective machines than native checks in the same programs and surface new patterns of defect behavior.

Core claim

ITHICA transforms arbitrary programs into tests for defect-induced silent data corruptions by inserting intra-thread, instruction-level error checks that primarily use instruction duplication and output comparison. The central insight is that the most pernicious defects cause inconsistent errors: two executions of the same instruction within the same thread, given the same inputs, can produce different architectural outputs depending on the execution context in which they run. This enables identification of affected instructions upon error detection. When applied to industrial hyperscaler test programs, datacenter workloads, and common libraries and run on over 3,000 CPU servers, the ITHICA-

What carries the argument

Intra-thread instruction duplication and output comparison that exploits inconsistent errors to turn programs into tests and flag affected instructions.

If this is right

  • ITHICA checks derived from baseline industrial programs detect 39% more defective servers than native checks within the same tests.
  • Datacenter workloads and common libraries can be turned into functional tests for defect-induced errors.
  • Affected instructions are identified when an error is detected during test execution.
  • New observations about defect behavior emerge that differ from conclusions in prior hyperscaler fleet studies.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same duplication idea could be tried on GPUs or other accelerators where execution context might also trigger inconsistent faults.
  • Automated pipelines that insert these checks could become routine for screening new hardware batches before deployment.
  • Defect models used in reliability analysis may need to treat error behavior as context-dependent rather than fixed.

Load-bearing premise

The most pernicious defects cause inconsistent errors such that two executions of the same instruction within the same thread, given the same inputs, can produce different architectural outputs depending on the execution context.

What would settle it

Running duplicated instructions from an ITHICA test on a server already known to produce silent data corruptions and checking whether the two executions with identical inputs always yield identical outputs; consistent outputs would undermine the inconsistent-error premise.

Figures

Figures reproduced from arXiv: 2605.15638 by Caroline Trippel, Eric X. Liu, Ioanna Vavelidou, Mike Fuller, Subhasish Mitra, Subho S. Banerjee.

Figure 1
Figure 1. Figure 1: Classification of how hardware er￾rors can manifest as three types of architec￾tural errors [6, 45] (§3.1). ITHICA explicitly detects pernicious inconsistent errors and im￾plicitly detects unresponsive errors. stimuli to logic circuits and inspect their outputs, leveraging fault models and test metrics for systematically generating scan tests [25, 28, 47, 49, 73, 76, 79, 81]. Functional testing complements… view at source ↗
Figure 2
Figure 2. Figure 2: Given an input program (<name>.cpp), ITHICA applies one or more transformations—implemented in this paper for LLVM IR— configured with some BlockSize and Interleaving, and outputs a functional test (<name>-ITHICA). Part two of our insight is that faults that induce inconsistent errors are harder to detect (more pernicious) than those that induce consistent errors. This is because consistent errors can be e… view at source ↗
Figure 3
Figure 3. Figure 3: EDR for different CC-ITHICA tests (with block size and interleaving of 1) and CC in DPool (D1–D14). Each triplet reports results for ITHICA (Ith), Native (Nat), and program crashes with no detection (Cr). For Ith and Nat, the subset of executions that crashed after a detection is shown in parentheses. D6* is uniquely detected by Arith for interleaving of 8 (§7.3) [PITH_FULL_IMAGE:figures/full_fig_p007_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Server detections across all CC-ITHICA runs in both pools. 6.1 Testing on the DPool First, to compare CC-ITHICA to CC, we run eight functional tests on each DPool server. Seven are CC-ITHICA tests obtained by ap￾plying its four main transformations (§4.1) and three combinations thereof (Arith+Mem, Arith+MemDiv, Arith+MemDiv+Br) on CC, all with block size and interleaving set to 1. The eighth is the origina… view at source ↗
Figure 5
Figure 5. Figure 5: shows the distribution of failing instructions and their average error frequencies across all CC-ITHICA tests run in the DPool with a block size of 1 and an interleaving of 1, except D6, which is uniquely detected at interleaving of 8 (§7.3). A “failing instruction” denotes one that exhibits an incorrect output; it does not imply a particular defective hardware unit, as discussed in §7.5. Cases where no sp… view at source ↗
Figure 6
Figure 6. Figure 6: Impact of interleaving and block size on EDR for each DPool server (D1 to D14), for CC-Arith. The top row shows the effect of varying interleaving (m=max, length of the basic block), while the bottom row shows the effect of varying block size (d=dep, length of instruction dependency chain). The rightmost panels show the average EDR across all servers. ITHICA Pass Arith (Block Size) Mem MemDiv Br (1) (2) (4… view at source ↗
Figure 7
Figure 7. Figure 7: Normalized execution frequency of failing opcodes for servers (columns) uniquely detected by one ITHICA program. Or￾ange indicates the detecting program; gray indicates non-detecting programs executing the same opcode. tests, we select the most frequently failing one [PITH_FULL_IMAGE:figures/full_fig_p011_7.png] view at source ↗
Figure 9
Figure 9. Figure 9: Failing instruction type combinations across ITHICA tests. Bar height: number of servers with errors in that combination. Bar segments: average per-server breakdown of errors by instruction type. Pie chart: same breakdown aggregated across all servers. electrical state (beyond architectural control, as discussed in §3.3) contribute to the manifestation of defect-induced errors. Finding 8: Reproduction of d… view at source ↗
Figure 10
Figure 10. Figure 10: Comparison of SiliFuzz, CC and ITHICA tests, across all commonly tested servers. Unique server detections for each test are shown in parentheses. hardware components, none of which is visible at the ISA-level. Moreover, the compiler’s mapping of LLVM IR to assembly, and the hardware’s mapping of assembly to micro-ops and micro-ops to functional units, introduce microarchitectural execution path non-determ… view at source ↗
read the original abstract

Hyperscaler reports of silent data corruptions (SDCs), presumed to be caused by silicon manufacturing defects, have motivated the development of functional tests for detecting defective CPUs. We present ITHICA, an approach for automatically generating functional tests for defect-induced errors from arbitrary programs by inserting intra-thread, instruction-level error checks, primarily leveraging instruction duplication and output comparison. Our key insight is that the most pernicious defects cause inconsistent errors: two executions of the same instruction within the same thread, given the same inputs, can produce different architectural outputs depending on the execution context in which they run. By exploiting this insight, ITHICA enables arbitrary programs to serve as tests and identifies affected instructions upon error detections. We use ITHICA to transform industrial hyperscaler test programs (our baseline), datacenter workloads, and common libraries into functional tests, and evaluate them on over 3,000 CPU servers. ITHICA error checks detect 39% more defective servers than native checks within the ITHICA tests derived from our baseline programs, and enable novel findings on defect behavior that challenge conclusions drawn by prior hyperscaler fleet studies.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The paper introduces ITHICA, an approach to automatically convert arbitrary programs into functional tests for defect-induced silent data corruptions (SDCs) by inserting intra-thread instruction-level checks, primarily via duplication of instructions and comparison of their architectural outputs. The core insight is that the most pernicious manufacturing defects produce inconsistent errors, such that the same instruction executed twice within the same thread on identical inputs can yield different outputs depending on execution context. The method is applied to industrial baseline test programs, datacenter workloads, and common libraries; these transformed tests are run on over 3,000 CPU servers. The evaluation reports that ITHICA checks detect 39% more defective servers than the native checks already present in the baseline-derived tests and yields new observations on defect behavior that challenge prior hyperscaler fleet studies.

Significance. If the attribution of observed inconsistencies to manufacturing defects is substantiated, the work would offer a practical, low-overhead way to leverage existing production programs for defect screening at hyperscale, potentially improving SDC mitigation and prompting re-examination of earlier fleet-study conclusions. The scale of the real-hardware deployment (thousands of servers) constitutes a concrete strength and supports reproducibility of the detection-rate measurements.

major comments (2)
  1. [Abstract] Abstract and evaluation description: the 39% improvement in defective-server detections is presented as a central quantitative result, yet the manuscript provides no independent ground truth (physical failure analysis, controlled fault injection, or orthogonal detection method) to confirm that the additional inconsistencies are caused by permanent manufacturing defects rather than transient faults, environmental variation, or microarchitectural nondeterminism. This attribution is load-bearing for both the percentage claim and the challenge to prior studies.
  2. [Evaluation] Methods and evaluation sections: the assumption that defects produce context-dependent inconsistent outputs for identical instructions and inputs is used to justify turning arbitrary programs into tests via duplication/comparison, but no validation experiments or controls are described that would rule out other sources of intra-thread output variation. Without such evidence the extra detections cannot be unambiguously credited to defects.
minor comments (2)
  1. [Abstract] Abstract: the phrase 'over 3,000 CPU servers' should be replaced by the exact count and a brief statement of selection criteria.
  2. [Throughout] Notation: ensure consistent use of 'SDC' after its first definition and clarify whether 'native checks' refers to existing hardware mechanisms or to the baseline program's own assertions.

Simulated Author's Rebuttal

2 responses · 1 unresolved

We thank the referee for their constructive comments and the opportunity to clarify aspects of our work. We address each major comment below and have revised the manuscript where feasible to strengthen the attribution of results to manufacturing defects.

read point-by-point responses

  1. Referee: [Abstract] Abstract and evaluation description: the 39% improvement in defective-server detections is presented as a central quantitative result, yet the manuscript provides no independent ground truth (physical failure analysis, controlled fault injection, or orthogonal detection method) to confirm that the additional inconsistencies are caused by permanent manufacturing defects rather than transient faults, environmental variation, or microarchitectural nondeterminism. This attribution is load-bearing for both the percentage claim and the challenge to prior studies.

    Authors: We acknowledge that direct ground truth such as physical failure analysis would provide stronger confirmation. However, such analysis is impractical at the scale of over 3,000 production servers due to cost, time, and the need to maintain fleet availability. We instead rely on the repeatability of inconsistencies across repeated executions on the same servers and the context-dependent error pattern, which aligns with known defect behaviors cited in the paper. Transient faults and environmental factors are mitigated by our experimental design of multiple runs per test. We will add a dedicated paragraph in the evaluation section discussing alternative explanations and why the observed patterns are most consistent with permanent defects. revision: partial

  2. Referee: [Evaluation] Methods and evaluation sections: the assumption that defects produce context-dependent inconsistent outputs for identical instructions and inputs is used to justify turning arbitrary programs into tests via duplication/comparison, but no validation experiments or controls are described that would rule out other sources of intra-thread output variation. Without such evidence the extra detections cannot be unambiguously credited to defects.

    Authors: The assumption draws from established CPU defect literature on intermittent and context-sensitive errors, which we reference. To strengthen this, we will include new control experiments in the revised evaluation: running the duplicated instruction sequences on a set of known-good servers to quantify baseline variation from microarchitectural sources, and reporting that detected inconsistencies are persistent rather than sporadic. This supports crediting the additional detections to defects while acknowledging that complete isolation of all nondeterministic sources remains challenging without hardware-level instrumentation. revision: yes

standing simulated objections not resolved
  • Independent physical failure analysis or controlled fault injection at hyperscale to provide definitive ground truth for all detected servers

Circularity Check

0 steps flagged

No significant circularity; empirical hardware results independent of self-referential inputs

full rationale

The paper presents ITHICA as a method to generate tests from arbitrary programs by exploiting an assumed key insight on defect-induced inconsistent errors. The central quantitative claim (39% more detections) is obtained by executing the generated tests on over 3,000 real CPU servers and comparing against native checks within the same tests. No equations, fitted parameters, or derived predictions are described that reduce the reported detection improvement to a quantity defined by the paper's own inputs or prior self-citations. The evaluation uses external hardware benchmarks, satisfying the criterion for a self-contained result against external measurements. A minor score of 2 accounts for the normal presence of an unverified modeling assumption without any reduction of outputs to inputs by construction.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The central claim rests on the domain assumption that pernicious defects produce inconsistent outputs on repeated identical instructions within one thread; no free parameters or invented entities are described.

axioms (1)
  • domain assumption Most pernicious defects cause inconsistent errors where the same instruction with same inputs produces different outputs depending on execution context
    This is explicitly stated as the key insight enabling the test generation approach.

pith-pipeline@v0.9.0 · 5748 in / 1188 out tokens · 40744 ms · 2026-05-19T19:49:05.506826+00:00 · methodology

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