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arxiv: 2606.11076 · v1 · pith:42MWNF7Dnew · submitted 2026-06-09 · 💻 cs.AR · quant-ph

Coset Ensemble Decoder for Quantum Error Correction with Algorithm-Hardware Co-Design

Pith reviewed 2026-06-27 11:19 UTC · model grok-4.3

classification 💻 cs.AR quant-ph
keywords quantum error correctiondecodercoset ensembleFPGAalgorithm-hardware co-designunion-findminimum-weight perfect matchingsurface code
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The pith

Coset ensemble decoding approximates coset-level maximum-likelihood decoding while cutting FPGA resource use for quantum error correction.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper develops a decoder for quantum error correction that improves on standard Union-Find and Minimum-Weight Perfect Matching methods by explicitly using logically equivalent cosets. At the algorithm level it generates an ensemble of consistent candidate error patterns, aggregates their information, and applies compression steps to keep the added work small. At the hardware level it replaces spatial replication of resources with temporal reuse on an FPGA, adding targeted memory and mapping optimizations to handle concurrent access. The result is a design whose accuracy-latency curve lies above prior decoders under circuit-level depolarizing noise while using substantially fewer LUTs.

Core claim

Coset ensemble decoding extends Union-Find by exploring an ensemble forest of coset-consistent candidates and aggregating them to approximate coset-level maximum-likelihood decoding; reverse-order elimination and lossless graph compression keep the overhead low. A domain-specific FPGA architecture reuses the same hardware blocks over time instead of scaling them with code distance, supported by multi-bank hashing and hierarchical ID mapping. Under circuit-level depolarizing noise this co-design yields a superior accuracy-latency trade-off and reduces LUT consumption by up to 8.2 times relative to reported Union-Find implementations, with the number of candidates serving as a tunable knob.

What carries the argument

Coset ensemble decoding: an algorithmic extension of Union-Find that generates and aggregates multiple coset-consistent error candidates to approximate coset-level maximum-likelihood decoding, paired with temporal resource reuse on FPGA.

If this is right

  • The accuracy-latency operating point lies above that of both MWPM and Union-Find decoders under circuit-level depolarizing noise.
  • FPGA LUT consumption drops by up to 8.2 times compared with published Union-Find decoder implementations.
  • Resource usage no longer grows proportionally with code distance because of temporal rather than spatial replication.
  • The candidate count acts as an explicit knob that lets the same hardware serve different fault-tolerant workload requirements.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Larger code distances become feasible on a fixed FPGA fabric because the architecture avoids distance-proportional replication.
  • The open-source release permits direct porting to other FPGA families and direct benchmarking against future decoder proposals.
  • The same ensemble-plus-compression pattern could be tested on other surface-code variants or color codes without changing the hardware template.

Load-bearing premise

The accuracy improvement from the ensemble approximation to coset-level maximum-likelihood decoding is not offset by the extra latency introduced on the target FPGA hardware.

What would settle it

A side-by-side measurement, on the same FPGA, of logical error rate versus decoding latency for a distance-5 surface code under circuit-level depolarizing noise, showing whether the coset ensemble decoder falls below the Union-Find curve.

Figures

Figures reproduced from arXiv: 2606.11076 by Bo Yuan, Giulio Bassanino, Hongxiang Fan, Jubo Xu, Paul H. J. Kelly, Qianzhou Wang, Shuang Liang, Wayne Luk, Yidong Zhou, Yuncheng Lu, Zhiwen Mo.

Figure 1
Figure 1. Figure 1: Layout of surface code (left) and syndrome behavior with correspond [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Two matching examples: the blue (left) belongs to coset 1 with [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Latency breakdown for code distances 3 (left) and 11 (right) on a two [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Graph compression. C. Lossless Graph Compression To reduce the additional exploration efforts introduced by Sec. III-A, we apply structure-preserving reductions with smaller complexity. The example in [PITH_FULL_IMAGE:figures/full_fig_p006_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Two-stage hardware architecture: a fully pipelined clustering engine (outside the light-yellow region) feeds the post-clustering modules (inside the [PITH_FULL_IMAGE:figures/full_fig_p007_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Multi-bank hashing distributes 7-vertex neighborhood to distinct [PITH_FULL_IMAGE:figures/full_fig_p007_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: Comparison of memory-cell update counts between the straightforward [PITH_FULL_IMAGE:figures/full_fig_p008_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: Logical error rate comparison among MWPM-based decoders, UF-based decoders, and our decoder. [PITH_FULL_IMAGE:figures/full_fig_p009_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: Logical error rate of MWPM, UF, and our decoder ( [PITH_FULL_IMAGE:figures/full_fig_p009_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: Decoding latency per decoding task (d syndrome rounds), compared with state-of-the-art decoders. 0 1 2 0 2 4 6 Probability Density p95=0.47 p99=0.65 p95=1.34p99=2.08 Ours After Opt. Before Opt. 0 1 2 0.0 0.5 1.0 p95=1.67 p99=2.27 Micro-Blossom Micro-Blossom 0.0 0.5 1.0 0 5 10 15 p95=0.56 p99=0.82 Helios Helios 0 1 2 3 Latency (µs) 0 1 2 3 Probability Density p95=0.65 p99=0.90 p95=2.12 p99=3.09 After Opt. … view at source ↗
Figure 11
Figure 11. Figure 11: Decoding latency distribution per d-round task at p=0.0005, for code distance 7 (top) and 9 (bottom). Helios’s per-iteration floor, producing the 3–5× advantage at d=3. As d grows, the two curves converge near d=7– 9, with our design still ahead in lower-p settings at d=7; beyond this range, Helios’s sublinear scaling becomes more favorable on pure latency. Our design targets a resource￾efficient latency/… view at source ↗
Figure 12
Figure 12. Figure 12: System infidelity comparison with SOTA decoders. [PITH_FULL_IMAGE:figures/full_fig_p011_12.png] view at source ↗
Figure 13
Figure 13. Figure 13: FPGA resource usage vs. code distance d. Filled markers denote full Vivado synthesis (d=3, 9, 15); open markers are estimates. The shaded region indicates extrapolation beyond measured data. term linearly while leaving the shared clustering engine and voting part unchanged. TABLE I HARDWARE RESOURCE COMPARISON. FOR FAIRER COMPARISON ACROSS DIFFERENT CODE DISTANCES, HELIOS AND QUEKUF ARE SHOWN WITH BOTH TH… view at source ↗
Figure 14
Figure 14. Figure 14: Hardware latency breakdown before and after optimization. [PITH_FULL_IMAGE:figures/full_fig_p012_14.png] view at source ↗
Figure 15
Figure 15. Figure 15: Tunability analysis of our proposal. (a) Power-law model validation [PITH_FULL_IMAGE:figures/full_fig_p012_15.png] view at source ↗
Figure 16
Figure 16. Figure 16: Logical error rate comparison on the repetition code under a [PITH_FULL_IMAGE:figures/full_fig_p012_16.png] view at source ↗
Figure 17
Figure 17. Figure 17: Logical error rate (left) and the corresponding system infidelity [PITH_FULL_IMAGE:figures/full_fig_p012_17.png] view at source ↗
read the original abstract

Reliable large-scale quantum computation relies on fault-tolerant architectures, where quantum error correction (QEC) continuously extracts and decodes error syndromes in real time. A critical component in QEC is the decoder, a classical subsystem that must simultaneously deliver high logical accuracy and ultra-low latency. This paper presents a novel algorithm-hardware co-design that improves the accuracy-latency trade-off over existing approaches such as vanilla Minimum-Weight Perfect Matching (MWPM) and Union-Find (UF) decoders. At the algorithmic level, we introduce coset ensemble decoding, which improves UF decoding by explicitly exploiting logically equivalent cosets. Our method performs ensemble forest exploration to generate multiple coset-consistent candidates and aggregates them to approximate coset-level maximum-likelihood decoding. We further reduce computational and memory complexity via reverse-order elimination and lossless graph compression, without sacrificing accuracy. At the hardware level, we design a domain-specific architecture that temporally reuses resources, avoiding the code-distance-proportional resource growth in prior spatial architectures. Several optimizations, such as multi-bank memory hashing and hierarchical ID mapping, are proposed to mitigate pipeline stalls and memory conflicts under highly concurrent access patterns. Under a circuit-level depolarizing noise model, our co-design approach achieves a better accuracy-latency trade-off than prior MWPM- and UF-based decoders, while reducing FPGA LUT consumption by up to 8.2 times compared with reported UF-based decoder resources. The tunable candidate number further exposes a flexible design knob, enabling users to tailor decoding performance to the requirements of different fault-tolerant workloads. Our implementation is publicly available at https://github.com/IMSeonL/coset-ensemble-decoder.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The manuscript introduces coset ensemble decoding, an extension to Union-Find decoding that performs ensemble forest exploration over coset-consistent candidates, aggregates them to approximate coset-level maximum-likelihood decoding, and applies reverse-order elimination plus lossless graph compression. This is paired with a domain-specific FPGA architecture using temporal resource reuse, multi-bank memory hashing, and hierarchical ID mapping to avoid distance-proportional resource scaling. Under circuit-level depolarizing noise, the co-design is claimed to deliver a superior accuracy-latency trade-off versus MWPM and UF baselines while reducing LUT consumption by up to 8.2×, with candidate count as a tunable knob.

Significance. If the empirical accuracy-latency curves hold after accounting for hardware pipeline and memory overheads, the work supplies a concrete, resource-efficient decoder design for real-time QEC that could be relevant to near-term fault-tolerant architectures. The public code release aids reproducibility.

major comments (2)
  1. [Evaluation section] Evaluation section (results and figures): the central claim that ensemble exploration yields a net accuracy gain not erased by added per-syndrome latency on the temporally-reused architecture requires explicit demonstration via logical-error-rate versus latency curves (with error bars) for multiple candidate numbers under the circuit-level depolarizing model; without these, it remains unclear whether the reported improvement survives the hardware mapping.
  2. [§3] §3 (algorithm description): the claim that aggregation of coset-consistent candidates approximates coset-level ML needs a quantitative bound or ablation showing that reverse-order elimination preserves the accuracy advantage rather than introducing a systematic bias that cancels the gain.
minor comments (2)
  1. [Abstract] Abstract: the 8.2× LUT reduction is stated without identifying the exact baseline UF implementation, code distance, or resource numbers; adding these values would make the comparison immediately verifiable.
  2. [§3.1] Notation: the definition of 'coset-consistent candidates' and the aggregation rule should be stated with a short pseudocode block or equation to avoid ambiguity when readers compare against standard UF.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive comments, which help clarify the presentation of our accuracy-latency results and the justification for the algorithmic approximations. We address each major comment below and will revise the manuscript to incorporate the requested demonstrations and ablations.

read point-by-point responses
  1. Referee: [Evaluation section] Evaluation section (results and figures): the central claim that ensemble exploration yields a net accuracy gain not erased by added per-syndrome latency on the temporally-reused architecture requires explicit demonstration via logical-error-rate versus latency curves (with error bars) for multiple candidate numbers under the circuit-level depolarizing model; without these, it remains unclear whether the reported improvement survives the hardware mapping.

    Authors: We agree that explicit logical-error-rate versus latency curves with error bars, plotted for multiple candidate counts under the circuit-level depolarizing model, would strengthen the central claim. In the revised manuscript we will add these curves to the Evaluation section, generated from the same FPGA-mapped implementation, to show that the accuracy gain is preserved after hardware latency is accounted for. revision: yes

  2. Referee: [§3] §3 (algorithm description): the claim that aggregation of coset-consistent candidates approximates coset-level ML needs a quantitative bound or ablation showing that reverse-order elimination preserves the accuracy advantage rather than introducing a systematic bias that cancels the gain.

    Authors: We acknowledge the value of a quantitative check on reverse-order elimination. The revised manuscript will include an ablation study that compares logical error rates obtained with and without this step across representative noise strengths and candidate counts, thereby confirming that the elimination step does not erase the accuracy advantage of the ensemble aggregation. revision: yes

Circularity Check

0 steps flagged

No circularity; derivation is algorithmic and empirical

full rationale

The paper introduces coset ensemble decoding as an explicit algorithmic modification to UF decoding via ensemble forest exploration over coset-consistent candidates, followed by reverse-order elimination and lossless graph compression to approximate coset-level ML decoding. These steps are presented as concrete algorithmic changes with hardware co-design (temporal reuse, multi-bank hashing), not as equations or parameters that reduce to their own inputs. Claims of improved accuracy-latency trade-off rest on empirical results under circuit-level depolarizing noise, with no fitted inputs renamed as predictions, no self-definitional loops, and no load-bearing self-citations in the text. The derivation chain is therefore self-contained against external benchmarks.

Axiom & Free-Parameter Ledger

1 free parameters · 1 axioms · 0 invented entities

The central performance claim rests on the depolarizing noise model being representative and on the ensemble aggregation approximating maximum-likelihood decoding without introducing hidden fitting parameters beyond the tunable candidate count.

free parameters (1)
  • candidate number
    Tunable ensemble size that trades accuracy for latency; value not fixed in abstract.
axioms (1)
  • domain assumption Circuit-level depolarizing noise model accurately represents the dominant error processes in the target hardware.
    Invoked when reporting accuracy-latency results.

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