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arxiv: 2606.19119 · v1 · pith:WBSSHO3Dnew · submitted 2026-06-17 · 💻 cs.AR · cs.DC

PuDGhost: Experimental Analysis of Computation Result Corruption in Processing-using-DRAM Operations on Real DRAM Chips and Implications for Future Systems

Daichi Tokuda , \.Ismail Emir Y\"uksel , Tatsuya Kubo , Ataberk Olgun , Haocong Luo , Nisa Bostanci , Jikun Wang , A. Giray Ya\u{g}l{\i}k\c{c}{\i}
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Shinya Takamaeda-Yamazaki Onur Mutlu
This is my paper

Pith reviewed 2026-06-26 18:46 UTC · model grok-4.3

classification 💻 cs.AR cs.DC
keywords Processing-using-DRAMPuDSiMRADRAM interferencePuDGhostcomputation corruptionDDR4 characterizationrow activation
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The pith

Interference from non-activated rows and concurrent columns corrupts results in DRAM-based computation by up to 48 percent.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper establishes that Processing-using-DRAM operations relying on simultaneous multiple-row activation produce erroneous outputs when data in adjacent non-activated rows or in other concurrently active columns interferes with the intended computation. This violates the assumption that each column computes independently from its own operands alone. Characterization across 96 real DDR4 chips reveals two main interference sources quantified for random inputs, and the work evaluates hardware-level mitigations such as column screening and dedicated buffer rows. A sympathetic reader would care because the finding directly questions whether density-scaled DRAM can reliably support this computation paradigm without new safeguards.

Core claim

PuDGhost is an interference phenomenon in which a simultaneous multiple-row activation computation in one column yields incorrect results because of data stored in non-activated rows and data being computed in other columns under the same activation. Experiments on 96 DDR4 chips from 12 modules show that adjacent non-activated rows alter outputs by as much as 10 percent and concurrently computing columns alter outputs by as much as 48 percent for random inputs. The authors therefore propose and evaluate on real hardware a robust column-screening method and a compute-row layout that inserts dedicated rows between active compute rows.

What carries the argument

PuDGhost, the interference mechanism in simultaneous multiple-row activation (SiMRA) where non-participating rows and columns alter column outputs.

If this is right

  • Column screening can identify and avoid unreliable columns under PuDGhost conditions.
  • Inserting dedicated rows between compute rows reduces interference on real DDR4 chips.
  • Both mitigations raise overall PuD computation accuracy.
  • Future PuD systems require awareness of row and column interference at the architecture level.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Designers of denser future DRAM may need to add physical spacing or shielding between columns to preserve PuD reliability.
  • Software schedulers could be extended to avoid simultaneous activation of columns whose data patterns are known to interfere strongly.
  • The 10 percent and 48 percent figures suggest that error-correction overhead in PuD will be higher than previously modeled.

Load-bearing premise

The 96 DDR4 chips tested are representative of DRAM behavior in general and the observed corruption stems from the SiMRA mechanism rather than manufacturing variation or test artifacts.

What would settle it

Running the same SiMRA workloads on a fresh set of DRAM modules from additional manufacturers and finding zero measurable output corruption would falsify the claim that PuDGhost is a general phenomenon.

Figures

Figures reproduced from arXiv: 2606.19119 by A. Giray Ya\u{g}l{\i}k\c{c}{\i}, Ataberk Olgun, Daichi Tokuda, Haocong Luo, \.Ismail Emir Y\"uksel, Jikun Wang, Nisa Bostanci, Onur Mutlu, Shinya Takamaeda-Yamazaki, Tatsuya Kubo.

Figure 1
Figure 1. Figure 1: (a) Ideal MAJ3. (b) MAJ3 under PuDGhost. Ideally, as illustrated in Figure 1a, the MAJX result in each DRAM column is determined solely by the activated cells used as operands. With each column performing its own MAJX, each one of the many (e.g., 65536) DRAM columns acts as a computing unit, enabling the massive parallelism of PuD. We hypothesize that this ideal picture of PuD computations might be challen… view at source ↗
Figure 2
Figure 2. Figure 2: DRAM Organization. parallel computation within DRAM by leveraging the intrinsic analog operational properties of DRAM circuitry. Many PuD architectures perform computation through two primitives: 1) in-DRAM data copy from one row to another (RowCopy) using consecutive multiple-row activation [22,23,26,30,43,50,64], and 2) in-DRAM bitwise operations using simultaneous multiple￾row activation (SiMRA) [23,26,… view at source ↗
Figure 3
Figure 3. Figure 3: Our FPGA-based PuD testing infrastructure (DRAM [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Experimental setup for evaluating interference from non-activated rows. We define po1 as the fraction of output bits that equal logic-1 when SiMRA is executed with random inputs over the target columns. For example, if target columns cover all 64K columns in a bank and we collect 128 samples, po1 = 0.60 means that 60% of the 64K × 128 output bits are logic-1. We use po1 to quantify the effect of PuDGhost o… view at source ↗
Figure 5
Figure 5. Figure 5: Row-type characterization under controlled patterns. [PITH_FULL_IMAGE:figures/full_fig_p005_5.png] view at source ↗
Figure 8
Figure 8. Figure 8: (a) Column-local interference. (b) Adjacent-row in [PITH_FULL_IMAGE:figures/full_fig_p006_8.png] view at source ↗
Figure 6
Figure 6. Figure 6: Sensitivity to fraction of logic-1 in adjacent rows. [PITH_FULL_IMAGE:figures/full_fig_p006_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: Sensitivity to the data patterns in the adjacent rows. [PITH_FULL_IMAGE:figures/full_fig_p006_7.png] view at source ↗
Figure 13
Figure 13. Figure 13: Adjacent-row interference vs. temperature. Obsv. 9. Temperature has a small effect on interfer￾ence from non-activated adjacent rows. We observe no significant temperature dependence in adjacent-row interference. For example, with 8-row activation under pc = 1.0, the mean Norm. po1 remains at approximately 1.02 across all tested temperatures (50◦C–80◦C). 6. Interference from Columns that Concur￾rently Per… view at source ↗
Figure 11
Figure 11. Figure 11: illustrates the adjacent-row data patterns for the base￾line and all four combinations in a given random-input sample. For example, for (bitin, bitadj) = (1, 1), each column where the SiMRA input is logic-1 ( 1 ) has its corresponding adjacent￾row cell set to logic-1 ( 2 ), while the remaining adjacent-row cells retain the random base pattern. Because the random inputs differ across samples, the spatial d… view at source ↗
Figure 12
Figure 12. Figure 12: Input-dependent adjacent-row interference. [PITH_FULL_IMAGE:figures/full_fig_p007_12.png] view at source ↗
Figure 15
Figure 15. Figure 15: Sensitivity to the fraction of logic-1 in concurrently [PITH_FULL_IMAGE:figures/full_fig_p008_15.png] view at source ↗
Figure 16
Figure 16. Figure 16: shows the Norm. po1 distribution of the target columns (y-axis) for each pc value of the controlled cells (x￾axis), across different numbers of SiMRA rows (each subplot). Figure 16a shows results for the Opposite-Parity configuration, and Figure 16b for the Same-Parity configuration. 0.0 0.250.75 1.0 0.95 1.00 1.05 N o r m. p o 1 2-Row Activation 0.0 0.250.75 1.0 0.95 1.00 1.05 4-Row Activation 0.0 0.250.… view at source ↗
Figure 17
Figure 17. Figure 17: Inter-column interference vs. temperature [PITH_FULL_IMAGE:figures/full_fig_p008_17.png] view at source ↗
Figure 18
Figure 18. Figure 18: Time interval between writing data and SiMRA. 8.3. Broader Implications 8.3.1. Security Concerns for PuD Systems. PuDGhost ex￾poses two attack vectors in multi-tenant PuD environments 6We believe PuDGhost would manifest in any SiMRA-capable chip regard￾less of manufacturer or DRAM type, as PuDGhost is based on fundamental analog operational properties of DRAM (e.g., charge sharing) and DRAM array design (… view at source ↗
Figure 19
Figure 19. Figure 19: Compute row layouts in a 1024-row subarray with four compute rows: (a) contiguous layout, (b) isolation-row layout ensuring fixed adjacent-row data. Interleaved Layout with Isolation Rows. We propose a compute row layout where each compute row group is placed between rows with fixed data patterns, called isolation rows (Figure 19b). Isolation rows are initialized once with a fixed data pattern and refresh… view at source ↗
Figure 20
Figure 20. Figure 20: Evaluation of column screening methods. 10.2. Application-Level Study: GEMV Kernel We evaluate the application-level impact of PuDGhost and the effectiveness of our mitigations (§9.3, §9.4) using general matrix-vector multiplication (GEMV), one of the primary target workloads for PuD [40–42, 49, 211]. Experimental Setup. We execute GEMV kernels on real DRAM chips using MAJ3, following prior PuD GEMV imple… view at source ↗
Figure 21
Figure 21. Figure 21: Effect of PuDGhost and our solutions on GEMV. 10.3. PuDGhost’s Impact on SiMRA-based TRNG We demonstrate the risks of designing SiMRA-based TRNG without accounting for PuDGhost on real DRAM chips. SiMRA￾based TRNG exploits columns that exhibit non-deterministic outputs under fixed SiMRA input [44, 61, 67]. These columns, which we refer to as source columns, produce outputs that fluc￾tuate due to metastabi… view at source ↗
Figure 22
Figure 22. Figure 22: Impact of PuDGhost on the entropy of SiMRA-based TRNG for different numbers of SiMRA rows. 11. Related Work To our knowledge, this is the first experimental study demon￾strating that non-operand data affects PuD computation results on real DRAM chips. DRAM Read Disturbance. Many works experimentally char￾acterize read disturbance phenomena on real DRAM chips [65, 69, 81–84, 86–94, 150–158, 167]. RowHammer… view at source ↗
read the original abstract

Processing-using-DRAM (PuD) is a promising computation paradigm that alleviates frequent data movement between main memory and processing units by using each DRAM column as a computation engine via simultaneous multiple-row activation (SiMRA). Unfortunately, DRAM density scaling may hinder PuD's benefits: denser cell arrays bring rows and columns closer, making regular DRAM operations susceptible to noise and interference from neighboring cells. Yet no prior work investigates whether interference from rows or columns not intended to participate in computation can compromise PuD robustness. In this work, we reveal PuDGhost, an interference phenomenon where a PuD operation in a given column produces erroneous results due to interference from 1) data in non-activated DRAM rows and 2) data in other columns that compute concurrently under the same SiMRA operation. PuDGhost violates the ideal picture that each column's computation depends solely on its own operand data, threatening future PuD systems. We present the first extensive characterization of PuDGhost using 96 real DDR4 DRAM chips from 12 modules, quantifying these two interference sources under various conditions. Among our 15 new empirical observations, we highlight two major results: 1) data in adjacent non-activated rows affects SiMRA outputs by up to 10% for random inputs, and 2) data in concurrently computing columns affects SiMRA outputs by up to 48% for random inputs. Guided by these findings, we propose countermeasures across multiple layers of the PuD computing stack. Specifically, we evaluate on real DDR4 DRAM chips: 1) robust column screening that reduces the risk of using unreliable columns in the presence of PuDGhost, and 2) a compute row layout that mitigates PuDGhost via dedicated rows between compute rows. Our solutions greatly improve PuD computation accuracy and provide a foundation for robust future PuD systems.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The paper claims that Processing-using-DRAM (PuD) via simultaneous multiple-row activation (SiMRA) is susceptible to an interference phenomenon termed PuDGhost, in which data stored in non-activated adjacent rows corrupts SiMRA outputs by up to 10% and data in concurrently computing columns corrupts outputs by up to 48% for random inputs. These effects are quantified through an empirical study on 96 real DDR4 chips from 12 modules, yielding 15 observations; the work also evaluates two countermeasures (robust column screening and dedicated-row compute layout) on the same hardware.

Significance. If the measurements are reproducible and attributable to the claimed interference mechanism, the work is significant because it supplies the first large-scale real-hardware evidence that row/column proximity effects can undermine the correctness assumption of column-independent PuD computation. The scale of the evaluation (96 chips, 12 modules, 15 observations) and the concrete quantitative bounds constitute a useful data point for architects considering PuD. The paper also ships concrete, chip-validated mitigation strategies rather than purely theoretical proposals.

major comments (2)
  1. [Abstract and Characterization section] Abstract + Characterization section: the headline quantitative claims (adjacent-row interference up to 10%, concurrent-column interference up to 48%) rest on the premise that the observed corruption is caused by the SiMRA mechanism rather than manufacturing variation, voltage/temperature drift, or measurement artifacts. The provided text does not describe the isolation experiments, control patterns, or statistical tests used to rule out these confounds; without such detail the attribution remains the least-secured link in the central claim.
  2. [Characterization section] Characterization section: the paper reports results across 96 chips from 12 modules but does not state whether the 10% and 48% figures are worst-case, median, or mean values, nor whether they are consistent across all modules or driven by a subset of chips. This information is load-bearing for any claim about broader DRAM population behavior.
minor comments (2)
  1. [Abstract] The abstract states that 15 empirical observations are presented; a short enumerated list or table mapping each observation to the relevant figure or subsection would improve traceability.
  2. [Throughout] Notation for the two interference sources (non-activated rows vs. concurrent columns) should be introduced once with consistent abbreviations to avoid repeated descriptive phrases.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the detailed and constructive review. The comments identify areas where additional clarity on experimental controls and statistical reporting will strengthen the manuscript. We address each major comment below and will incorporate the requested details in the revised version.

read point-by-point responses

  1. Referee: [Abstract and Characterization section] Abstract + Characterization section: the headline quantitative claims (adjacent-row interference up to 10%, concurrent-column interference up to 48%) rest on the premise that the observed corruption is caused by the SiMRA mechanism rather than manufacturing variation, voltage/temperature drift, or measurement artifacts. The provided text does not describe the isolation experiments, control patterns, or statistical tests used to rule out these confounds; without such detail the attribution remains the least-secured link in the central claim.

    Authors: We agree that explicit documentation of the isolation methodology is essential for attributing the observed corruption to row/column interference under SiMRA. Our experimental design included repeated measurements at controlled voltages and temperatures, use of fixed all-0/all-1 patterns as baselines, and per-chip statistical aggregation to distinguish systematic interference from random variation. However, the current manuscript condenses these details. We will add a dedicated subsection in the Characterization section describing the control patterns, temperature/voltage sweeps, and statistical tests (including confidence intervals and outlier analysis) used to isolate the SiMRA-specific effects. revision: yes

  2. Referee: [Characterization section] Characterization section: the paper reports results across 96 chips from 12 modules but does not state whether the 10% and 48% figures are worst-case, median, or mean values, nor whether they are consistent across all modules or driven by a subset of chips. This information is load-bearing for any claim about broader DRAM population behavior.

    Authors: We agree that the nature of the reported maxima must be stated explicitly. The 10% (row) and 48% (column) figures are the maximum observed error rates across the full set of 96 chips and 12 modules for random inputs; every module exhibited the effect, though the peak magnitude varied by vendor and density. We will revise the text to clarify that these are worst-case values, and we will add median/mean statistics plus per-module consistency data to support claims about population behavior. revision: yes

Circularity Check

0 steps flagged

Purely empirical hardware characterization with no derivations or self-referential steps

full rationale

The paper reports direct measurements of interference on 96 real DDR4 chips. No equations, parameters, predictions, or derivation chains exist that could reduce to inputs by construction. Claims rest on experimental observations rather than any fitted model or self-citation load-bearing premise. This is the most common honest finding for measurement-driven hardware papers.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

Work rests on standard DRAM timing and activation assumptions rather than new parameters or entities.

axioms (1)
  • domain assumption Simultaneous multiple-row activation (SiMRA) produces column-wise computation whose result depends only on the activated rows' data in the absence of external interference
    This is the ideal picture the paper shows is violated; it is invoked as the baseline that PuDGhost breaks.

pith-pipeline@v0.9.1-grok · 5947 in / 1228 out tokens · 30639 ms · 2026-06-26T18:46:55.617941+00:00 · methodology

discussion (0)

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